JPH0990405A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPH0990405A JPH0990405A JP24347995A JP24347995A JPH0990405A JP H0990405 A JPH0990405 A JP H0990405A JP 24347995 A JP24347995 A JP 24347995A JP 24347995 A JP24347995 A JP 24347995A JP H0990405 A JPH0990405 A JP H0990405A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- tft
- lower gate
- gate electrodes
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、たとえばアクティ
ブマトリックス型液晶パネル（以下、ＡＭＬＣＤと称す
る）にマトリックス状に設けられた画素のオンオフを制
御するスイッチング素子として好適に用いられる薄膜ト
ランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor preferably used as a switching element for controlling ON / OFF of pixels provided in a matrix on an active matrix type liquid crystal panel (hereinafter referred to as AMLCD).
【０００２】[0002]
【従来の技術】近年、多結晶シリコン（以下、ｐ−Ｓｉ
と称する）を半導体層に用いた薄膜トランジスタ（以
下、ＴＦＴと称する）に関する研究が活発に行われてい
る。このｐ−Ｓｉ・ＴＦＴを上述した画素用のスイッチ
ング素子として用いたＡＭＬＣＤにおいては、ドライバ
回路を同一基板上に形成することが可能であり、コスト
低減、基板サイズの縮小化等の効果が期待できる。ま
た、上記ｐ−Ｓｉ・ＴＦＴにおいては、ゲート電極をマ
スクとしてイオン注入を行うことにより、ゲート電極と
ソース領域およびドレイン領域とを自己整合的に作製す
ることが可能となる。このため、ｐ−Ｓｉ・ＴＦＴを画
素のスイッチング素子として用いた場合に、画素電極と
ゲート電極との間の容量結合による画素信号の変動を抑
えることができる。2. Description of the Related Art In recent years, polycrystalline silicon (hereinafter referred to as p-Si
(Hereinafter, referred to as "TFT") as a semiconductor layer has been actively researched. In the AMLCD using the p-Si.TFT as the switching element for the pixel described above, the driver circuit can be formed on the same substrate, and effects such as cost reduction and substrate size reduction can be expected. . In the p-Si TFT, the gate electrode and the source region and the drain region can be self-aligned by performing ion implantation with the gate electrode as a mask. Therefore, when the p-Si.TFT is used as a pixel switching element, it is possible to suppress variation in the pixel signal due to capacitive coupling between the pixel electrode and the gate electrode.
【０００３】しかし、画素のスイッチング素子としてｐ
−Ｓｉ・ＴＦＴを用いた場合には、非晶質シリコン（以
下、ａ−Ｓｉ：Ｈと称する）を半導体層に用いたａ−Ｓ
ｉ：Ｈ・ＴＦＴに比べてオフ電流が高く、特に、ソース
−ドレイン電圧が高くなると、急激にオフ電流が増加す
るという問題がある。このような現象が生じる理由は、
ソースードレイン電圧が高くなると、ドレイン端の電界
強度が強くなって、欠陥準位を介したトンネル電流や熱
励起電流等が流れるためであると一般に説明されてい
る。However, p is used as a pixel switching element.
In the case of using -Si.TFT, a-S using amorphous silicon (hereinafter referred to as a-Si: H) for the semiconductor layer is used.
The off current is higher than that of the i: H.TFT, and in particular, when the source-drain voltage becomes higher, the off current sharply increases. The reason for this phenomenon is
It is generally explained that when the source-drain voltage becomes higher, the electric field strength at the drain end becomes stronger, and a tunnel current, a thermal excitation current, or the like flows through the defect level.
【０００４】この問題を解決するために、例えば図１０
に示すような複数のゲート電極２０５、２０６を有する
デュアルゲート構造のＴＦＴが提案されている（特公平
５−４４１９５号）。また、図１１に示すようなオフセ
ット領域またはＬＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ
Ｄｒａｉｎ）領域２１３ａを有するオフセット構造また
はＬＤＤ構造のＴＦＴが提案されている（特公平３−３
４６９９号）。さらに、図１２に示すようなデュアルゲ
ートのオフセット構造またはＬＤＤ構造のＴＦＴが提案
されている（特開平２−１３５７８０号）。尚、これら
の図において、２０１はガラス基板、２０２は絶縁膜、
２０３はチャンネル領域、２０４はゲート絶縁膜、２０
５および２０６はゲート電極、２０７は層間絶縁膜、２
０８および２０９はソース電極およびドレイン電極、２
１０、２１１および２１３はソース領域およびドレイン
領域、２１３ａはオフセット領域またはＬＤＤ領域を示
す。To solve this problem, for example, FIG.
A dual-gate structure TFT having a plurality of gate electrodes 205 and 206 as shown in (4) has been proposed (Japanese Patent Publication No. 5-44195). In addition, an offset region or an LDD (Lightly Doped) as shown in FIG.
A TFT having an offset structure or an LDD structure having a drain region 213a has been proposed (Japanese Patent Publication No. 3-3).
4699). Furthermore, a TFT having a dual-gate offset structure or LDD structure as shown in FIG. 12 has been proposed (Japanese Patent Laid-Open No. 2-135780). In these figures, 201 is a glass substrate, 202 is an insulating film,
203 is a channel region, 204 is a gate insulating film, 20
5 and 206 are gate electrodes, 207 is an interlayer insulating film, 2
08 and 209 are source and drain electrodes, 2
Reference numerals 10, 211 and 213 denote source and drain regions and 213a denotes an offset region or LDD region.
【０００５】このように複数のゲート電極２０５、２０
６を設けた構造では、ソース−ドレイン電圧が個々のゲ
ート電極に対応したＴＦＴに分割されるので、オフ電流
が低減される。また、オフセット領域またはＬＤＤ領域
２１３ａを設けた構造では、ソース−ドレイン電圧がオ
フセット領域またはＬＤＤ領域に分散されるので、電界
強度が減少してオフ電流が低減される。オフセット構造
またはＬＤＤ構造では、ソース−ドレイン抵抗が増大し
てオン電流が減少するという欠点もあるが、ｐ−Ｓｉ・
ＴＦＴでは移動度が高いので問題が生じない。As described above, the plurality of gate electrodes 205, 20
In the structure provided with 6, the source-drain voltage is divided into the TFTs corresponding to the individual gate electrodes, so that the off current is reduced. In the structure provided with the offset region or the LDD region 213a, the source-drain voltage is dispersed in the offset region or the LDD region, so that the electric field strength is reduced and the off current is reduced. The offset structure or the LDD structure has a drawback that the source-drain resistance increases and the on-current decreases, but p-Si.
Since the TFT has high mobility, no problem occurs.
【０００６】[0006]
【発明が解決しようとする課題】一般に、トップゲート
構造のＴＦＴには、基板裏面からの光入射により光伝導
が生じて、オフ電流が増加するという問題がある。従来
のａ−Ｓｉ：Ｈ・ＴＦＴでは、一般に逆スタガ構造が採
用されるので、ゲート電極が自動的に遮光膜となって、
問題は生じない。しかし、トップゲート構造を採用した
場合には、このような光入射によるオフ電流の増加とい
う問題が生じる。In general, a TFT having a top gate structure has a problem that photoconduction occurs due to light incident from the back surface of the substrate and the off current increases. In the conventional a-Si: H.TFT, an inverted stagger structure is generally adopted, so that the gate electrode automatically becomes a light-shielding film.
No problem. However, when the top gate structure is adopted, there is a problem that the off current increases due to such light incidence.
【０００７】この問題を解決するために、トップゲート
構造のＴＦＴでは、図１３に示すように、チャンネル領
域３０４の下側に、絶縁膜３０３を介してゲート電極３
０６よりも大きい形状の遮光膜３０２を形成することが
一般的に行われている。この場合は、プロセス温度の関
係から遮光膜として金属を用いることが多いので、図１
３および図１４に示すように、ソース領域およびドレイ
ン領域３１０、３１１と遮光膜３０２との間に寄生容量
３１２、３１３が発生する。このため、遮光膜３０２を
ゲートバスラインやソースバスライン等と接続すると、
バスラインの電圧変化がこの寄生容量を介して画素電圧
の変動をもたらすことになり、画像に悪影響を与えると
いう問題がある。尚、この図１３において、３０１はガ
ラス基板、３０２は遮光膜、３０３は絶縁膜、３０４は
チャンネル領域、３０５はゲート絶縁膜、３０６はゲー
ト電極、３０７は層間絶縁膜、３０８および３０９はソ
ース領域およびドレイン電極、３１０および３１１はソ
ース領域およびドレイン領域、３１２および３１３は寄
生容量を示す。In order to solve this problem, in the TFT having the top gate structure, as shown in FIG. 13, the gate electrode 3 is formed below the channel region 304 with the insulating film 303 interposed therebetween.
Generally, the light shielding film 302 having a shape larger than 06 is formed. In this case, a metal is often used as the light-shielding film because of the process temperature.
As shown in FIG. 3 and FIG. 14, parasitic capacitances 312 and 313 are generated between the source and drain regions 310 and 311 and the light shielding film 302. Therefore, if the light shielding film 302 is connected to a gate bus line, a source bus line, etc.,
There is a problem that a change in the voltage of the bus line causes a change in the pixel voltage via the parasitic capacitance, which adversely affects the image. In FIG. 13, 301 is a glass substrate, 302 is a light shielding film, 303 is an insulating film, 304 is a channel region, 305 is a gate insulating film, 306 is a gate electrode, 307 is an interlayer insulating film, and 308 and 309 are source regions. And drain electrodes, 310 and 311 indicate source and drain regions, and 312 and 313 indicate parasitic capacitances.
【０００８】本発明は、このような従来技術の課題を解
決すべくなされたものであり、光入射によるオフ電流の
増加を防ぐことができ、遮光膜による寄生容量が画像に
悪影響を及ぼすのを防ぐことができる薄膜トランジスタ
（ＴＦＴ）を提供することを目的とする。The present invention has been made to solve the above-mentioned problems of the prior art. It is possible to prevent an increase in off-current due to the incidence of light and prevent the parasitic capacitance due to the light-shielding film from adversely affecting the image. It is an object to provide a thin film transistor (TFT) that can be prevented.
【０００９】[0009]
【課題を解決するための手段】本発明の薄膜トランジス
タは、チャンネル領域の両側にソース領域とドレイン領
域とを有する半導体薄膜の該チャンネル領域を挟んで一
方側に、絶縁膜を介して２以上の上部ゲート電極が形成
され、他方側に絶縁膜を介して１以上の下部ゲート電極
が、各下部ゲート電極の両端部を相互に隣接する上部ゲ
ート電極の各々に対して重畳させて形成され、そのこと
により上記目的が達成される。A thin film transistor according to the present invention includes a semiconductor thin film having a source region and a drain region on both sides of a channel region, sandwiching the channel region on one side, and at least two upper portions with an insulating film interposed therebetween. A gate electrode is formed, and one or more lower gate electrodes are formed on the other side through an insulating film by overlapping both ends of each lower gate electrode with each of the upper gate electrodes adjacent to each other. The above object is achieved by the above.
【００１０】本発明の薄膜トランジスタにおいて、前記
半導体薄膜の前記上部ゲート電極とは重畳しない部分
に、前記ソース領域およびドレイン領域に導入されてい
る不純物と同じ導電型の不純物が該ソース領域およびド
レイン領域よりも低濃度に導入されている構成とするこ
とができる。In the thin film transistor of the present invention, an impurity of the same conductivity type as the impurities introduced into the source region and the drain region is formed in a portion of the semiconductor thin film which does not overlap with the upper gate electrode from the source region and the drain region. Can be configured to be introduced at a low concentration.
【００１１】本発明の薄膜トランジスタにおいて、前記
上部ゲート電極および下部ゲート電極が同一の信号線に
接続されている構成、または前記下部ゲート電極に一定
の電圧が印加されている構成とすることができる。In the thin film transistor of the present invention, the upper gate electrode and the lower gate electrode may be connected to the same signal line, or a constant voltage may be applied to the lower gate electrode.
【００１２】以下に、本発明の作用について説明する。The operation of the present invention will be described below.
【００１３】本発明にあっては、半導体薄膜を挟んで２
以上の上部ゲート電極と１以上の下部ゲート電極とが形
成され、各下部ゲート電極の両端部が相互に隣接する上
部ゲート電極の各々に対して重畳している。この構造に
より、ソース−ドレイン電圧が各々のゲート電極に対応
したＴＦＴに分散され、これによりオフ電流が低減され
る。In the present invention, the semiconductor thin film is sandwiched between the two
The above upper gate electrode and one or more lower gate electrodes are formed, and both ends of each lower gate electrode overlap with each other of the adjacent upper gate electrodes. With this structure, the source-drain voltage is distributed to the TFTs corresponding to the respective gate electrodes, thereby reducing the off current.
【００１４】また、ＭＩＳ型ＴＦＴでは、キャリアがゲ
ート電極に近い絶縁膜の界面に形成されるので、下部ゲ
ート電極で構成されるＴＦＴと、上部ゲート電極で構成
されるＴＦＴの間では、チャンネル領域の膜厚方向の中
央部が空乏化する。その結果、さらにオフ電流が低減さ
れる。In the MIS type TFT, carriers are formed at the interface of the insulating film close to the gate electrode, so that a channel region is formed between the TFT composed of the lower gate electrode and the TFT composed of the upper gate electrode. The central part in the film thickness direction of is depleted. As a result, the off current is further reduced.
【００１５】さらに、光が基板裏面から入射しても、下
部ゲート電極で構成されるＴＦＴが下部ゲート電極の陰
になるので、光電流の発生が抑えられる。Further, even if light is incident from the back surface of the substrate, the TFT composed of the lower gate electrode is behind the lower gate electrode, so that generation of photocurrent can be suppressed.
【００１６】また、上部ゲート電極とソース領域および
ドレイン領域とは自己整合的に形成でき、下部ゲート電
極はソース領域およびドレイン領域と重ならないので、
画素電極とゲート電極との容量結合による画素電圧の変
動が抑制される。Further, the upper gate electrode and the source region and the drain region can be formed in a self-aligned manner, and the lower gate electrode does not overlap the source region and the drain region.
Fluctuations in pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode are suppressed.
【００１７】半導体薄膜の上部ゲート電極とは重畳しな
い部分に、ソース領域およびドレイン領域と同じ導電型
の不純物を低濃度に導入すると、下部ゲート電極がオフ
レベルになった時に、半導体薄膜の下部ゲート電極上の
部分が空乏化され、さらにオフ電流の低減を図ることが
できる。このＬＤＤ領域は、上部ゲート電極をマスクと
して不純物導入を行うことにより、注入領域を正確に制
御できる。If impurities of the same conductivity type as those of the source region and the drain region are introduced into the portion of the semiconductor thin film which does not overlap with the upper gate electrode at a low concentration, when the lower gate electrode is turned off, the lower gate of the semiconductor thin film is turned on. The portion on the electrode is depleted, and the off current can be further reduced. In this LDD region, the implantation region can be accurately controlled by introducing impurities using the upper gate electrode as a mask.
【００１８】上部ゲート電極および下部ゲート電極は、
同一の信号線に接続してもよく、下部ゲート電極に一定
の電圧を印加してもよい。下部ゲート電極に一定の電圧
を印加する場合には、全体として最もオンオフ比が高く
なるように電圧を印加する。この場合、下部ゲート電極
と上部ゲート電極とを接続する必要が無い。The upper gate electrode and the lower gate electrode are
They may be connected to the same signal line, or a constant voltage may be applied to the lower gate electrode. When a constant voltage is applied to the lower gate electrode, the voltage is applied so that the on / off ratio becomes highest as a whole. In this case, it is not necessary to connect the lower gate electrode and the upper gate electrode.
【００１９】[0019]
【実施形態】以下、本発明の実施形態について、図面を
参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２０】本実施形態のＴＦＴは、例えば図１（ａ）
に示すように、ガラス基板１０１上に、チャンネル領域
１０４、ソース領域およびドレイン領域１１１、１１２
を有する半導体薄膜が形成され、その上下に、絶縁膜１
０３、１０５を介して上部ゲート電極１０６、１０７お
よび下部ゲート電極１０２が形成されている。下部ゲー
ト電極１０２はソース領域およびドレイン領域１１１、
１１２と重なっておらず、また、その一部は、隣接する
上部ゲート電極１０６、１０７と重なっている。その上
には、上部ゲート電極１０６、１０７を覆うように層間
絶縁膜１０８が形成され、絶縁膜１０５および層間絶縁
膜１０８に形成されたコンタクトホールを介して、ソー
ス電極およびドレイン電極１０９、１１０がソース領域
およびドレイン領域１１１、１１２に接続されている。The TFT of this embodiment has, for example, the structure shown in FIG.
, The channel region 104, the source region and the drain region 111, 112 are formed on the glass substrate 101.
Is formed on the upper and lower sides of the semiconductor thin film.
Upper gate electrodes 106 and 107 and lower gate electrode 102 are formed via 03 and 105. The lower gate electrode 102 includes a source region and a drain region 111,
It does not overlap 112, and a part thereof overlaps the adjacent upper gate electrodes 106 and 107. An interlayer insulating film 108 is formed thereon so as to cover the upper gate electrodes 106 and 107, and source and drain electrodes 109 and 110 are formed through contact holes formed in the insulating film 105 and the interlayer insulating film 108. It is connected to the source and drain regions 111 and 112.
【００２１】この構造によれば、従来の複数ゲート電極
を有するＴＦＴと同様に、ソース−ドレイン電圧が個々
のゲート電極に対応したＴＦＴに分割されるので、オフ
電流が低減される。According to this structure, similarly to the conventional TFT having a plurality of gate electrodes, the source-drain voltage is divided among the TFTs corresponding to the individual gate electrodes, so that the off current is reduced.
【００２２】本実施形態の構造をＭＩＳ型ＴＦＴに適用
した場合には、キャリアがそれぞれのゲート電極に近い
絶縁膜の界面に形成され、例えばＮｃｈ ＴＦＴのオフ
状態では、図１（ｂ）に示すように、正孔が絶縁膜１０
３、１０５とチャンネル領域１０４との界面に形成され
る。このため、中央の下部ゲート電極１０２で構成され
るＴＦＴと、両端の上部ゲート電極１０６、１０７で構
成されるＴＦＴの間で、チャンネル領域１０４の膜厚方
向の中央部１１３が空乏化する。その結果、膜厚分のオ
フセット領域が形成されることになり、さらにオフ電流
が低減される。また、本実施形態においては、図２
（ｃ）に示すように、光が基板裏面から入射する場合、
下部ゲート電極１０２で構成されるＴＦＴが下部ゲート
電極１０２の陰になる。このため、チャンネル１０４で
の正孔−電子対の発生が抑えられ、オフ電流の増加を防
ぐことができる。光が基板表面から入射する場合には、
従来のトップゲート構造のＴＦＴと同様に、上部ゲート
電極１０６、１０７により遮光することができる。When the structure of this embodiment is applied to a MIS type TFT, carriers are formed at the interface of the insulating film close to the respective gate electrodes. For example, in the off state of the Nch TFT, it is shown in FIG. 1 (b). As described above, holes are generated in the insulating film 10.
It is formed at the interface between the channel regions 104 and 104. Therefore, the central portion 113 in the film thickness direction of the channel region 104 is depleted between the TFT formed of the central lower gate electrode 102 and the TFT formed of the upper gate electrodes 106 and 107 at both ends. As a result, an offset region corresponding to the film thickness is formed, and the off current is further reduced. Further, in the present embodiment, FIG.
As shown in (c), when light enters from the back surface of the substrate,
The TFT composed of the lower gate electrode 102 is behind the lower gate electrode 102. Therefore, generation of hole-electron pairs in the channel 104 is suppressed, and an increase in off current can be prevented. When light enters from the substrate surface,
Like the conventional top gate structure TFT, the upper gate electrodes 106 and 107 can shield light.
【００２３】また、本実施形態においては、上部ゲート
電極１０５、１０６とソース領域およびドレイン領域１
１１、１１２とは自己整合的に形成することができ、か
つ、下部ゲート電極１０２はソース領域およびドレイン
領域１１１、１１２と重ならないので、画素電極とゲー
ト電極との容量結合による画素電圧の変動が抑制され、
画像への悪影響が少なくなる。Further, in this embodiment, the upper gate electrodes 105 and 106 and the source and drain regions 1 are formed.
11 and 112 can be formed in a self-aligned manner, and the lower gate electrode 102 does not overlap the source region and the drain region 111 and 112, so that the pixel voltage varies due to capacitive coupling between the pixel electrode and the gate electrode. Suppressed,
The adverse effect on the image is reduced.
【００２４】さらに、図２（ｄ）に示すように、半導体
薄膜の下部電極１０２上の部分１１４に、ソース領域お
よびドレイン領域１１１、１１２と同じ導電型の不純物
を低濃度に導入すると、下部ゲート電極１０２がオフレ
ベルになった時に、チャンネル領域１０４にソース領域
およびドレイン領域１１１、１１２と反対導電型のキャ
リアが発生するのを防ぐことができる。その結果、半導
体薄膜の下部ゲート電極１０２上の部分１１４を空乏化
して実質的に高抵抗とすることができ、オフ電流の低減
を図ることができる。また、従来のＬＤＤ構造と同様
に、ソース−ドレイン電圧がＬＤＤ領域に分散されこと
によっても、オフ電流が低減される。このＬＤＤ領域１
１４は、上部ゲート電極１０６、１０７をマスクとして
不純物導入を行うことにより、注入領域を正確に制御で
き、容易に作製することができる。上部ゲート電極１０
５、１０６および下部ゲート電極１０２は、同一の信号
線に接続して使用することもでき、下部ゲート電極１０
２に一定の電圧が印加されるようにしてもよい。下部ゲ
ート電極１０２に一定の電圧を印加する場合には、全体
として最もオンオフ比が高くなるような電圧を印加す
る。この場合、下部ゲート電極１０２と上部ゲート電極
１０５、１０６とを接続する必要が無いので、プロセス
の簡略化を図ることができる。Further, as shown in FIG. 2D, when impurities of the same conductivity type as the source and drain regions 111 and 112 are introduced into the portion 114 on the lower electrode 102 of the semiconductor thin film at a low concentration, the lower gate is formed. It is possible to prevent carriers of the opposite conductivity type from the source and drain regions 111 and 112 from being generated in the channel region 104 when the electrode 102 is turned off. As a result, the portion 114 of the semiconductor thin film on the lower gate electrode 102 can be depleted to have a substantially high resistance, and the off current can be reduced. Further, as in the conventional LDD structure, the off-current is reduced by distributing the source-drain voltage in the LDD region. This LDD region 1
By implanting impurities using the upper gate electrodes 106 and 107 as masks, the implantation region 14 can be controlled accurately and can be easily manufactured. Upper gate electrode 10
5, 106 and the lower gate electrode 102 can be used by connecting to the same signal line.
A constant voltage may be applied to 2. When a constant voltage is applied to the lower gate electrode 102, a voltage that has the highest on / off ratio as a whole is applied. In this case, since it is not necessary to connect the lower gate electrode 102 and the upper gate electrodes 105 and 106, the process can be simplified.
【００２５】ここでは、１つの下部ゲート電極１０２と
２つの上部ゲート電極１０５、１０６を有する構成につ
いて説明したが、下部ゲート電極が１以上で上部ゲート
電極が２以上の構成としてもよい。この場合にも、同様
の効果が得られることはもちろんである。また、Ｎｃｈ
ＴＦＴについて説明したが、Ｐｃｈ ＴＦＴについて
も同様である。Although the structure having one lower gate electrode 102 and the two upper gate electrodes 105 and 106 has been described here, the structure may be one or more lower gate electrodes and two or more upper gate electrodes. In this case as well, the same effect can be obtained. Also, Nch
Although the TFT has been described, the same applies to the Pch TFT.
【００２６】[0026]
【実施例】以下、本発明の具体的な実施例について説明
する。EXAMPLES Specific examples of the present invention will be described below.
【００２７】（実施例１）図４（ｇ）に本実施例１のＴ
ＦＴの断面図を示す。(Embodiment 1) FIG.
The cross section of FT is shown.
【００２８】このＴＦＴは、ガラス基板４０１上に、ｐ
−Ｓｉからなる半導体薄膜４０４が形成され、その上下
に、絶縁膜４０３、４０５を介して上部ゲート電極４０
６、４０６および下部ゲート電極４０２が形成されてい
る。下部ゲート電極４０２はソース領域およびドレイン
領域と重なっておらず、また、その一部は、隣接する上
部ゲート電極４０６、４０６と重なっている。その上に
は、上部ゲート電極４０６、４０６を覆うように層間絶
縁膜４０８が形成され、絶縁膜４０５および層間絶縁膜
４０８に形成されたコンタクトホールを介して、ソース
電極およびドレイン電極４０９、４０９がソース領域お
よびドレイン領域に接続されている。This TFT is formed on a glass substrate 401 by p
A semiconductor thin film 404 made of —Si is formed, and the upper gate electrode 40 is formed above and below the semiconductor thin film 404 via insulating films 403 and 405.
6, 406 and the lower gate electrode 402 are formed. The lower gate electrode 402 does not overlap with the source region and the drain region, and a part thereof overlaps with the adjacent upper gate electrodes 406 and 406. An interlayer insulating film 408 is formed thereon so as to cover the upper gate electrodes 406, 406, and source and drain electrodes 409, 409 are formed through contact holes formed in the insulating film 405 and the interlayer insulating film 408. It is connected to the source region and the drain region.
【００２９】このＴＦＴの作製方法を図３および図４に
従って説明する。A method of manufacturing this TFT will be described with reference to FIGS.
【００３０】まず、図３（ａ）に示すように、ガラス基
板４０１上にＴａ膜を成膜し、これをパターニングして
下部ゲート電極４０２を形成する。First, as shown in FIG. 3A, a Ta film is formed on a glass substrate 401, and the Ta film is patterned to form a lower gate electrode 402.
【００３１】次に、図３（ｂ）に示すように、厚み３０
０ｎｍのＳｉＯ2膜をＡＰＣＶＤ（常圧化学気相成長）
法により成膜し、下部ゲート電極４０２に対応したゲー
ト絶縁膜４０３を形成する。Next, as shown in FIG. 3B, the thickness 30
APCVD (Normal pressure chemical vapor deposition) of 0 nm SiO 2 film
Then, a gate insulating film 403 corresponding to the lower gate electrode 402 is formed.
【００３２】続いて、図３（ｃ）に示すように、厚み５
０ｎｍのｐ−Ｓｉ膜をＬＰＣＶＤ（減圧化学気相成長）
法により成膜し、これをパターニングして半導体薄膜４
０４を形成する。Subsequently, as shown in FIG. 3C, the thickness 5
LPCVD (low pressure chemical vapor deposition) of 0 nm p-Si film
The semiconductor thin film 4 is formed by the method
04 is formed.
【００３３】その後、図３（ｄ）に示すように、厚み１
００ｎｍのＳｉＯ2膜をＡＰＣＶＤ法により成膜し、上
部ゲート電極に対応したゲート絶縁膜４０５を形成す
る。After that, as shown in FIG.
A SiO 2 film having a thickness of 00 nm is formed by APCVD method to form a gate insulating film 405 corresponding to the upper gate electrode.
【００３４】次に、図４（ｅ）に示すように、その上に
Ｔａ膜を成膜し、これをパターニングして上部ゲート電
極４０６、４０６を形成する。Next, as shown in FIG. 4 (e), a Ta film is formed thereon and is patterned to form upper gate electrodes 406 and 406.
【００３５】続いて、図４（ｆ）に示すように、中央の
下部ゲート電極４０２に対応したチャンネル領域をレジ
スト４０７により保護して、イオン注入法によりリンイ
オンを１×１０15ｃｍ-2、９０ｋＶで注入する。レジス
トを除去した後、活性化アニールを６００℃で２０時間
行う。Subsequently, as shown in FIG. 4F, the central channel region corresponding to the lower gate electrode 402 is protected by a resist 407, and phosphorus ions are added at 1 × 10 15 cm -2 , 90 kV by an ion implantation method. Inject. After removing the resist, activation annealing is performed at 600 ° C. for 20 hours.
【００３６】さらに、図４（ｇ）に示すように、厚み４
００ｎｍのＳｉＯ2膜をＡＰＣＶＤ法により成膜して層
間絶縁膜４０８を形成後、コンタクトホールを形成し、
Ａｌ電極を形成してソース電極およびドレイン電極４０
９、４０９とする。Further, as shown in FIG.
A SiO 2 film having a thickness of 00 nm is formed by an APCVD method to form an interlayer insulating film 408, and then a contact hole is formed.
Source electrode and drain electrode 40 by forming an Al electrode
9 and 409.
【００３７】この実施例では、上部ゲート電極長Ｌ１、
Ｌ２を各々４μｍ、上部ゲート電極間を３μｍ、下部ゲ
ート電極長Ｌ３を７μｍ、重なり領域を各々２μｍと
し、チャンネル幅は３μｍとした。In this embodiment, the upper gate electrode length L1,
L2 was 4 μm each, upper gate electrodes were 3 μm apart, lower gate electrode length L3 was 7 μm, overlapping regions were 2 μm each, and channel width was 3 μm.
【００３８】図５（ａ）および（ｂ）に、本実施例１の
ＴＦＴについて、下部ゲート電極４０２を上部ゲート電
極４０６に接続した場合のドレイン電流−ゲート電圧
（ＩD−ＶG）曲線を示す。左側の図５（ａ）のグラフは
暗時を示し、右側の図５（ｂ）のグラフは基板裏面から
の２０００ｌｘの光照射時を示す。また、通常のデュア
ルゲート構造のＴＦＴを比較例として同図に点線で示し
た。比較例のＴＦＴは、下部ゲート電極４０２の作製工
程がないこと、およびイオン注入工程で中央の下部ゲー
ト電極４０２に対応したチャンネル領域をレジスト４０
７で保護しなかったこと以外は実施例１のＴＦＴと同様
にして作製した。[0038] FIGS. 5 (a) and (b), the TFT of the embodiment 1, the drain current in the case of connecting the bottom gate electrode 402 to the upper gate electrode 406 - the gate voltage (I D -V G) curve Show. The graph of FIG. 5A on the left side shows the dark time, and the graph of FIG. 5B on the right side shows the time of light irradiation of 2000 lx from the back surface of the substrate. Further, a normal dual-gate structure TFT is shown by a dotted line in the figure as a comparative example. In the TFT of the comparative example, there is no manufacturing process of the lower gate electrode 402, and the channel region corresponding to the lower gate electrode 402 at the center is resist 40 in the ion implantation process.
A TFT was manufactured in the same manner as the TFT of Example 1 except that it was not protected by 7.
【００３９】この図５（ａ）および（ｂ）によれば、暗
時のオフ電流については、本実施例１のＴＦＴと比較例
のＴＦＴとで、あまり差が見られない。しかし、基板裏
面から光を２０００ｌｘ照射した時には、本実施例１の
ＴＦＴではオフ電流の増加が殆ど見られないが、比較例
のＴＦＴでは１桁程度のオフ電流の増加が見られる。こ
のように、本実施例１の構造は、光入射時のオフ電流の
低減に非常に有効である。According to FIGS. 5 (a) and 5 (b), there is not much difference in the off-current in the dark between the TFT of the first embodiment and the TFT of the comparative example. However, when 2000 lx of light is irradiated from the back surface of the substrate, the off-current hardly increases in the TFT of the first embodiment, but the off-current of the comparative example increases by about one digit. As described above, the structure of Example 1 is very effective in reducing the off-current when light is incident.
【００４０】また、図５（ｃ）に、本実施例１のＴＦＴ
について、下部ゲート電極４０２を上部ゲート電極４０
６に接続しないで独立して変化させた場合の（ＩD−
ＶG）曲線を示す。この図５（ｃ）によれば、下部ゲー
ト電極４０２の電圧ＶG２を正方向に高くしていくと、
中央の下部ゲート電極４０２に対応したＴＦＴがオン状
態になるので、オン電流は増加する。しかし、この場
合、下部ゲート電極４０２に対応したＴＦＴが単なる抵
抗体に近付くので、若干オフ電流が増加する。一方、下
部ゲート電極４０２の電圧ＶG２を負方向に高くしてい
くと、中央の下部ゲート電極４０２に対応したＴＦＴが
オフ状態になるので、オン電流は減少するが、オフ電流
も減少する。Further, FIG. 5C shows the TFT of the first embodiment.
The lower gate electrode 402 and the upper gate electrode 40
(I D − when changing independently without connecting to 6
V G ) curve is shown. According to FIG. 5C, when the voltage V G 2 of the lower gate electrode 402 is increased in the positive direction,
Since the TFT corresponding to the lower gate electrode 402 at the center is turned on, the on-current increases. However, in this case, since the TFT corresponding to the lower gate electrode 402 approaches a simple resistor, the off current slightly increases. On the other hand, when the voltage V G 2 of the lower gate electrode 402 is increased in the negative direction, the TFT corresponding to the central lower gate electrode 402 is turned off, so the on-current decreases but the off-current also decreases. .
【００４１】図５（ｄ）に、本実施例１のＴＦＴについ
て、オンオフ比のＶG２依存性を示す。尚、オンオフ比
は、ＶG＝１０Ｖ時とＶG＝−１０Ｖ時とのドレイン電流
の比で定義した。この図５（ｄ）によれば、本実施例１
のＴＦＴでは、ＶG２が約−２Ｖ程度で最もオンオフ比
が高くなっている。従って、下部ゲート電極４０２にＶ
G２＝−２Ｖの電圧を印加することにより、最も良好な
特性が得られると考えられる。尚、この値は、ｐ−Ｓｉ
やゲート絶縁膜の作製方法やサイズ等により変化するこ
とは言うまでもない。FIG. 5D shows the V G 2 dependence of the on / off ratio of the TFT of the first embodiment. The on / off ratio was defined as the ratio of the drain current when V G = 10V and when V G = −10V. According to FIG. 5D, the first embodiment
The TFT has the highest on / off ratio when V G 2 is about −2V. Therefore, V is applied to the lower gate electrode 402.
It is considered that the best characteristics can be obtained by applying a voltage of G 2 = −2V. In addition, this value is p-Si
Needless to say, it varies depending on the manufacturing method and size of the gate insulating film.
【００４２】また、本実施例１のＴＦＴを液晶表示装置
のスイッチング素子として形成した場合、画素電極とゲ
ート電極との容量結合による画素電圧の変動が抑制さ
れ、画像への悪影響は見られなかった。Further, when the TFT of the first embodiment is formed as a switching element of a liquid crystal display device, fluctuation of the pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode is suppressed, and no adverse effect on the image is seen. .
【００４３】（実施例２）図８に本実施例２のＴＦＴの
断面図を示す。(Embodiment 2) FIG. 8 shows a sectional view of a TFT of the present embodiment 2.
【００４４】このＴＦＴは、ガラス基板６０１上に、ｐ
−Ｓｉからなる半導体薄膜６０４が形成され、その上下
に、絶縁膜６０３、６０５を介して上部ゲート電極６０
６、６０６および下部ゲート電極６０２が形成されてい
る。半導体薄膜６０４の下部ゲート電極６０２上の部分
６１０には、ソース領域およびドレイン領域と同じ導電
型の不純物が低濃度に導入されている。下部ゲート電極
６０２はソース領域およびドレイン領域と重なっておら
ず、また、その一部は、隣接する上部ゲート電極６０
６、６０６と重なっている。その上には、上部ゲート電
極６０６、６０６を覆うように層間絶縁膜６０８が形成
され、絶縁膜６０５および層間絶縁膜６０８に形成され
たコンタクトホールを介して、ソース電極およびドレイ
ン電極４０９、４０９がソース領域およびドレイン領域
に接続されている。This TFT is formed on a glass substrate 601 with p
A semiconductor thin film 604 made of —Si is formed, and the upper gate electrode 60 is formed above and below the semiconductor thin film 604 via insulating films 603 and 605.
6, 606 and the lower gate electrode 602 are formed. In a portion 610 of the semiconductor thin film 604 on the lower gate electrode 602, impurities of the same conductivity type as those of the source region and the drain region are introduced at a low concentration. The lower gate electrode 602 does not overlap with the source region and the drain region, and a part of the lower gate electrode 602 is adjacent to the upper gate electrode 60.
It overlaps with 6,606. An interlayer insulating film 608 is formed thereon so as to cover the upper gate electrodes 606 and 606, and source and drain electrodes 409 and 409 are formed through contact holes formed in the insulating film 605 and the interlayer insulating film 608. It is connected to the source region and the drain region.
【００４５】このＴＦＴの作製方法を図６、図７および
図８に従って説明する。A method of manufacturing this TFT will be described with reference to FIGS. 6, 7 and 8.
【００４６】まず、図６（ａ）に示すように、ガラス基
板６０１上にＴａ膜を成膜し、これをパターニングして
下部ゲート電極６０２を形成する。First, as shown in FIG. 6A, a Ta film is formed on a glass substrate 601, and this is patterned to form a lower gate electrode 602.
【００４７】次に、図６（ｂ）に示すように、厚み３０
０ｎｍのＳｉＯ2膜をＡＰＣＶＤ法により成膜し、下部
ゲート電極６０２に対応したゲート絶縁膜６０３を形成
する。 続いて、図６（ｃ）に示すように、厚み５０ｎ
ｍのｐ−Ｓｉ膜をＬＰＣＶＤ法により成膜し、これをパ
ターニングして半導体薄膜６０４を形成する。Next, as shown in FIG. 6B, the thickness 30
A 0 nm SiO 2 film is formed by the APCVD method, and a gate insulating film 603 corresponding to the lower gate electrode 602 is formed. Then, as shown in FIG.
A p-Si film of m is formed by the LPCVD method and is patterned to form a semiconductor thin film 604.
【００４８】その後、図６（ｄ）に示すように、厚み１
００ｎｍのＳｉＯ2膜をＡＰＣＶＤ法により成膜し、上
部ゲート電極に対応したゲート絶縁膜６０５を形成す
る。Thereafter, as shown in FIG. 6D, the thickness 1
A SiO 2 film having a thickness of 00 nm is formed by APCVD method to form a gate insulating film 605 corresponding to the upper gate electrode.
【００４９】次に、図７（ｅ）に示すように、その上に
Ｔａ膜を成膜し、これをパターニングして上部ゲート電
極６０６、６０６を形成する。Next, as shown in FIG. 7E, a Ta film is formed thereon, and this is patterned to form upper gate electrodes 606 and 606.
【００５０】続いて、図７（ｆ）に示すように、イオン
注入法によりリンイオンを１×１０12ｃｍ-2、９０ｋＶ
で注入する。Subsequently, as shown in FIG. 7 (f), phosphorus ions are added by ion implantation at 1 × 10 12 cm −2 and 90 kV.
Inject.
【００５１】その後、図７（ｇ）に示すように、中央の
下部ゲート電極６０２に対応したチャンネル領域をレジ
スト６０７により保護して、イオン注入法によりリンイ
オンを１×１０15ｃｍ-2、９０ｋＶで注入する。レジス
トを除去した後、活性化アニールを６００℃で２０Ｈ行
う。Then, as shown in FIG. 7G, the channel region corresponding to the lower gate electrode 602 at the center is protected by a resist 607, and phosphorus ions are applied at 1 × 10 15 cm -2 and 90 kV by an ion implantation method. inject. After removing the resist, activation annealing is performed at 600 ° C. for 20 hours.
【００５２】さらに、図８に示すように、厚み４００ｎ
ｍのＳｉＯ2膜をＡＰＣＶＤ法により成膜して層間絶縁
膜６０８を形成後、コンタクトホールを形成し、Ａｌ電
極を形成してソース電極およびドレイン電極６０９、６
０９とする。Further, as shown in FIG.
m SiO 2 film is formed by an APCVD method to form an interlayer insulating film 608, a contact hole is formed, an Al electrode is formed, and a source electrode and a drain electrode 609, 6 are formed.
09.
【００５３】この実施例では、上部ゲート電極長Ｌ１、
Ｌ２を各々４μｍ、上部ゲート電極間を３μｍ、下部ゲ
ート電極長Ｌ３を７μｍ、重なり領域を各々２μｍと
し、チャンネル幅は３μｍとした。In this embodiment, the upper gate electrode length L1,
L2 was 4 μm each, upper gate electrodes were 3 μm apart, lower gate electrode length L3 was 7 μm, overlapping regions were 2 μm each, and channel width was 3 μm.
【００５４】図９（ａ）および（ｂ）に、本実施例２の
ＴＦＴについて、下部ゲート電極６０２を上部ゲート電
極６０６に接続した場合のドレイン電流−ゲート電圧
（ＩD−ＶG）曲線を示す。左側の図９（ａ）のグラフは
暗時を示し、右側の図９（ｂ）のグラフは基板裏面から
の２０００ｌｘの光照射時を示す。また、実施例１のＴ
ＦＴを点線で同図に示した。[0054] FIG. 9 (a) and 9 (b), the TFT of the second embodiment, the drain current in the case of connecting the bottom gate electrode 602 to the upper gate electrode 606 - the gate voltage (I D -V G) curve Show. The graph of FIG. 9A on the left side shows the dark time, and the graph of FIG. 9B on the right side shows the time of light irradiation of 2000 lx from the back surface of the substrate. In addition, T of Example 1
The FT is shown in the figure by a dotted line.
【００５５】この図９（ａ）および（ｂ）によれば、本
実施例２のＴＦＴは、実施例１のＴＦＴに比べてオン電
流が増加している。これは、低濃度の不純物導入によ
り、下部ゲート電極６０２に対応したＴＦＴの閾値電圧
が負方向にシフトしたためである。また、ＶGを十分負
側にすることにより、下部ゲート電極６０２に対応した
ＴＦＴのチャンネル領域が空乏層化するので、実施例１
のＴＦＴに比べてオフ電流も低減している。さらに、光
照射によるオフ電流の増加も見られない。このように、
本実施例２の構造は、オフ電流の低減に非常に有効であ
る。According to FIGS. 9 (a) and 9 (b), the ON current of the TFT of the second embodiment is larger than that of the TFT of the first embodiment. This is because the threshold voltage of the TFT corresponding to the lower gate electrode 602 is shifted in the negative direction due to the introduction of the low concentration impurity. Further, by making V G sufficiently negative, the channel region of the TFT corresponding to the lower gate electrode 602 becomes a depletion layer.
The off-current is also reduced as compared with the TFT. Further, no increase in off current due to light irradiation is observed. in this way,
The structure of Example 2 is very effective in reducing the off current.
【００５６】また、図９（ｃ）に、本実施例２のＴＦＴ
について、下部ゲート電極６０２を上部ゲート電極６０
６に接続しないで独立して変化させた場合の（ＩD−
ＶG）曲線を示す。本実施例２のＴＦＴについても、実
施例１のＴＦＴと同様に、下部ゲート電極６０２の電圧
ＶG２を負方向に高くしていくにつれてオン電流は減少
するが、オフ電流も減少するという傾向が見られた。Further, FIG. 9C shows the TFT of the second embodiment.
The lower gate electrode 602 and the upper gate electrode 60.
(I D − when changing independently without connecting to 6
V G ) curve is shown. In the TFT of the second embodiment, as in the TFT of the first embodiment, the on-current decreases as the voltage V G 2 of the lower gate electrode 602 increases in the negative direction, but the off-current also tends to decrease. It was observed.
【００５７】図９（ｄ）に、本実施例２のＴＦＴについ
て、オンオフ比のＶG２依存性を示す。尚、オンオフ比
は、実施例１と同様に定義した。この図９（ｄ）によれ
ば、本実施例２のＴＦＴでは、ＶＧ2が約−７Ｖ程度で
最もオンオフ比が高くなっている。従って、下部ゲート
電極６０２にＶG２＝−７Ｖの電圧を印加することによ
り、最も良好な特性が得られると考えられる。尚、この
値についても、ｐ−Ｓｉやゲート絶縁膜の作製方法やサ
イズ等により変化することは言うまでもない。FIG. 9D shows the V G 2 dependency of the on / off ratio of the TFT of the second embodiment. The on / off ratio was defined as in Example 1. According to FIG. 9D, in the TFT of Example 2, the on / off ratio was highest when VG 2 was about −7V. Therefore, it is considered that the best characteristics can be obtained by applying the voltage V G 2 = −7V to the lower gate electrode 602. Needless to say, this value also changes depending on the manufacturing method, size, and the like of p-Si and the gate insulating film.
【００５８】また、本実施例２のＴＦＴも実施例１のＴ
ＦＴと同様に、液晶表示装置のスイッチング素子として
形成した場合、画素電極とゲート電極との容量結合によ
る画素電圧の変動が抑制され、画像への悪影響は見られ
なかった。The TFT of the second embodiment is also the T of the first embodiment.
Similar to the FT, when formed as a switching element of a liquid crystal display device, fluctuation of the pixel voltage due to capacitive coupling between the pixel electrode and the gate electrode was suppressed, and no adverse effect on the image was observed.
【００５９】上記実施例１および２では、ゲート絶縁膜
にＡＰＣＶＤ法によるＳｉＯ2膜を、半導体層にＬＰＣ
ＶＤ法によるｐ−Ｓｉ膜、ゲート電極にＴａを用いた
が、その他の作製法や材料を用いてもよい。例えば、ゲ
ート絶縁膜の形成は、スパッタリング法やＬＰＣＶＤ
法、ＰＣＶＤ法等により行うことができ、ＳｉＮ膜やＴ
ａ2Ｏ5膜、Ａｌ2Ｏ3膜等を用いてもよい。上下の絶縁膜
の膜厚やそれらの膜厚比も、ｐ−Ｓｉ膜や絶縁膜の膜質
に応じて最適化することができる。ｐ−Ｓｉ膜の形成
は、ＬＰＣＶＤ法やＰＣＶＤ法によりａ−Ｓｉ膜を成膜
した後、固相成長やレーザーアニール、ランプアニール
等によりｐ−Ｓｉ膜としてもよい。ゲート電極の材料と
しては、作製に耐える導電性材料であればいずれも用い
ることができる。 また、本発明より得られるＴＦＴ
は、ＡＭＬＣＤの画素用トランジスタや、他にイメージ
センサのスイッチングトランジスタなど、様々な用途に
適用することができる。In Examples 1 and 2 above, the SiO 2 film formed by the APCVD method was used as the gate insulating film and the LPC was used as the semiconductor layer.
Although Ta is used for the p-Si film and the gate electrode by the VD method, other manufacturing methods and materials may be used. For example, the gate insulating film is formed by sputtering or LPCVD.
Method, PCVD method, etc.
An a 2 O 5 film, an Al 2 O 3 film or the like may be used. The film thicknesses of the upper and lower insulating films and the film thickness ratio thereof can be optimized according to the film quality of the p-Si film or the insulating film. The p-Si film may be formed by forming the a-Si film by the LPCVD method or the PCVD method, and then forming the p-Si film by solid phase growth, laser annealing, lamp annealing or the like. As a material for the gate electrode, any conductive material that can be manufactured can be used. In addition, the TFT obtained by the present invention
Can be applied to various applications such as a pixel transistor of AMLCD and a switching transistor of an image sensor.
【００６０】[0060]
【発明の効果】以上の説明から明らかなように、本発明
によればＴＦＴのオフ電流を低減でき、光入射によるオ
フ電流の増加も防ぐことができる。また、このＴＦＴを
画素用スイッチング素子として用いると、画素電極とゲ
ート電極との容量結合による画素電圧の変動が抑制さ
れ、画像への悪影響も生じない。As is apparent from the above description, according to the present invention, the off current of the TFT can be reduced and the increase of the off current due to the incidence of light can be prevented. Further, when the TFT is used as a pixel switching element, the fluctuation of the pixel voltage due to the capacitive coupling between the pixel electrode and the gate electrode is suppressed and the image is not adversely affected.
【００６１】半導体薄膜の下部電極上の部分にＬＤＤ領
域を形成すると、さらにオフ電流の低減を図ることがで
きる。このＬＤＤ領域は、上部ゲート電極をマスクとし
て位置制御性良く形成することができる。If the LDD region is formed on the lower electrode of the semiconductor thin film, the off current can be further reduced. This LDD region can be formed with good position controllability using the upper gate electrode as a mask.
【００６２】上部ゲート電極および下部ゲート電極は、
同一の信号線に接続してもよく、下部ゲート電極に一定
の電圧を印加してもよい。下部ゲート電極に一定の電圧
を印加する場合には、全体として最もオンオフ比が高く
なるように電圧を印加することにより、特性を良好する
ことができる。このように下部ゲート電極に一定の電圧
を印加する場合には、下部ゲート電極と上部ゲート電極
とを接続する必要が無く、さらにプロセスが簡略化でき
る。The upper gate electrode and the lower gate electrode are
They may be connected to the same signal line, or a constant voltage may be applied to the lower gate electrode. When a constant voltage is applied to the lower gate electrode, the characteristics can be improved by applying the voltage so that the overall on / off ratio becomes the highest. When a constant voltage is applied to the lower gate electrode as described above, it is not necessary to connect the lower gate electrode and the upper gate electrode, and the process can be further simplified.
【図１】（ａ）および（ｂ）は、本発明のＴＦＴの一実
施形態を示す断面図である。1A and 1B are cross-sectional views showing an embodiment of a TFT of the present invention.
【図２】（ｃ）および（ｄ）は、本発明のＴＦＴの一実
施形態を示す断面図である。2 (c) and (d) are cross-sectional views showing an embodiment of the TFT of the present invention.
【図３】（ａ）〜（ｄ）は、実施例１のＴＦＴの製造工
程を示す断面図である。3 (a) to 3 (d) are cross-sectional views showing a manufacturing process of the TFT of Example 1. FIG.
【図４】（ｅ）〜（ｇ）は、実施例１のＴＦＴの製造工
程を示す断面図である。4 (e) to (g) are cross-sectional views showing a manufacturing process of the TFT of Example 1. FIG.
【図５】（ａ）〜（ｄ）は、実施例１のＴＦＴの特性を
示すグラフである。5 (a) to (d) are graphs showing characteristics of the TFT of Example 1. FIG.
【図６】（ａ）〜（ｄ）は、実施例２のＴＦＴの製造工
程を示す断面図である。6A to 6D are cross-sectional views showing the manufacturing process of the TFT of Example 2.
【図７】（ｅ）〜（ｇ）は、実施例２のＴＦＴの製造工
程を示す断面図である。7E to 7G are cross-sectional views showing the manufacturing steps of the TFT of Example 2.
【図８】実施例２のＴＦＴの製造工程を示す断面図であ
る。FIG. 8 is a cross-sectional view showing a manufacturing process of a TFT of Example 2.
【図９】（ａ）〜（ｄ）は、実施例２のＴＦＴの特性を
示すグラフである。9A to 9D are graphs showing the characteristics of the TFT of Example 2. FIG.
【図１０】従来のオフ電流を低減したＴＦＴを示す断面
図である。FIG. 10 is a cross-sectional view showing a conventional TFT with reduced off current.
【図１１】従来のオフ電流を低減した他のＴＦＴを示す
断面図である。FIG. 11 is a cross-sectional view showing another conventional TFT with reduced off current.
【図１２】従来のオフ電流を低減した更に他のＴＦＴを
示す断面図である。FIG. 12 is a cross-sectional view showing still another conventional TFT in which the off-current is reduced.
【図１３】従来の遮光膜を形成したＴＦＴを示す断面図
である。FIG. 13 is a sectional view showing a conventional TFT having a light-shielding film formed thereon.
【図１４】図１３のＴＦＴの等価回路である。FIG. 14 is an equivalent circuit of the TFT of FIG.
１０１、４０１、６０１ ガラス基板 １０２、４０２、６０２ 下部ゲート電極 １０３、４０３、６０３ 下部ゲート電極に対応した絶
縁膜 １０４ チャンネル領域 １０５、４０５、６０５ 上部ゲート電極に対応した絶
縁膜 １０６、１０７、４０６、６０６ 上部ゲート電極 １０８、４０８、６０８ 層間絶縁膜 １０９、１１０、４０９、６０９ ソース電極およびド
レイン電極 １１１、１１２ ソース領域およびドレイン領域 １１３、１１４ 空乏層領域 ４０４、６０４ 半導体層 ４０７、６０７ レジスト101, 401, 601 Glass substrate 102, 402, 602 Lower gate electrode 103, 403, 603 Insulating film 104 corresponding to lower gate electrode 104 Channel regions 105, 405, 605 Insulating film 106, 107, 406 corresponding to upper gate electrode 606 upper gate electrode 108, 408, 608 interlayer insulating film 109, 110, 409, 609 source electrode and drain electrode 111, 112 source region and drain region 113, 114 depletion layer region 404, 604 semiconductor layer 407, 607 resist
Claims (4)
レイン領域とを有する半導体薄膜の該チャンネル領域を
挟んで一方側に、絶縁膜を介して２以上の上部ゲート電
極が形成され、他方側に絶縁膜を介して１以上の下部ゲ
ート電極が、各下部ゲート電極の両端部を相互に隣接す
る上部ゲート電極の各々に対して重畳させて形成されて
いる薄膜トランジスタ。1. A semiconductor thin film having a source region and a drain region on both sides of a channel region, two or more upper gate electrodes are formed on one side of the channel region with an insulating film interposed therebetween, and insulated on the other side. A thin film transistor in which one or more lower gate electrodes are formed through a film, with both ends of each lower gate electrode being overlapped on each of the adjacent upper gate electrodes.
は重畳しない部分に、前記ソース領域およびドレイン領
域に導入されている不純物と同じ導電型の不純物が該ソ
ース領域およびドレイン領域よりも低濃度に導入されて
いる請求項１に記載の薄膜トランジスタ。2. The impurity of the same conductivity type as the impurities introduced into the source region and the drain region is made to have a lower concentration than that of the source region and the drain region in a portion of the semiconductor thin film which does not overlap with the upper gate electrode. The thin film transistor according to claim 1, which is introduced.
極が同一の信号線に接続されている請求項１または２に
記載の薄膜トランジスタ。3. The thin film transistor according to claim 1, wherein the upper gate electrode and the lower gate electrode are connected to the same signal line.
されている請求項１または２に記載の薄膜トランジス
タ。4. The thin film transistor according to claim 1, wherein a constant voltage is applied to the lower gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24347995A JPH0990405A (en) | 1995-09-21 | 1995-09-21 | Thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24347995A JPH0990405A (en) | 1995-09-21 | 1995-09-21 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0990405A true JPH0990405A (en) | 1997-04-04 |
Family
ID=17104507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24347995A Withdrawn JPH0990405A (en) | 1995-09-21 | 1995-09-21 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0990405A (en) |
Cited By (103)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002067328A3 (en) * | 2001-02-16 | 2002-11-07 | Ignis Innovation Inc | Organic light emitting diode display having shield electrodes |
| WO2002067327A3 (en) * | 2001-02-16 | 2004-05-21 | Ignis Innovation Inc | Pixel current driver for organic light emitting diode displays |
| US7535022B2 (en) | 2001-05-24 | 2009-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor with plural channels and corresponding overlapping electrode |
| US7569849B2 (en) | 2001-02-16 | 2009-08-04 | Ignis Innovation Inc. | Pixel driver circuit and pixel circuit having the pixel driver circuit |
| JP2011018062A (en) * | 2010-08-23 | 2011-01-27 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
| US8044893B2 (en) | 2005-01-28 | 2011-10-25 | Ignis Innovation Inc. | Voltage programmed pixel circuit, display system and driving method thereof |
| KR101107697B1 (en) * | 2005-04-19 | 2012-01-25 | 엘지디스플레이 주식회사 | Thin film transistor and liquid crystal display device having the same |
| US8334863B2 (en) | 2007-12-24 | 2012-12-18 | Ignis Innovation Inc. | Display system with a solar cell and device having the same |
| US8378938B2 (en) | 2004-12-07 | 2013-02-19 | Ignis Innovation Inc. | Method and system for programming and driving active matrix light emitting device pixel having a controllable supply voltage |
| US8502751B2 (en) | 2003-09-23 | 2013-08-06 | Ignis Innovation Inc. | Pixel driver circuit with load-balance in current mirror circuit |
| US8860636B2 (en) | 2005-06-08 | 2014-10-14 | Ignis Innovation Inc. | Method and system for driving a light emitting device display |
| US8901579B2 (en) | 2011-08-03 | 2014-12-02 | Ignis Innovation Inc. | Organic light emitting diode and method of manufacturing |
| US8907991B2 (en) | 2010-12-02 | 2014-12-09 | Ignis Innovation Inc. | System and methods for thermal compensation in AMOLED displays |
| USRE45291E1 (en) | 2004-06-29 | 2014-12-16 | Ignis Innovation Inc. | Voltage-programming scheme for current-driven AMOLED displays |
| US8922544B2 (en) | 2012-05-23 | 2014-12-30 | Ignis Innovation Inc. | Display systems with compensation for line propagation delay |
| US8933455B2 (en) | 1999-08-31 | 2015-01-13 | Semiconductor Energy Laboratory Co., Ltd. | Display device comprising pixel |
| US8994625B2 (en) | 2004-12-15 | 2015-03-31 | Ignis Innovation Inc. | Method and system for programming, calibrating and driving a light emitting device display |
| US8994617B2 (en) | 2010-03-17 | 2015-03-31 | Ignis Innovation Inc. | Lifetime uniformity parameter extraction methods |
| US9030506B2 (en) | 2009-11-12 | 2015-05-12 | Ignis Innovation Inc. | Stable fast programming scheme for displays |
| US9058775B2 (en) | 2006-01-09 | 2015-06-16 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US9059117B2 (en) | 2009-12-01 | 2015-06-16 | Ignis Innovation Inc. | High resolution pixel architecture |
| US9070775B2 (en) | 2011-08-03 | 2015-06-30 | Ignis Innovations Inc. | Thin film transistor |
| US9093028B2 (en) | 2009-12-06 | 2015-07-28 | Ignis Innovation Inc. | System and methods for power conservation for AMOLED pixel drivers |
| US9093029B2 (en) | 2011-05-20 | 2015-07-28 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9111485B2 (en) | 2009-06-16 | 2015-08-18 | Ignis Innovation Inc. | Compensation technique for color shift in displays |
| US9125278B2 (en) | 2006-08-15 | 2015-09-01 | Ignis Innovation Inc. | OLED luminance degradation compensation |
| US9134825B2 (en) | 2011-05-17 | 2015-09-15 | Ignis Innovation Inc. | Systems and methods for display systems with dynamic power control |
| US9171500B2 (en) | 2011-05-20 | 2015-10-27 | Ignis Innovation Inc. | System and methods for extraction of parasitic parameters in AMOLED displays |
| US9171504B2 (en) | 2013-01-14 | 2015-10-27 | Ignis Innovation Inc. | Driving scheme for emissive displays providing compensation for driving transistor variations |
| US9269322B2 (en) | 2006-01-09 | 2016-02-23 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US9275579B2 (en) | 2004-12-15 | 2016-03-01 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9280933B2 (en) | 2004-12-15 | 2016-03-08 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9305488B2 (en) | 2013-03-14 | 2016-04-05 | Ignis Innovation Inc. | Re-interpolation with edge detection for extracting an aging pattern for AMOLED displays |
| US9311859B2 (en) | 2009-11-30 | 2016-04-12 | Ignis Innovation Inc. | Resetting cycle for aging compensation in AMOLED displays |
| US9324268B2 (en) | 2013-03-15 | 2016-04-26 | Ignis Innovation Inc. | Amoled displays with multiple readout circuits |
| US9336717B2 (en) | 2012-12-11 | 2016-05-10 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9343006B2 (en) | 2012-02-03 | 2016-05-17 | Ignis Innovation Inc. | Driving system for active-matrix displays |
| US9351368B2 (en) | 2013-03-08 | 2016-05-24 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9370075B2 (en) | 2008-12-09 | 2016-06-14 | Ignis Innovation Inc. | System and method for fast compensation programming of pixels in a display |
| US9373724B2 (en) | 2010-01-15 | 2016-06-21 | Canon Kabushiki Kaisha | Method of driving transistor and device including transistor driven by the method |
| US9385169B2 (en) | 2011-11-29 | 2016-07-05 | Ignis Innovation Inc. | Multi-functional active matrix organic light-emitting diode display |
| US9384698B2 (en) | 2009-11-30 | 2016-07-05 | Ignis Innovation Inc. | System and methods for aging compensation in AMOLED displays |
| US9430958B2 (en) | 2010-02-04 | 2016-08-30 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US9437137B2 (en) | 2013-08-12 | 2016-09-06 | Ignis Innovation Inc. | Compensation accuracy |
| US9466240B2 (en) | 2011-05-26 | 2016-10-11 | Ignis Innovation Inc. | Adaptive feedback system for compensating for aging pixel areas with enhanced estimation speed |
| US9489891B2 (en) | 2006-01-09 | 2016-11-08 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US9502653B2 (en) | 2013-12-25 | 2016-11-22 | Ignis Innovation Inc. | Electrode contacts |
| US9530349B2 (en) | 2011-05-20 | 2016-12-27 | Ignis Innovations Inc. | Charged-based compensation and parameter extraction in AMOLED displays |
| WO2017043572A1 (en) * | 2015-09-11 | 2017-03-16 | 三菱電機株式会社 | Thin film transistor substrate and method for producing same |
| US9606607B2 (en) | 2011-05-17 | 2017-03-28 | Ignis Innovation Inc. | Systems and methods for display systems with dynamic power control |
| US9633597B2 (en) | 2006-04-19 | 2017-04-25 | Ignis Innovation Inc. | Stable driving scheme for active matrix displays |
| US9697771B2 (en) | 2013-03-08 | 2017-07-04 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9721505B2 (en) | 2013-03-08 | 2017-08-01 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9741282B2 (en) | 2013-12-06 | 2017-08-22 | Ignis Innovation Inc. | OLED display system and method |
| US9747834B2 (en) | 2012-05-11 | 2017-08-29 | Ignis Innovation Inc. | Pixel circuits including feedback capacitors and reset capacitors, and display systems therefore |
| US9761170B2 (en) | 2013-12-06 | 2017-09-12 | Ignis Innovation Inc. | Correction for localized phenomena in an image array |
| JP2017163139A (en) * | 2016-03-08 | 2017-09-14 | 株式会社半導体エネルギー研究所 | Imaging device, module, and electronic apparatus |
| USRE46561E1 (en) | 2008-07-29 | 2017-09-26 | Ignis Innovation Inc. | Method and system for driving light emitting display |
| US9773439B2 (en) | 2011-05-27 | 2017-09-26 | Ignis Innovation Inc. | Systems and methods for aging compensation in AMOLED displays |
| US9786223B2 (en) | 2012-12-11 | 2017-10-10 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9786209B2 (en) | 2009-11-30 | 2017-10-10 | Ignis Innovation Inc. | System and methods for aging compensation in AMOLED displays |
| US9799246B2 (en) | 2011-05-20 | 2017-10-24 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9830857B2 (en) | 2013-01-14 | 2017-11-28 | Ignis Innovation Inc. | Cleaning common unwanted signals from pixel measurements in emissive displays |
| US9842889B2 (en) | 2014-11-28 | 2017-12-12 | Ignis Innovation Inc. | High pixel density array architecture |
| US9867257B2 (en) | 2008-04-18 | 2018-01-09 | Ignis Innovation Inc. | System and driving method for light emitting device display |
| US9881532B2 (en) | 2010-02-04 | 2018-01-30 | Ignis Innovation Inc. | System and method for extracting correlation curves for an organic light emitting device |
| US9881587B2 (en) | 2011-05-28 | 2018-01-30 | Ignis Innovation Inc. | Systems and methods for operating pixels in a display to mitigate image flicker |
| US9886899B2 (en) | 2011-05-17 | 2018-02-06 | Ignis Innovation Inc. | Pixel Circuits for AMOLED displays |
| US9947293B2 (en) | 2015-05-27 | 2018-04-17 | Ignis Innovation Inc. | Systems and methods of reduced memory bandwidth compensation |
| US9952698B2 (en) | 2013-03-15 | 2018-04-24 | Ignis Innovation Inc. | Dynamic adjustment of touch resolutions on an AMOLED display |
| US10012678B2 (en) | 2004-12-15 | 2018-07-03 | Ignis Innovation Inc. | Method and system for programming, calibrating and/or compensating, and driving an LED display |
| US10013907B2 (en) | 2004-12-15 | 2018-07-03 | Ignis Innovation Inc. | Method and system for programming, calibrating and/or compensating, and driving an LED display |
| US10019941B2 (en) | 2005-09-13 | 2018-07-10 | Ignis Innovation Inc. | Compensation technique for luminance degradation in electro-luminance devices |
| US10078984B2 (en) | 2005-02-10 | 2018-09-18 | Ignis Innovation Inc. | Driving circuit for current programmed organic light-emitting diode displays |
| US10089921B2 (en) | 2010-02-04 | 2018-10-02 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10089924B2 (en) | 2011-11-29 | 2018-10-02 | Ignis Innovation Inc. | Structural and low-frequency non-uniformity compensation |
| US10102808B2 (en) | 2015-10-14 | 2018-10-16 | Ignis Innovation Inc. | Systems and methods of multiple color driving |
| US10134325B2 (en) | 2014-12-08 | 2018-11-20 | Ignis Innovation Inc. | Integrated display system |
| US10152915B2 (en) | 2015-04-01 | 2018-12-11 | Ignis Innovation Inc. | Systems and methods of display brightness adjustment |
| US10163401B2 (en) | 2010-02-04 | 2018-12-25 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10163996B2 (en) | 2003-02-24 | 2018-12-25 | Ignis Innovation Inc. | Pixel having an organic light emitting diode and method of fabricating the pixel |
| US10176752B2 (en) | 2014-03-24 | 2019-01-08 | Ignis Innovation Inc. | Integrated gate driver |
| US10176736B2 (en) | 2010-02-04 | 2019-01-08 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10181282B2 (en) | 2015-01-23 | 2019-01-15 | Ignis Innovation Inc. | Compensation for color variations in emissive devices |
| US10192479B2 (en) | 2014-04-08 | 2019-01-29 | Ignis Innovation Inc. | Display system using system level resources to calculate compensation parameters for a display module in a portable device |
| US10204540B2 (en) | 2015-10-26 | 2019-02-12 | Ignis Innovation Inc. | High density pixel pattern |
| US10235933B2 (en) | 2005-04-12 | 2019-03-19 | Ignis Innovation Inc. | System and method for compensation of non-uniformities in light emitting device displays |
| US10242619B2 (en) | 2013-03-08 | 2019-03-26 | Ignis Innovation Inc. | Pixel circuits for amoled displays |
| US10311780B2 (en) | 2015-05-04 | 2019-06-04 | Ignis Innovation Inc. | Systems and methods of optical feedback |
| US10319307B2 (en) | 2009-06-16 | 2019-06-11 | Ignis Innovation Inc. | Display system with compensation techniques and/or shared level resources |
| US10339860B2 (en) | 2015-08-07 | 2019-07-02 | Ignis Innovation, Inc. | Systems and methods of pixel calibration based on improved reference values |
| US10373554B2 (en) | 2015-07-24 | 2019-08-06 | Ignis Innovation Inc. | Pixels and reference circuits and timing techniques |
| CN110212035A (en) * | 2018-08-10 | 2019-09-06 | 友达光电股份有限公司 | Transistor arrangement and its operating method |
| US10410579B2 (en) | 2015-07-24 | 2019-09-10 | Ignis Innovation Inc. | Systems and methods of hybrid calibration of bias current |
| US10573231B2 (en) | 2010-02-04 | 2020-02-25 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10586491B2 (en) | 2016-12-06 | 2020-03-10 | Ignis Innovation Inc. | Pixel circuits for mitigation of hysteresis |
| US10657895B2 (en) | 2015-07-24 | 2020-05-19 | Ignis Innovation Inc. | Pixels and reference circuits and timing techniques |
| US10714018B2 (en) | 2017-05-17 | 2020-07-14 | Ignis Innovation Inc. | System and method for loading image correction data for displays |
| US10867536B2 (en) | 2013-04-22 | 2020-12-15 | Ignis Innovation Inc. | Inspection system for OLED display panels |
| US10971078B2 (en) | 2018-02-12 | 2021-04-06 | Ignis Innovation Inc. | Pixel measurement through data line |
| US10997901B2 (en) | 2014-02-28 | 2021-05-04 | Ignis Innovation Inc. | Display system |
| US10996258B2 (en) | 2009-11-30 | 2021-05-04 | Ignis Innovation Inc. | Defect detection and correction of pixel circuits for AMOLED displays |
| US11025899B2 (en) | 2017-08-11 | 2021-06-01 | Ignis Innovation Inc. | Optical correction systems and methods for correcting non-uniformity of emissive display devices |
-
1995
- 1995-09-21 JP JP24347995A patent/JPH0990405A/en not_active Withdrawn
Cited By (215)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9466622B2 (en) | 1999-08-31 | 2016-10-11 | Semiconductor Energy Laboratory Co., Ltd. | Display device comprising a thin film transistor and a storage capacitor |
| US9250490B2 (en) | 1999-08-31 | 2016-02-02 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device including light shielding film |
| US8933455B2 (en) | 1999-08-31 | 2015-01-13 | Semiconductor Energy Laboratory Co., Ltd. | Display device comprising pixel |
| US8890220B2 (en) | 2001-02-16 | 2014-11-18 | Ignis Innovation, Inc. | Pixel driver circuit and pixel circuit having control circuit coupled to supply voltage |
| WO2002067327A3 (en) * | 2001-02-16 | 2004-05-21 | Ignis Innovation Inc | Pixel current driver for organic light emitting diode displays |
| US7414600B2 (en) | 2001-02-16 | 2008-08-19 | Ignis Innovation Inc. | Pixel current driver for organic light emitting diode displays |
| US7569849B2 (en) | 2001-02-16 | 2009-08-04 | Ignis Innovation Inc. | Pixel driver circuit and pixel circuit having the pixel driver circuit |
| WO2002067328A3 (en) * | 2001-02-16 | 2002-11-07 | Ignis Innovation Inc | Organic light emitting diode display having shield electrodes |
| US7535022B2 (en) | 2001-05-24 | 2009-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor with plural channels and corresponding overlapping electrode |
| US10163996B2 (en) | 2003-02-24 | 2018-12-25 | Ignis Innovation Inc. | Pixel having an organic light emitting diode and method of fabricating the pixel |
| US9472139B2 (en) | 2003-09-23 | 2016-10-18 | Ignis Innovation Inc. | Circuit and method for driving an array of light emitting pixels |
| US10089929B2 (en) | 2003-09-23 | 2018-10-02 | Ignis Innovation Inc. | Pixel driver circuit with load-balance in current mirror circuit |
| US8502751B2 (en) | 2003-09-23 | 2013-08-06 | Ignis Innovation Inc. | Pixel driver circuit with load-balance in current mirror circuit |
| US9472138B2 (en) | 2003-09-23 | 2016-10-18 | Ignis Innovation Inc. | Pixel driver circuit with load-balance in current mirror circuit |
| US9852689B2 (en) | 2003-09-23 | 2017-12-26 | Ignis Innovation Inc. | Circuit and method for driving an array of light emitting pixels |
| US8941697B2 (en) | 2003-09-23 | 2015-01-27 | Ignis Innovation Inc. | Circuit and method for driving an array of light emitting pixels |
| USRE45291E1 (en) | 2004-06-29 | 2014-12-16 | Ignis Innovation Inc. | Voltage-programming scheme for current-driven AMOLED displays |
| USRE47257E1 (en) | 2004-06-29 | 2019-02-26 | Ignis Innovation Inc. | Voltage-programming scheme for current-driven AMOLED displays |
| US9153172B2 (en) | 2004-12-07 | 2015-10-06 | Ignis Innovation Inc. | Method and system for programming and driving active matrix light emitting device pixel having a controllable supply voltage |
| US8405587B2 (en) | 2004-12-07 | 2013-03-26 | Ignis Innovation Inc. | Method and system for programming and driving active matrix light emitting device pixel having a controllable supply voltage |
| US9741292B2 (en) | 2004-12-07 | 2017-08-22 | Ignis Innovation Inc. | Method and system for programming and driving active matrix light emitting device pixel having a controllable supply voltage |
| US8378938B2 (en) | 2004-12-07 | 2013-02-19 | Ignis Innovation Inc. | Method and system for programming and driving active matrix light emitting device pixel having a controllable supply voltage |
| US10013907B2 (en) | 2004-12-15 | 2018-07-03 | Ignis Innovation Inc. | Method and system for programming, calibrating and/or compensating, and driving an LED display |
| US9280933B2 (en) | 2004-12-15 | 2016-03-08 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9275579B2 (en) | 2004-12-15 | 2016-03-01 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9970964B2 (en) | 2004-12-15 | 2018-05-15 | Ignis Innovation Inc. | Method and system for programming, calibrating and driving a light emitting device display |
| US8994625B2 (en) | 2004-12-15 | 2015-03-31 | Ignis Innovation Inc. | Method and system for programming, calibrating and driving a light emitting device display |
| US10012678B2 (en) | 2004-12-15 | 2018-07-03 | Ignis Innovation Inc. | Method and system for programming, calibrating and/or compensating, and driving an LED display |
| US10699624B2 (en) | 2004-12-15 | 2020-06-30 | Ignis Innovation Inc. | Method and system for programming, calibrating and/or compensating, and driving an LED display |
| US8497825B2 (en) | 2005-01-28 | 2013-07-30 | Ignis Innovation Inc. | Voltage programmed pixel circuit, display system and driving method thereof |
| US8044893B2 (en) | 2005-01-28 | 2011-10-25 | Ignis Innovation Inc. | Voltage programmed pixel circuit, display system and driving method thereof |
| US9728135B2 (en) | 2005-01-28 | 2017-08-08 | Ignis Innovation Inc. | Voltage programmed pixel circuit, display system and driving method thereof |
| US9373645B2 (en) | 2005-01-28 | 2016-06-21 | Ignis Innovation Inc. | Voltage programmed pixel circuit, display system and driving method thereof |
| US10078984B2 (en) | 2005-02-10 | 2018-09-18 | Ignis Innovation Inc. | Driving circuit for current programmed organic light-emitting diode displays |
| US10235933B2 (en) | 2005-04-12 | 2019-03-19 | Ignis Innovation Inc. | System and method for compensation of non-uniformities in light emitting device displays |
| KR101107697B1 (en) * | 2005-04-19 | 2012-01-25 | 엘지디스플레이 주식회사 | Thin film transistor and liquid crystal display device having the same |
| US10388221B2 (en) | 2005-06-08 | 2019-08-20 | Ignis Innovation Inc. | Method and system for driving a light emitting device display |
| US9330598B2 (en) | 2005-06-08 | 2016-05-03 | Ignis Innovation Inc. | Method and system for driving a light emitting device display |
| US8860636B2 (en) | 2005-06-08 | 2014-10-14 | Ignis Innovation Inc. | Method and system for driving a light emitting device display |
| US9805653B2 (en) | 2005-06-08 | 2017-10-31 | Ignis Innovation Inc. | Method and system for driving a light emitting device display |
| US10019941B2 (en) | 2005-09-13 | 2018-07-10 | Ignis Innovation Inc. | Compensation technique for luminance degradation in electro-luminance devices |
| US9489891B2 (en) | 2006-01-09 | 2016-11-08 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US10262587B2 (en) | 2006-01-09 | 2019-04-16 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US9269322B2 (en) | 2006-01-09 | 2016-02-23 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US9058775B2 (en) | 2006-01-09 | 2015-06-16 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US10229647B2 (en) | 2006-01-09 | 2019-03-12 | Ignis Innovation Inc. | Method and system for driving an active matrix display circuit |
| US10127860B2 (en) | 2006-04-19 | 2018-11-13 | Ignis Innovation Inc. | Stable driving scheme for active matrix displays |
| US9633597B2 (en) | 2006-04-19 | 2017-04-25 | Ignis Innovation Inc. | Stable driving scheme for active matrix displays |
| US9842544B2 (en) | 2006-04-19 | 2017-12-12 | Ignis Innovation Inc. | Stable driving scheme for active matrix displays |
| US10453397B2 (en) | 2006-04-19 | 2019-10-22 | Ignis Innovation Inc. | Stable driving scheme for active matrix displays |
| US9125278B2 (en) | 2006-08-15 | 2015-09-01 | Ignis Innovation Inc. | OLED luminance degradation compensation |
| US10325554B2 (en) | 2006-08-15 | 2019-06-18 | Ignis Innovation Inc. | OLED luminance degradation compensation |
| US9530352B2 (en) | 2006-08-15 | 2016-12-27 | Ignis Innovations Inc. | OLED luminance degradation compensation |
| US8334863B2 (en) | 2007-12-24 | 2012-12-18 | Ignis Innovation Inc. | Display system with a solar cell and device having the same |
| US9877371B2 (en) | 2008-04-18 | 2018-01-23 | Ignis Innovations Inc. | System and driving method for light emitting device display |
| US10555398B2 (en) | 2008-04-18 | 2020-02-04 | Ignis Innovation Inc. | System and driving method for light emitting device display |
| US9867257B2 (en) | 2008-04-18 | 2018-01-09 | Ignis Innovation Inc. | System and driving method for light emitting device display |
| USRE46561E1 (en) | 2008-07-29 | 2017-09-26 | Ignis Innovation Inc. | Method and system for driving light emitting display |
| USRE49389E1 (en) | 2008-07-29 | 2023-01-24 | Ignis Innovation Inc. | Method and system for driving light emitting display |
| US9370075B2 (en) | 2008-12-09 | 2016-06-14 | Ignis Innovation Inc. | System and method for fast compensation programming of pixels in a display |
| US9824632B2 (en) | 2008-12-09 | 2017-11-21 | Ignis Innovation Inc. | Systems and method for fast compensation programming of pixels in a display |
| US11030949B2 (en) | 2008-12-09 | 2021-06-08 | Ignis Innovation Inc. | Systems and method for fast compensation programming of pixels in a display |
| US10319307B2 (en) | 2009-06-16 | 2019-06-11 | Ignis Innovation Inc. | Display system with compensation techniques and/or shared level resources |
| US9111485B2 (en) | 2009-06-16 | 2015-08-18 | Ignis Innovation Inc. | Compensation technique for color shift in displays |
| US9418587B2 (en) | 2009-06-16 | 2016-08-16 | Ignis Innovation Inc. | Compensation technique for color shift in displays |
| US10553141B2 (en) | 2009-06-16 | 2020-02-04 | Ignis Innovation Inc. | Compensation technique for color shift in displays |
| US9117400B2 (en) | 2009-06-16 | 2015-08-25 | Ignis Innovation Inc. | Compensation technique for color shift in displays |
| US9030506B2 (en) | 2009-11-12 | 2015-05-12 | Ignis Innovation Inc. | Stable fast programming scheme for displays |
| US9818376B2 (en) | 2009-11-12 | 2017-11-14 | Ignis Innovation Inc. | Stable fast programming scheme for displays |
| US10685627B2 (en) | 2009-11-12 | 2020-06-16 | Ignis Innovation Inc. | Stable fast programming scheme for displays |
| US10679533B2 (en) | 2009-11-30 | 2020-06-09 | Ignis Innovation Inc. | System and methods for aging compensation in AMOLED displays |
| US9311859B2 (en) | 2009-11-30 | 2016-04-12 | Ignis Innovation Inc. | Resetting cycle for aging compensation in AMOLED displays |
| US10304390B2 (en) | 2009-11-30 | 2019-05-28 | Ignis Innovation Inc. | System and methods for aging compensation in AMOLED displays |
| US9384698B2 (en) | 2009-11-30 | 2016-07-05 | Ignis Innovation Inc. | System and methods for aging compensation in AMOLED displays |
| US9786209B2 (en) | 2009-11-30 | 2017-10-10 | Ignis Innovation Inc. | System and methods for aging compensation in AMOLED displays |
| US10699613B2 (en) | 2009-11-30 | 2020-06-30 | Ignis Innovation Inc. | Resetting cycle for aging compensation in AMOLED displays |
| US10996258B2 (en) | 2009-11-30 | 2021-05-04 | Ignis Innovation Inc. | Defect detection and correction of pixel circuits for AMOLED displays |
| US9059117B2 (en) | 2009-12-01 | 2015-06-16 | Ignis Innovation Inc. | High resolution pixel architecture |
| US9262965B2 (en) | 2009-12-06 | 2016-02-16 | Ignis Innovation Inc. | System and methods for power conservation for AMOLED pixel drivers |
| US9093028B2 (en) | 2009-12-06 | 2015-07-28 | Ignis Innovation Inc. | System and methods for power conservation for AMOLED pixel drivers |
| US9373724B2 (en) | 2010-01-15 | 2016-06-21 | Canon Kabushiki Kaisha | Method of driving transistor and device including transistor driven by the method |
| US9430958B2 (en) | 2010-02-04 | 2016-08-30 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10971043B2 (en) | 2010-02-04 | 2021-04-06 | Ignis Innovation Inc. | System and method for extracting correlation curves for an organic light emitting device |
| US9881532B2 (en) | 2010-02-04 | 2018-01-30 | Ignis Innovation Inc. | System and method for extracting correlation curves for an organic light emitting device |
| US10395574B2 (en) | 2010-02-04 | 2019-08-27 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10032399B2 (en) | 2010-02-04 | 2018-07-24 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US9773441B2 (en) | 2010-02-04 | 2017-09-26 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US11200839B2 (en) | 2010-02-04 | 2021-12-14 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10176736B2 (en) | 2010-02-04 | 2019-01-08 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10089921B2 (en) | 2010-02-04 | 2018-10-02 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10163401B2 (en) | 2010-02-04 | 2018-12-25 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US10573231B2 (en) | 2010-02-04 | 2020-02-25 | Ignis Innovation Inc. | System and methods for extracting correlation curves for an organic light emitting device |
| US8994617B2 (en) | 2010-03-17 | 2015-03-31 | Ignis Innovation Inc. | Lifetime uniformity parameter extraction methods |
| JP2011018062A (en) * | 2010-08-23 | 2011-01-27 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
| US9489897B2 (en) | 2010-12-02 | 2016-11-08 | Ignis Innovation Inc. | System and methods for thermal compensation in AMOLED displays |
| US9997110B2 (en) | 2010-12-02 | 2018-06-12 | Ignis Innovation Inc. | System and methods for thermal compensation in AMOLED displays |
| US10460669B2 (en) | 2010-12-02 | 2019-10-29 | Ignis Innovation Inc. | System and methods for thermal compensation in AMOLED displays |
| US8907991B2 (en) | 2010-12-02 | 2014-12-09 | Ignis Innovation Inc. | System and methods for thermal compensation in AMOLED displays |
| US9134825B2 (en) | 2011-05-17 | 2015-09-15 | Ignis Innovation Inc. | Systems and methods for display systems with dynamic power control |
| US9606607B2 (en) | 2011-05-17 | 2017-03-28 | Ignis Innovation Inc. | Systems and methods for display systems with dynamic power control |
| US10515585B2 (en) | 2011-05-17 | 2019-12-24 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9886899B2 (en) | 2011-05-17 | 2018-02-06 | Ignis Innovation Inc. | Pixel Circuits for AMOLED displays |
| US10249237B2 (en) | 2011-05-17 | 2019-04-02 | Ignis Innovation Inc. | Systems and methods for display systems with dynamic power control |
| US10475379B2 (en) | 2011-05-20 | 2019-11-12 | Ignis Innovation Inc. | Charged-based compensation and parameter extraction in AMOLED displays |
| US9093029B2 (en) | 2011-05-20 | 2015-07-28 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9171500B2 (en) | 2011-05-20 | 2015-10-27 | Ignis Innovation Inc. | System and methods for extraction of parasitic parameters in AMOLED displays |
| US9589490B2 (en) | 2011-05-20 | 2017-03-07 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9530349B2 (en) | 2011-05-20 | 2016-12-27 | Ignis Innovations Inc. | Charged-based compensation and parameter extraction in AMOLED displays |
| US10580337B2 (en) | 2011-05-20 | 2020-03-03 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9355584B2 (en) | 2011-05-20 | 2016-05-31 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9799248B2 (en) | 2011-05-20 | 2017-10-24 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US10032400B2 (en) | 2011-05-20 | 2018-07-24 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US10127846B2 (en) | 2011-05-20 | 2018-11-13 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US10325537B2 (en) | 2011-05-20 | 2019-06-18 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9799246B2 (en) | 2011-05-20 | 2017-10-24 | Ignis Innovation Inc. | System and methods for extraction of threshold and mobility parameters in AMOLED displays |
| US9466240B2 (en) | 2011-05-26 | 2016-10-11 | Ignis Innovation Inc. | Adaptive feedback system for compensating for aging pixel areas with enhanced estimation speed |
| US10706754B2 (en) | 2011-05-26 | 2020-07-07 | Ignis Innovation Inc. | Adaptive feedback system for compensating for aging pixel areas with enhanced estimation speed |
| US9978297B2 (en) | 2011-05-26 | 2018-05-22 | Ignis Innovation Inc. | Adaptive feedback system for compensating for aging pixel areas with enhanced estimation speed |
| US9640112B2 (en) | 2011-05-26 | 2017-05-02 | Ignis Innovation Inc. | Adaptive feedback system for compensating for aging pixel areas with enhanced estimation speed |
| US10417945B2 (en) | 2011-05-27 | 2019-09-17 | Ignis Innovation Inc. | Systems and methods for aging compensation in AMOLED displays |
| US9773439B2 (en) | 2011-05-27 | 2017-09-26 | Ignis Innovation Inc. | Systems and methods for aging compensation in AMOLED displays |
| US10290284B2 (en) | 2011-05-28 | 2019-05-14 | Ignis Innovation Inc. | Systems and methods for operating pixels in a display to mitigate image flicker |
| US9881587B2 (en) | 2011-05-28 | 2018-01-30 | Ignis Innovation Inc. | Systems and methods for operating pixels in a display to mitigate image flicker |
| US9224954B2 (en) | 2011-08-03 | 2015-12-29 | Ignis Innovation Inc. | Organic light emitting diode and method of manufacturing |
| US8901579B2 (en) | 2011-08-03 | 2014-12-02 | Ignis Innovation Inc. | Organic light emitting diode and method of manufacturing |
| US9070775B2 (en) | 2011-08-03 | 2015-06-30 | Ignis Innovations Inc. | Thin film transistor |
| US9385169B2 (en) | 2011-11-29 | 2016-07-05 | Ignis Innovation Inc. | Multi-functional active matrix organic light-emitting diode display |
| US9818806B2 (en) | 2011-11-29 | 2017-11-14 | Ignis Innovation Inc. | Multi-functional active matrix organic light-emitting diode display |
| US10079269B2 (en) | 2011-11-29 | 2018-09-18 | Ignis Innovation Inc. | Multi-functional active matrix organic light-emitting diode display |
| US10453904B2 (en) | 2011-11-29 | 2019-10-22 | Ignis Innovation Inc. | Multi-functional active matrix organic light-emitting diode display |
| US10089924B2 (en) | 2011-11-29 | 2018-10-02 | Ignis Innovation Inc. | Structural and low-frequency non-uniformity compensation |
| US10380944B2 (en) | 2011-11-29 | 2019-08-13 | Ignis Innovation Inc. | Structural and low-frequency non-uniformity compensation |
| US10043448B2 (en) | 2012-02-03 | 2018-08-07 | Ignis Innovation Inc. | Driving system for active-matrix displays |
| US9343006B2 (en) | 2012-02-03 | 2016-05-17 | Ignis Innovation Inc. | Driving system for active-matrix displays |
| US10453394B2 (en) | 2012-02-03 | 2019-10-22 | Ignis Innovation Inc. | Driving system for active-matrix displays |
| US9792857B2 (en) | 2012-02-03 | 2017-10-17 | Ignis Innovation Inc. | Driving system for active-matrix displays |
| US9747834B2 (en) | 2012-05-11 | 2017-08-29 | Ignis Innovation Inc. | Pixel circuits including feedback capacitors and reset capacitors, and display systems therefore |
| US10424245B2 (en) | 2012-05-11 | 2019-09-24 | Ignis Innovation Inc. | Pixel circuits including feedback capacitors and reset capacitors, and display systems therefore |
| US9368063B2 (en) | 2012-05-23 | 2016-06-14 | Ignis Innovation Inc. | Display systems with compensation for line propagation delay |
| US9536460B2 (en) | 2012-05-23 | 2017-01-03 | Ignis Innovation Inc. | Display systems with compensation for line propagation delay |
| US9940861B2 (en) | 2012-05-23 | 2018-04-10 | Ignis Innovation Inc. | Display systems with compensation for line propagation delay |
| US8922544B2 (en) | 2012-05-23 | 2014-12-30 | Ignis Innovation Inc. | Display systems with compensation for line propagation delay |
| US9741279B2 (en) | 2012-05-23 | 2017-08-22 | Ignis Innovation Inc. | Display systems with compensation for line propagation delay |
| US10176738B2 (en) | 2012-05-23 | 2019-01-08 | Ignis Innovation Inc. | Display systems with compensation for line propagation delay |
| US9978310B2 (en) | 2012-12-11 | 2018-05-22 | Ignis Innovation Inc. | Pixel circuits for amoled displays |
| US11030955B2 (en) | 2012-12-11 | 2021-06-08 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9786223B2 (en) | 2012-12-11 | 2017-10-10 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9685114B2 (en) | 2012-12-11 | 2017-06-20 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US10311790B2 (en) | 2012-12-11 | 2019-06-04 | Ignis Innovation Inc. | Pixel circuits for amoled displays |
| US9997106B2 (en) | 2012-12-11 | 2018-06-12 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US10140925B2 (en) | 2012-12-11 | 2018-11-27 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9336717B2 (en) | 2012-12-11 | 2016-05-10 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US11875744B2 (en) | 2013-01-14 | 2024-01-16 | Ignis Innovation Inc. | Cleaning common unwanted signals from pixel measurements in emissive displays |
| US10847087B2 (en) | 2013-01-14 | 2020-11-24 | Ignis Innovation Inc. | Cleaning common unwanted signals from pixel measurements in emissive displays |
| US9171504B2 (en) | 2013-01-14 | 2015-10-27 | Ignis Innovation Inc. | Driving scheme for emissive displays providing compensation for driving transistor variations |
| US9830857B2 (en) | 2013-01-14 | 2017-11-28 | Ignis Innovation Inc. | Cleaning common unwanted signals from pixel measurements in emissive displays |
| US9721505B2 (en) | 2013-03-08 | 2017-08-01 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9697771B2 (en) | 2013-03-08 | 2017-07-04 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US10013915B2 (en) | 2013-03-08 | 2018-07-03 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US10242619B2 (en) | 2013-03-08 | 2019-03-26 | Ignis Innovation Inc. | Pixel circuits for amoled displays |
| US9351368B2 (en) | 2013-03-08 | 2016-05-24 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US10593263B2 (en) | 2013-03-08 | 2020-03-17 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9934725B2 (en) | 2013-03-08 | 2018-04-03 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9922596B2 (en) | 2013-03-08 | 2018-03-20 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US9659527B2 (en) | 2013-03-08 | 2017-05-23 | Ignis Innovation Inc. | Pixel circuits for AMOLED displays |
| US10198979B2 (en) | 2013-03-14 | 2019-02-05 | Ignis Innovation Inc. | Re-interpolation with edge detection for extracting an aging pattern for AMOLED displays |
| US9818323B2 (en) | 2013-03-14 | 2017-11-14 | Ignis Innovation Inc. | Re-interpolation with edge detection for extracting an aging pattern for AMOLED displays |
| US9305488B2 (en) | 2013-03-14 | 2016-04-05 | Ignis Innovation Inc. | Re-interpolation with edge detection for extracting an aging pattern for AMOLED displays |
| US9536465B2 (en) | 2013-03-14 | 2017-01-03 | Ignis Innovation Inc. | Re-interpolation with edge detection for extracting an aging pattern for AMOLED displays |
| US9952698B2 (en) | 2013-03-15 | 2018-04-24 | Ignis Innovation Inc. | Dynamic adjustment of touch resolutions on an AMOLED display |
| US9324268B2 (en) | 2013-03-15 | 2016-04-26 | Ignis Innovation Inc. | Amoled displays with multiple readout circuits |
| US9721512B2 (en) | 2013-03-15 | 2017-08-01 | Ignis Innovation Inc. | AMOLED displays with multiple readout circuits |
| US9997107B2 (en) | 2013-03-15 | 2018-06-12 | Ignis Innovation Inc. | AMOLED displays with multiple readout circuits |
| US10460660B2 (en) | 2013-03-15 | 2019-10-29 | Ingis Innovation Inc. | AMOLED displays with multiple readout circuits |
| US10867536B2 (en) | 2013-04-22 | 2020-12-15 | Ignis Innovation Inc. | Inspection system for OLED display panels |
| US9990882B2 (en) | 2013-08-12 | 2018-06-05 | Ignis Innovation Inc. | Compensation accuracy |
| US9437137B2 (en) | 2013-08-12 | 2016-09-06 | Ignis Innovation Inc. | Compensation accuracy |
| US10600362B2 (en) | 2013-08-12 | 2020-03-24 | Ignis Innovation Inc. | Compensation accuracy |
| US9741282B2 (en) | 2013-12-06 | 2017-08-22 | Ignis Innovation Inc. | OLED display system and method |
| US10186190B2 (en) | 2013-12-06 | 2019-01-22 | Ignis Innovation Inc. | Correction for localized phenomena in an image array |
| US9761170B2 (en) | 2013-12-06 | 2017-09-12 | Ignis Innovation Inc. | Correction for localized phenomena in an image array |
| US10395585B2 (en) | 2013-12-06 | 2019-08-27 | Ignis Innovation Inc. | OLED display system and method |
| US9502653B2 (en) | 2013-12-25 | 2016-11-22 | Ignis Innovation Inc. | Electrode contacts |
| US10439159B2 (en) | 2013-12-25 | 2019-10-08 | Ignis Innovation Inc. | Electrode contacts |
| US9831462B2 (en) | 2013-12-25 | 2017-11-28 | Ignis Innovation Inc. | Electrode contacts |
| US10997901B2 (en) | 2014-02-28 | 2021-05-04 | Ignis Innovation Inc. | Display system |
| US10176752B2 (en) | 2014-03-24 | 2019-01-08 | Ignis Innovation Inc. | Integrated gate driver |
| US10192479B2 (en) | 2014-04-08 | 2019-01-29 | Ignis Innovation Inc. | Display system using system level resources to calculate compensation parameters for a display module in a portable device |
| US10170522B2 (en) | 2014-11-28 | 2019-01-01 | Ignis Innovations Inc. | High pixel density array architecture |
| US9842889B2 (en) | 2014-11-28 | 2017-12-12 | Ignis Innovation Inc. | High pixel density array architecture |
| US10134325B2 (en) | 2014-12-08 | 2018-11-20 | Ignis Innovation Inc. | Integrated display system |
| US10726761B2 (en) | 2014-12-08 | 2020-07-28 | Ignis Innovation Inc. | Integrated display system |
| US10181282B2 (en) | 2015-01-23 | 2019-01-15 | Ignis Innovation Inc. | Compensation for color variations in emissive devices |
| US10152915B2 (en) | 2015-04-01 | 2018-12-11 | Ignis Innovation Inc. | Systems and methods of display brightness adjustment |
| US10311780B2 (en) | 2015-05-04 | 2019-06-04 | Ignis Innovation Inc. | Systems and methods of optical feedback |
| US9947293B2 (en) | 2015-05-27 | 2018-04-17 | Ignis Innovation Inc. | Systems and methods of reduced memory bandwidth compensation |
| US10403230B2 (en) | 2015-05-27 | 2019-09-03 | Ignis Innovation Inc. | Systems and methods of reduced memory bandwidth compensation |
| US10657895B2 (en) | 2015-07-24 | 2020-05-19 | Ignis Innovation Inc. | Pixels and reference circuits and timing techniques |
| US10373554B2 (en) | 2015-07-24 | 2019-08-06 | Ignis Innovation Inc. | Pixels and reference circuits and timing techniques |
| US10410579B2 (en) | 2015-07-24 | 2019-09-10 | Ignis Innovation Inc. | Systems and methods of hybrid calibration of bias current |
| US10339860B2 (en) | 2015-08-07 | 2019-07-02 | Ignis Innovation, Inc. | Systems and methods of pixel calibration based on improved reference values |
| WO2017043572A1 (en) * | 2015-09-11 | 2017-03-16 | 三菱電機株式会社 | Thin film transistor substrate and method for producing same |
| JPWO2017043572A1 (en) * | 2015-09-11 | 2017-11-16 | 三菱電機株式会社 | Thin film transistor substrate and manufacturing method thereof |
| US10102808B2 (en) | 2015-10-14 | 2018-10-16 | Ignis Innovation Inc. | Systems and methods of multiple color driving |
| US10446086B2 (en) | 2015-10-14 | 2019-10-15 | Ignis Innovation Inc. | Systems and methods of multiple color driving |
| US10204540B2 (en) | 2015-10-26 | 2019-02-12 | Ignis Innovation Inc. | High density pixel pattern |
| JP2017163139A (en) * | 2016-03-08 | 2017-09-14 | 株式会社半導体エネルギー研究所 | Imaging device, module, and electronic apparatus |
| US10586491B2 (en) | 2016-12-06 | 2020-03-10 | Ignis Innovation Inc. | Pixel circuits for mitigation of hysteresis |
| US10714018B2 (en) | 2017-05-17 | 2020-07-14 | Ignis Innovation Inc. | System and method for loading image correction data for displays |
| US11025899B2 (en) | 2017-08-11 | 2021-06-01 | Ignis Innovation Inc. | Optical correction systems and methods for correcting non-uniformity of emissive display devices |
| US11792387B2 (en) | 2017-08-11 | 2023-10-17 | Ignis Innovation Inc. | Optical correction systems and methods for correcting non-uniformity of emissive display devices |
| US10971078B2 (en) | 2018-02-12 | 2021-04-06 | Ignis Innovation Inc. | Pixel measurement through data line |
| US11847976B2 (en) | 2018-02-12 | 2023-12-19 | Ignis Innovation Inc. | Pixel measurement through data line |
| CN110212035B (en) * | 2018-08-10 | 2023-12-19 | 友达光电股份有限公司 | Transistor structure and method of operating the same |
| CN110212035A (en) * | 2018-08-10 | 2019-09-06 | 友达光电股份有限公司 | Transistor arrangement and its operating method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0990405A (en) | Thin-film transistor | |
| KR100277617B1 (en) | Display | |
| US5712495A (en) | Semiconductor device including active matrix circuit | |
| US5712494A (en) | Thin film field effect transistor having an extension portion acting as a light shield and back gate | |
| US5877514A (en) | Liquid crystal display device integrated with driving circuit and method for fabricating the same | |
| US5940151A (en) | Liquid crystal display and method for fabricating the same | |
| US6828585B2 (en) | Thin-film transistor, method for fabricating the same, and liquid crystal display device | |
| US6310670B1 (en) | Thin-film transistor (TFT) liquid crystal display (LCD) devices having field-induced LDD regions | |
| JPH02168630A (en) | Thin film transistor, its | |
| JPH10163498A (en) | Thin film transistor, fabrication thereof and liquid crystal display | |
| US6713825B2 (en) | Poly-crystalline thin film transistor and fabrication method thereof | |
| JPH09107102A (en) | Thin-film transistor and preparation thereof | |
| US5767531A (en) | Thin-film transistor, method of fabricating the same, and liquid-crystal display apparatus | |
| US6124153A (en) | Method for manufacturing a polysilicon TFT with a variable thickness gate oxide | |
| JPH0982969A (en) | Thin-film transistor and liquid-crystal display | |
| JP2001085695A (en) | Method for manufacturing semiconductor device, manufacture of active matrix substrate and electro- optical device | |
| JPH08250742A (en) | Semiconductor device | |
| JPH04360583A (en) | Thin film transistor | |
| JP3643025B2 (en) | Active matrix display device and manufacturing method thereof | |
| JPH08116067A (en) | Semiconductor device, display device and manufacture of display device | |
| JPH08148694A (en) | Thin-film transistor | |
| JPH05275701A (en) | Thin-film transistor | |
| JPH06169086A (en) | Polycrystalline silicon thin film transistor | |
| JP3603968B2 (en) | Thin film transistor and method for manufacturing the same | |
| JPH0682834A (en) | Active matrix panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20021203 |