KR0171287B1 - Multi-queue control method of main memory unit - Google Patents

Abstract

According to the present invention, a memory controller 1, a plurality of input queues 2, and a plurality of output queues 3 are controlled via a queue controller 4 on a processor board, without retrying requests from the system bus. The present invention relates to a multi-queue control method of main memory to improve the overall system performance by providing the information stored in a queue.

Description

Multiple queue control method of main memory

1 is a block diagram of a conventional single queue controller.

2 is a first-in, first-out (FIFO) memory configuration of the present invention.

3 is a signal flow diagram for explaining the operation of the multi-queue controller of the present invention.

a) is an operation description signal flow diagram of the input address queue;

b) is a signal flow diagram describing the operation of the input data queue.

c) is a signal flow diagram illustrating the operation of the output queue and data queue.

* Explanation of symbols for main parts of the drawings

1: Memory Controller 2: Input Cue

3: output queue 4: queue controller

5: system bus interface

The present invention relates to a method of controlling a queue of a main memory device in a multi-processor system employing a continuous bus protocol or a system based on a similar logical architecture. In particular, it aims to improve the overall system performance by storing and providing them in a queue without retrying requests from the system bus.

The conventional single queue control system has a memory controller 1 and a bus interface 5 and a memory controller 1 (DMC or higher module) that control the input queue 2 and the output queue 3 as shown in FIG. If the bus interface cannot handle this when the input queue (2) and the memory controller (1), which serve to temporarily store requests coming from the bus, wish to transfer data to the system bus, Data and addresses and a queue controller (4) consisting of an output queue (3) serving as a temporary storage and a logic controlling the input queue (2) and the output queue (3) in order to efficiently handle consecutive memory access requests. It consists of a system bus interface (5) that connects memory and a processor, and logic for controlling it is also composed of PAL (Programmable Array Logic).

As described above, in the conventional main memory controlling method, when a processor requests data or an address through a system bus, the queue controller 4 controls the system bus while sequentially controlling the input queue 2 and the output queue 3. Respond to data or address requests from the processor. However, the conventional main memory queue control method is composed of a single queue, which limits the response to consecutive memory requests, resulting in a high retry rate for the memory, resulting in lower overall system performance. The queue control logic is configured with PAL (Programmable Array Logic), which makes it difficult to cope with system property change requests (spec changes).

Accordingly, an object of the present invention is to queue a main memory in a multiprocessor system employing a Pended Bus Protocol or similar logical architecture to improve the problems of the prior art. It provides multi-queue control method of main memory so that overall system performance is improved by providing control method, and saving and providing in request without retrying processor request through system bus.

The control method of the present invention for achieving the above object is a process of temporarily storing the input address and data in the input queue (2) consisting of a plurality of stages, and the output queue (3) consisting of a plurality of stages of the address and data to be output ), And cache related queue processing.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of a first-in, first-out (FIFO) memory, which raises valid data from a data input line IN to which data required by a processor is input, and an output line OUT to output data according to a processor's request. Load clock stored at the edge of the first-in first-out memory and the unload clock and first-in first-out memory that takes the information of the first-in first-out memory by activating the corresponding signal if necessary in the upper module. It consists of a full line indicating the status and an empty line indicating the empty data in the first-in first-out memory.

The data input / output (IN / OUT) line inputs and outputs data required by the processor, and the load clock line (LDCLK) transfers valid data from the input to the first-in, first-out (FIFO) memory at the rising edge. The unload clock line (UNCLK) sends the data of the first-in first-out memory one by one by activating the corresponding signal from the upper module if necessary, and checks whether the first-in first-out memory is empty or full and full and empty. Inform via

The memory controller 1 controls the input queue 2 and the output queue 3 on the processor board, and is located between the bus interface 5 and the memory controller 1 (DMC or higher module) and enters the bus. An input queue (2) that temporarily stores requests, and an output that temporarily stores data when the bus interface cannot handle it when the memory controller (1) wants to transfer data to the system bus A queue controller (4) consisting of a queue (3), logic to control multiple stage input queues (2) and output queues (3) to efficiently process consecutive memory access requests, and data and addresses It consists of a system bus interface (5) that connects to the processor, and the logic for controlling it is also composed of PAL (Programmable Array Logic).

The input queue (2) (1) is located between the bus interface 5 and the memory controller 1 (DMC or higher level module) and temporarily stores a request coming from the bus. It consists of multiple first-in first-out (FIFO) memory, so that when the memory controller 1 is in a busy wait state and there are no requests stored in the queue, the request of the bus can be processed without time delay. If it is busy and the queue is empty, it stores the processor's requests as much as first-in, first-out (FIFO) storage capability. The information stored in the queue is address, data (when written), address tag, transfer type, byte enable, and memory lock status.

The input queue 2 is composed of a first-in, first-out (FIFO) memory of a plurality of stages (usually 64 or more stages).

The output queue 3 (OutPut Queue) serves to temporarily store data when the memory controller 1 wishes to transfer data to the system bus when the bus interface cannot handle it. If the queue is composed of multiple stages and the bus interface is able to process data, it operates in the transparent mode like the input queue (2). If the bus interface is busy, the memory controller (1) The data is sequentially queued, and the data is sequentially driven by the bus according to the state of the bus.

The information stored in the queue is address tag and data, and like the input queue 2, it is composed of a multi-stage (FIFO) memory.

The queue controller 4 is composed of logic for controlling the input queue 2 and the output queue 3 of multiple stages to efficiently process consecutive memory access requests.

The role of the input queue 2 is to reduce the bus utilization rate by temporarily storing new requests arriving when the memory controller 1 is processing an earlier request or performing a new operation, thereby reducing the retry of the bus according to the busy response. And fast data access time.

The output queue 3 is a place where data can be temporarily stored in response to a read request.

By keeping the data bus occupied and storing the data when the transfer of data is delayed, the memory controller 1 makes it possible to handle new requests.

The operation principle of the input queue 2 is to operate in the pass-through mode when the memory controller 1 does not operate, and if the memory controller 1 is processing the preceding request, the pipe line of the data transfer protocol of the bus Each step is tracked and the stored request is sent to the memory controller 1 when the controller is ready for data processing.

3 is a signal flow diagram for explaining the operation of the multi-queue control method of the present invention. A) illustrates a process of storing a corresponding address in a first-in first-out memory. The information detection step from the bus interface and whether the detected address is valid are shown in FIG. Determining whether the queue is full; if the queue is full; notifying the retry logic if the queue is full; and if the queue is empty, queue the data at the corresponding address. It consists of storing in.

(b) describes a process of storing the corresponding data in the first-in, first-out memory, determining whether the address queue is in operation, determining whether to perform the write operation, and storing the data in the first-in, first-out memory. Is made of.

(c) describes the process of outputting the address and data from the first-in first-out memory to the upper module, determining whether the first-in first-out memory is empty, and if the queue is not empty, whether the memory controller 1 is ready. And determining an address and data from the first-in first-out memory to the upper module.

On the other hand, there is a queue area related to the cache in the input queue, which stores cache state related information corresponding to each input address queue.

The cache state indicates whether the address is shared or whether memory can be accessed.

In relation to the cache, the queue is activated from the moment the address queue is operated, and at least three state-machines are operated in case a continuous memory reference is generated.

Therefore, the time delay that may occur due to the presence of the queue is excluded, and the output queue 3 stores the data processed by the memory controller 1 and the slot address of the processor to be transmitted.

The storage function is performed only when the bus interface is not ready to transmit. Otherwise, it operates in pass-through mode so that there is no time delay caused by the queue.

As described above, the present invention provides an input queue 2 and an output queue 3 configured as multiple queues in a tightly coupled multi-processor system in which multiple processors require a common memory. By responding quickly to the demands of the processor, it is possible to prevent time delay and improve the performance of the system.

Claims (5)

An input queue address process of storing a corresponding address in a first-in first-out memory, an input data process of storing corresponding data in a first-in first-out memory, a process of temporarily storing an address and data to be output in an output queue consisting of a plurality of stages; A method for controlling multiple queues in a main memory, comprising cache related queues. The method of claim 1, wherein the input queue address process comprises: detecting an information from a bus interface; determining whether the detected address is valid; determining whether the queue is full; and if the queue is full. And informing the retry logic of the corresponding information, and if the queue is empty, storing the corresponding address in the first-in, first-out memory. The method of claim 1, wherein the input data queue process includes determining whether an address queue is in operation, determining whether to perform a write operation, and storing the data in a first-in first-out memory when the write operation is performed. Method of controlling a multi-queue of the main memory, characterized in that consisting of. 2. The process of claim 1, wherein temporarily storing the address and data to be output in a queue consisting of a plurality of stages includes determining whether the first-in, first-out memory is empty, and if the queue is not empty, the memory controller 1 is prepared. And determining the presence or absence, and sending an address and data to a higher module by first-in first-out. The process of operating the cache-related queue is activated from the moment the address queue is operated, and at least three state-machines are operated in preparation for a continuous memory reference. How to control multiple queues in storage.