KR0164073B1 - Semiconductor device menufacturing method - Google Patents
Semiconductor device menufacturing method Download PDFInfo
- Publication number
- KR0164073B1 KR0164073B1 KR1019950030483A KR19950030483A KR0164073B1 KR 0164073 B1 KR0164073 B1 KR 0164073B1 KR 1019950030483 A KR1019950030483 A KR 1019950030483A KR 19950030483 A KR19950030483 A KR 19950030483A KR 0164073 B1 KR0164073 B1 KR 0164073B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxygen
- semiconductor device
- thin film
- plasma treatment
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 원자외선용 감광막과 상호작용하여 테일이나 잔유물이 남는 감광막패턴을 형성하는 물질로 형성된 박막 상부에 감광막패턴을 형성하는데 있어서, 감광막 패터닝전, 산소가스와 같은 반응성 산소플라즈마나 반응성 이온주입방법을 이용하여 상기 박막의 표면을 개질화시킴으로써 테일이나 잔유물이 없는 균일한 감광막패턴을 형성하고 이를 이용하여 반도체소자를 이용함으로써 단락이나 합선 등을 방지할 수 있어 반도체소자의 특성, 수율 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in forming a photoresist pattern on a thin film formed of a material that interacts with a photoresist for far ultraviolet rays to form a photoresist pattern in which tails or residues remain, before photoresist patterning, such as oxygen gas. By modifying the surface of the thin film by using reactive oxygen plasma or reactive ion implantation method, a uniform photoresist pattern without tail or residue is formed, and by using the semiconductor device, short circuit or short circuit can be prevented by using the semiconductor device. It is a technology to improve the characteristics, yield and reliability of the semiconductor device according to the high integration.
Description
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 13 : 패드산화막11 semiconductor substrate 13 pad oxide film
15 : 실리콘질화막 17 : 개질화된 영역15 silicon nitride film 17 modified region
19 : 감광막 21 : 노광마스크19: photosensitive film 21: exposure mask
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 표면의 오염을 극복하기 위하여 플라즈마처리함으로써 표면을 개질화하여 균일한 선폭의 패턴을 형성공정, 하지의존성이 있는 물질의 증착공정 그리고 피증착물의 점착력을 증가시키는 공정에 사용함으로써 반도체소자의 특성, 수율 및 신뢰성을 향상시키는데 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, the plasma treatment is performed to overcome surface contamination, thereby modifying the surface to form a pattern having a uniform line width, a process of depositing a material having dependence on the ground, and adhesion of a deposit. The present invention relates to improving the characteristics, yield and reliability of semiconductor devices by using them in increasing processes.
종래의 반도체 소자 제조방법은 원자외선(DUV)을 광원으로 하는 노광공정시, 원자외선용 감광막 내부의 산성분은 원자외선을 받아 감광막을 유화시키는데 중요한 역할을 하며 대기 중의 암모니아기 또는 기판 내의 질소성분과 반응하여 중성화되어 감광막과 반도체기판의 접합부분에서의 산성분 농도가 감소하므로 후공정인 현상공정후에 테일(tail)이나 잔유물이 있는 감광막패턴이 형성한다. 이로인하여, 감광막패턴을 이용한 식각공정으로 형성된 패턴은 단선 및 합선 등이 발생되어 반도체 소자의 특성, 수율 및 신뢰성을 저하시키며 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.In the conventional semiconductor device manufacturing method, during the exposure process using the ultraviolet (DUV) as a light source, the acid component inside the ultraviolet ray photosensitive film plays an important role in emulsifying the photosensitive film by receiving the ultraviolet ray. It is neutralized in the reaction and the acid component concentration at the junction between the photoresist film and the semiconductor substrate is reduced, so that a photoresist pattern with tails or residues is formed after the development process. As a result, a pattern formed by an etching process using a photoresist pattern may cause disconnection and short circuit, thereby degrading characteristics, yield, and reliability of the semiconductor device, thereby making it difficult to integrate the semiconductor device.
여기서, 산성분의 감소는 기판의 오염 또는 반도체기판의 질소함유정도가 큰 경우 발생한다.Here, the decrease in acid content occurs when the contamination of the substrate or the nitrogen content of the semiconductor substrate is large.
따라서, 본 발명은 종래기술의 문제점을 해결하기 위하여, 반도체기판 표면으로부터 수백 Å 두께의 물성을 개질화함으로써 반도체소자의 특성, 수율 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the problems of the prior art, the semiconductor device can improve the characteristics, yield and reliability of the semiconductor device and thereby high integration of the semiconductor device by modifying the properties of the thickness of several hundred micrometers from the surface of the semiconductor substrate. The purpose is to provide a manufacturing method.
이상의 목적을 달성하기 위한 본 발명인 반도체 소자 제조방법의 특징은, 물질층이 형성된 반도체기판 상부에 원자외선용 감광막과 상호반응하여 테일이나 잔유물을 발생시키는 물질로 박막을 형성하는 공정과, 상기 박막 표면을 반응성 플라즈마처리하여 표면개질화함으로써 박막 표면에 일정두께의 산화막을 형성하는 공정과, 상기 박막 상부에 원자외선용 감광막을 도포하는 공정과, 상기 감광막을 노광 및 현상하여 테일이나 잔유물이 없는 균일한 감광막패턴을 형성하는 공정을 포함하는데 있다.A semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a thin film made of a material generating a tail or residue by interacting with the photosensitive film for far ultraviolet rays on the semiconductor substrate on which the material layer is formed, and the surface of the thin film To form an oxide film having a predetermined thickness on the surface of the thin film by surface modification by reactive plasma treatment, to apply an ultraviolet-ray photosensitive film on the thin film, and to expose and develop the photosensitive film to produce a uniform tail or residue. It includes a step of forming a photosensitive film pattern.
여기서, 상기 반응성 플라즈마는 산소플라즈마이고, 상기 표면개질화공정은 1 내지 50KeV의 낮은 에너지를 이용한 산소이온주입공정으로 공정으로 형성되고, 상기 산소플라즈마처리조건은 산소가스유량 0 내지 10slm, 반응실압력 10-3내지 100Torr, 플라즈마발생전원 13.56MHz의 고주파 그리고 전력은 0 내지 10KW이거나, 상기 산소플라즈마처리조건은 산소가스유량 0 내지 10slm, 반응실압력 10-3내지 100Torr, 플라즈마발생전원 2.45GHz의 초고주파 그리고 전력은 0 내지 10KW이고, 상기 산소플라즈마처리조건은 상기 반도체기판에 수백 KHz의 저주파, 13.56MHz의 고주파 또는 디.씨.(DC) 바이어스가 0 내지 10킬로와트(KW) 인가되며, 상기 산소플라즈마처리조건은 상기 산소가스 대신에 N2O 가스 0 내지 10slm 그리고 SiH4가스 0 내지 1000 SCCM이 사용될 수 있다.Here, the reactive plasma is an oxygen plasma, the surface modification process is formed by an oxygen ion injection process using a low energy of 1 to 50 KeV, the oxygen plasma treatment conditions are oxygen gas flow rate of 0 to 10 slm, reaction chamber pressure 10 -3 to 100 Torr, plasma generating power 13.56 MHz high frequency and power is 0 to 10 KW, or the oxygen plasma treatment conditions are oxygen gas flow rate of 0 to 10 slm, reaction chamber pressure 10 -3 to 100 Torr, plasma generating power 2.45 GHz ultra high frequency And the power is 0 to 10KW, the oxygen plasma treatment condition is a low frequency of hundreds of KHz, a high frequency or DC (DC) bias of 13.56MHz is applied to the semiconductor substrate 0 to 10 kilowatts (KW), the oxygen plasma As the treatment conditions, N 2 O gas 0 to 10 slm and SiH 4 gas 0 to 1000 SCCM may be used instead of the oxygen gas.
그리고, 상기 플라즈마처리로 개질화된 산화막은 10 내지 500Å 두께로 형성된다.In addition, the oxide film modified by the plasma treatment is formed to a thickness of 10 to 500Å.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체 소자 제조방법을 도시한 단면도로서, 소자분리절연막을 형성공정 중 버즈빅을 방지하기 위한 절연막패턴 형성공정에 관한 것이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and relates to a process of forming an insulating layer pattern for preventing buzz big during the process of forming a device isolation insulating film.
제1a도를 참조하면, 반도체기판(11) 상부에 패드산화막(13)을 형성하고 그 상부에 버즈빅(bird's beak)을 억제할 수 있는 실리콘질화막(15)을 300 내지 500Å 두께 형성한다. 그리고, 상기 실리콘질화막(15) 표면을 산소플라즈마처리하여 표면으로부터 10 내지 200Å 두께를 개질화함으로써 개질화된 영역(17)을 형성한다.Referring to FIG. 1A, a pad oxide film 13 is formed on the semiconductor substrate 11, and a silicon nitride film 15 that is capable of suppressing bird's beak is formed on the semiconductor substrate 11 to have a thickness of 300 to 500 μm. Then, the surface of the silicon nitride film 15 is subjected to oxygen plasma treatment to form a modified region 17 by modifying a thickness of 10 to 200 microseconds from the surface.
이때, 상기 산소플라즈마처리조건은 산소가스유량 0 내지 10slm, 반응실압력 10-3 내지 100Torr로 하고, 플라즈마발생전원은 13.56MHz의 고주파나 2.45GHz의 초고주파를 이용하며 전력은 0 내지 10KW을 사용한다. 그리고, 필요에 따라 기판에 수백 KHz의 저주파, 13.56MHz의 고주파 또는 디.씨.(DC) 바이어스를 0 내지 10KW 인가하여 실시할 수 있다. 그리고, 상기 산소가스는 N2O 가스 0 내지 10slm 그리고 SiH4가스 0 내지 1000 SCCM를 대신 사용할 수 있다.At this time, the oxygen plasma treatment conditions are the oxygen gas flow rate of 0 to 10 slm, the reaction chamber pressure of 10-3 to 100 Torr, the plasma generating power source uses a high frequency of 13.56 MHz or ultra-high frequency of 2.45 GHz, the power of 0 to 10 KW. . Then, if necessary, a low frequency of several hundred KHz, a high frequency of 13.56 MHz, or a DC (DC) bias may be applied to the substrate by applying 0 to 10 KW. In addition, the oxygen gas may use N 2 O gas 0 to 10 slm and SiH 4 gas 0 to 1000 SCCM instead.
여기서, 개질화된 영역(17)은 1 내지 50KeV의 낮은 에너지로 산소 이온을 임플란트(implantation) 하여 상기 실리콘질화막(15)의 표면을 개질화함으로써 형성할 수도 있다.The modified region 17 may be formed by implanting oxygen ions with a low energy of 1 to 50 KeV to modify the surface of the silicon nitride film 15.
제1b도를 참조하면, 전체표면상부에 원자외선용 감광막(19)을 도포한다. 그리고, 노광마스크(21)를 이용한 노광공정을 실시한다. 이때, 상기 노광공정은 광원을 원자외선으로 하여 실시된 것이다.Referring to FIG. 1B, an ultraviolet ray photosensitive film 19 is applied over the entire surface. And the exposure process using the exposure mask 21 is performed. At this time, the exposure step is performed using the light source as far ultraviolet rays.
제1c도를 참조하면, 상기 노광된 감광막(19)을 현상하여 감광막(19)패턴을 형성하되, 테일이나 잔유물이 남지않는 감광막(19)패턴을 형성한다.Referring to FIG. 1C, the exposed photoresist layer 19 is developed to form a photoresist layer 19 pattern, and forms a photoresist layer 19 pattern in which no tail or residue remains.
제1d도를 참조하면, 상기 감광막(19)패턴을 마스크로하여 상기 실리콘질화막(15)을 식각함으로써 균일한 실리콘질화막(15)패턴을 형성한다.Referring to FIG. 1D, the silicon nitride film 15 is etched using the photosensitive film 19 pattern as a mask to form a uniform silicon nitride film 15 pattern.
본 발명은 본 발명의 실시예에서 사용된 실리콘질화막 대신에 상기 실리콘질화막과 같이 원자외선용 감광막과 상호작용을 일으켜 테일이나 잔유물을 발생시키는 티타늄질화막(TiN), 실리콘산화질화막(SiON), 피.에스.지.(PSG : Phospho Silicate Glass, 이하에서 PSG 라 함) 또는 비.피.에스.지(BPSG : Boro Phospho Silicate Glass, 이하에서 BPSG 라 함)를 사용하는 경우에도 적용할 수 있다.The present invention is a titanium nitride film (TiN), silicon oxynitride film (SiON), P. instead of the silicon nitride film used in the embodiment of the present invention to generate a tail or residue by interacting with an ultraviolet ray photosensitive film like the silicon nitride film. It is also applicable to the use of S.G. (PSG: Phospho Silicate Glass, hereinafter PSG) or B.P.S.G (BPSG: Boro Phospho Silicate Glass, hereinafter BPSG).
이상에서 설명한 바와 같이 본 발명에 따른 반도체 소자 제조방법은, 감광막 하부의 박막표면을 개질화하여 표면오염이나 박막내부에 함유된 질소로 인하여 발생될 수 있는 감광막의 테일 및 잔유물을 방지함으로써 균일한 감광막패턴을 형성하고 후공정에서 균일한 박막패턴을 형성할 수 있어 단락이나 합선 등의 현상을 방지함으로써 반도체소자의 수율, 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention may modify the thin film surface under the photosensitive film to prevent the tail and residues of the photosensitive film which may be generated due to surface contamination or nitrogen contained in the thin film. By forming a pattern and forming a uniform thin film pattern in a later step, it is possible to prevent short circuits or short circuits, thereby improving yield, characteristics, and reliability of the semiconductor device, thereby enabling high integration of the semiconductor device.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950030483A KR0164073B1 (en) | 1995-09-18 | 1995-09-18 | Semiconductor device menufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950030483A KR0164073B1 (en) | 1995-09-18 | 1995-09-18 | Semiconductor device menufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970018193A KR970018193A (en) | 1997-04-30 |
| KR0164073B1 true KR0164073B1 (en) | 1999-02-01 |
Family
ID=19427109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950030483A KR0164073B1 (en) | 1995-09-18 | 1995-09-18 | Semiconductor device menufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0164073B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100472031B1 (en) * | 2002-08-07 | 2005-03-10 | 동부아남반도체 주식회사 | Method for fabrication of semiconductor device |
-
1995
- 1995-09-18 KR KR1019950030483A patent/KR0164073B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100472031B1 (en) * | 2002-08-07 | 2005-03-10 | 동부아남반도체 주식회사 | Method for fabrication of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970018193A (en) | 1997-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3161040B2 (en) | Method for manufacturing semiconductor device | |
| EP0581280A2 (en) | Pattern forming method | |
| US4330569A (en) | Method for conditioning nitride surface | |
| CN111326413A (en) | Plasma etching method and plasma etching apparatus | |
| US6969683B2 (en) | Method of preventing resist poisoning in dual damascene structures | |
| US6051282A (en) | Surface treatment of antireflective layer in chemical vapor deposition process | |
| JPH06177089A (en) | Manufacture of semiconductor device | |
| US20050208733A1 (en) | Oxygen plasma treatment for a nitride surface to reduce photo footing | |
| US5563098A (en) | Buried contact oxide etch with poly mask procedure | |
| KR0164073B1 (en) | Semiconductor device menufacturing method | |
| US4552831A (en) | Fabrication method for controlled via hole process | |
| JPH0883786A (en) | Manufacture of semiconductor device | |
| JPH05160022A (en) | Manufacture of semiconductor device | |
| JP4343379B2 (en) | Substrate processing method, substrate processing apparatus, and device manufacturing method | |
| US5372677A (en) | Method of manufacturing semiconductor devices | |
| JPH04133325A (en) | Pattern formation method | |
| KR960011812B1 (en) | Method for forming a three-layer resist pattern in semiconductor device | |
| KR100299515B1 (en) | Method of manufacturing semiconductor device | |
| KR100196226B1 (en) | Method for forming a contact hole of a semiconductor device | |
| Lai et al. | Resist hardening using a conformable mold | |
| KR100557980B1 (en) | Photoresist lessen method | |
| US6861206B2 (en) | Method for producing a structured layer on a semiconductor substrate | |
| KR940005450B1 (en) | Manufacturing method of thin film transistor | |
| KR100367492B1 (en) | Method for manufacturing conductive line in semiconductor device | |
| WO2001009683A1 (en) | Reduction of resist poisoning |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |