KR0153599B1 - Initial circuit of the system - Google Patents

Abstract

1. Technical field described in the claims

It relates to the system initialization circuit, and especially to the system initialization circuit due to the setting register value in case of unexpected voltage inflow.

2. Technical problem to be solved in invention

A circuit that can change the register value after testing the product by simplifying the circuit by reducing the compared voltage flowing into the system in half and using the register to set the stable area of the voltage to operate the system stably. Provided.

3. Summary of Solution to Invention

Comprising a resistor 101, a voltage divider 103, first and second comparators 106 and 166 for voltage sensing, and the like, the register 101 sets a stable area of voltage, and the voltage divider 103 registers 101. According to the value set in), make the reference voltage to be compared in the first and second comparators 105 and 166, and reduce the voltage entering the reference voltage and the system in half so that the voltage higher than the average voltage flowing into the system is also detected. can do. In other words, assuming that the system operates at 5V, an unexpected high voltage of 8V (voltage causing the system to malfunction) may be detected to initialize the system.

4. Uses of the Invention

Initialization circuit

Description

Initialization circuit of the system

1 is a block diagram according to the present invention.

2 is a concrete circuit diagram of the voltage divider 103 of FIG.

3 is an exemplary output waveform according to the present invention.

The present invention relates to a system initialization circuit, and more particularly, to an initialization circuit of a system for initializing the system by a set register value upon unexpected voltage inflow.

In general, a stable voltage is required for the system to operate reliably. However, when an unexpected voltage is introduced due to an unexpected state, a malfunction occurs, and a countermeasure is required. The microcomputer mainly used in the system operates according to a sequence of pre-programmed series. However, in some parts of the program execution, the result of the front end can affect the rear end. At this time, if the malfunction occurs due to the inflow of unexpected voltage, the original function of the microcomputer is lost. Also, what is needed is to make the program run again from the beginning. The initializing method is artificially performed as disclosed in US Pat. No. 5,340,085, issued August 30, 1994, and automatically initialized as disclosed in US Pat. No. 4,586,179, issued May 29, 1986. There is something to do. The latter method detects when the system is unstable due to voltage instability and initializes it at that moment. The conventional method is to initialize only when the voltage falls below a certain level. This is a fixed method, and the voltage operating range of each product is different. there was. In addition, since the operating range of the voltage is fixed only at the lower limit level, an initialization circuit for the upper limit level is required. The next upper level of voltage sensing requires a voltage that is twice as high as the system operating voltage.

Therefore, an object of the present invention is to simplify the circuit by reducing the compared voltage flowing into the system in half, and by using the resistor to set the stable region of the voltage to operate the system stably, after testing the product register value It is to provide a circuit that can be changed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram according to the present invention,

A register 101 which is initialized by a signal of a reset terminal RESET and stores a value for setting a range of a stable region of a voltage;

The reference voltage generator 105 which generates a reference voltage as a reference and the reference voltage generated by the reference voltage generator 105 are divided according to the set value generated by the register 101 to upper and lower reference voltages. A voltage divider 103 for generating (VHref, VLref),

An upper and lower limit determination unit 109 which provides a determination signal for limiting a range of upper and lower limit levels with respect to values of the upper and lower reference voltages VHref and VLref generated in the voltage divider 103;

Upper and lower reference voltages for detecting whether or not the upper and lower ranges are out of the upper and lower reference voltages VHref and VLref of the voltage divider 103 from the outputs of the upper and lower limit determination units 109. The range detectors 106 and 166,

An inverter 113 for inverting and detecting a detection value of a lower range of the lower reference voltage range detection unit 166;

Initialization signal output unit for generating an initialization signal of the reset stage (RESET) by adding the detection value of the upper range of the upper limit reference voltage range detection unit 106 and the output of the inverter 113 and the power-on reset stage 110 Consists of 108.

2 is a concrete circuit diagram of the voltage divider 103 of FIG.

A falling edge detection unit 200 for detecting a falling edge of the output signal LDB 7 of the register 101;

A rising edge detector 202 for detecting a rising edge of the output signal LDB 3 of the register 101;

An OR gate OR1 that sums the output of the falling edge detector 200 and the reset signal of the reset signal terminal RESET;

An OR gate OR2 for synthesizing the output of the rising edge detector 202 and the reset signal of the reset signal terminal RESET;

A first encoder (EDC1) for encoding the output upper bits [LDB (6: 4)] of the register 101,

A second encoder (EDC2) encoding the output low bits [LDB (2: 0)] of the register 101,

A first synthesizer 201 for synthesizing the output of the oragate OR1 and the output of the first encoder EDC1;

A second synthesizer 202 for synthesizing the output of the oragate OR2 and the output of the second encoder EDC2;

A latch unit 203 for latching outputs of the first and second synthesis units 201 and 202,

Resistor R1-R9 for dividing the output of the reference voltage generator 105,

Third synthesis unit 203-214 which generates upper and lower reference voltages VHref and VLref by combining the partial voltage generated by the resistors R1 to R9 and the outputs of the first and second synthesis units 201 and 202. It consists of.

3 is an exemplary output waveform diagram according to the present invention.

(3a) is an example of the input voltage, and (3b) is an example of the detection output in accordance with the upper and lower reference voltages from the input voltage of (3a).

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS.

A value for setting the voltage stable region range is stored in the register 101. The output value of the register 101 is input to the voltage divider 103, and the voltage divider 103 is configured as shown in FIG. 2 and the LDB 7 of the output LDBs 7: 4 of the register 101 is formed. The polling edge detection unit 200 detects the polling edge and synthesizes the output of the reset signal terminal RESET and the OR gate OR1 to the LDB in the first encoder EDC1 in the first synthesis unit 221. (6: 4) is synthesized by the output encoded with the first synthesis unit 231. In the output LDB (3: 0) of the register 101, the rising edge detection unit 202 detects the rising edge by the LDB 3 to synthesize the output of the reset signal terminal RESET and the OR gate OR2. The second synthesizer 232 synthesizes the LDB (3: 0) with the output encoded by the second encoder EDC2. That is, the outputs of the first and second encoders EDC1 and EDC2 are synthesized by the outputs of the OR gates OR1 and OR2 and the first and second synthesis units 231 and 232, and the upper and lower bytes (DHL7-DH0 and DL7-DL0). It is latched by the latch unit 223, the voltage generated by the reference voltage generator 105 and divided by the resistors R1-R9 and synthesized in the third synthesis unit (203-214), The lower limit reference voltages VHref and VLref are generated. The output of the voltage divider 103 is input as a comparison reference value of the upper and lower limit reference voltage range detectors 106 and 166 and flows in as shown in FIG. 3a generated by the upper and lower limit determiner 109 to compare voltages. It is detected whether the reference voltage range is out of range as shown in FIG. According to a result of the logical sum of the outputs of the upper and lower reference voltage range detectors 106 and 166 and the output of the power-on reset signal terminal 110, an initialization signal is generated through the ora gate 108. .

That is, in the present invention, as shown in FIG. 1, the register 101, the voltage divider 103, and the upper and lower reference voltage range detection units 106 and 166 for detecting the reference voltage are used. In setting, the voltage divider 103 generates the reference voltages to be compared by the upper and lower reference voltage range detectors 106 and 166 according to the value set in the register 101. The voltages generated by the reference voltage generator 105 are divided into two in half each of the resistors R9-R6 and R5-R2 of the resistors R1-R9, respectively, and are divided in two by the resistors R9-R6. Each of the over-resistance R5-R2 is divided and synthesized by the outputs of the first and second synthesis sections 231 and 232 and the third synthesis sections 203-214 in the previous stages to form upper and lower reference voltages VHref and VLref. Is generated. Therefore, since the voltage is reduced in half with respect to the entire reference voltage generated by the reference voltage generator 195, the voltage higher than the average voltage flowing into the system can be detected. In other words, assuming that the system is operating at 5V, even if an unexpected high voltage of 8V (voltage causing the system to malfunction) is detected, the system can be detected and initialized. The second voltage divider 103 generates a reference voltage. The initial voltage of the resistor 101 is set to create a reference voltage that cannot be initialized at first, and then a value is input to the register 101 by a program. At the time of setting, the reference voltage can be made comparable, and the reference voltage can be kept constant regardless of the voltage flowing into the system until the value of the resistor 101 is changed. After the upper and lower reference voltages VHref and VLref are set, when the voltage VDD flowing into the system is out of the reference voltage double range (2VLref-2VHref), the first and second comparators 106 and 166 detect this and initialize the initialization. Initialize the whole system by generating reset signal (RESET).

As described above, the voltage compared to the voltage flowing into the system can be reduced by half to simplify the circuit, and the resistor can be used to set a stable area of voltage at which the system can operate stably. The register value can be changed, and if any value is written to the register, the value is in a stable operating range, and there is an advantage of initializing the system when a voltage outside the upper and lower levels is introduced.

Claims (2)

An initialization circuit for initializing a system, comprising: a register (101) which is initialized by a reset signal of a reset stage (RESET) of the system and stores a value for setting a range of a stable region of voltage, and a reference; The reference voltage generator 105 which generates a reference voltage and the reference voltage generated by the reference voltage generator 105 are divided according to the set value generated by the resistor 101, and the upper and lower reference voltages VHref, A voltage divider 103 for generating a VLref) and a decision signal for defining a range of upper and lower limit levels with respect to values of the upper and lower reference voltages VHref and VLref generated in the voltage divider 103. Compared with the upper and lower limit reference voltages VHref and VLref of the voltage divider 103 from the outputs of the upper and lower limit determination units 109 and the upper and lower limit determination units 109, Upper and lower limit reference war to detect whether Inverter 113 for inverting the detection range of the lower range of the voltage range detection unit 106 and 166, the lower reference voltage range detection unit 166, and the detection value and the inverter that are upper ranges of the upper limit reference voltage range detection unit 106. And an initialization signal output unit (108) for generating an initialization signal of the reset stage (RESET) by adding the outputs of the 113 and the power-on reset stage (110). The voltage divider (103) according to claim 1, wherein the voltage divider (103) detects a falling edge of the output signal (LDB 7) of the register (101), and an output signal of the register (101). LDB (3)], the rising edge detector 202 for detecting the rising edge of the LDB (3), the orifice OR1 for adding the output of the falling edge detector 200 and the reset signal of the reset signal stage (RESET), and the Encoding the output high bits [LDB (6: 4)] of the register 101 and the OR gate OR2 for combining the output of the rising edge detector 202 and the reset signal of the reset signal terminal RESET. A first encoder (EDC1), a second encoder (EDC2) encoding the output low bits [LDB (2: 0)] of the register 101, an output of the oragate OR1 and a first encoder ( A first synthesis unit 201 for synthesizing the output of the EDC1, a second synthesis unit 202 for synthesizing the output of the oragate OR2 and the output of the second encoder EDC2, and the first and second units. Synthesis section 201,202 A latch unit 203 for latching an output, resistors R1-R9 for dividing the output of the reference voltage generator 105, divided voltages generated by the resistors R1-R9, and the first and second parts. And a third synthesizer (203-214) which generates the upper and lower reference voltages (VHref, VLref) by combining with the outputs of the combiner (201, 202).