KR0152803B1 - Multi(pip)-television receiver - Google Patents

Abstract

The present invention relates to an input video signal processing technology of a television receiver. In the conventional VRC, two video signals are synthesized for two screens and exported to a video output. As a result, there was a defect that an additional cost was added, and thus the price was placed in an unfavorable position in terms of price competition. To solve this problem, the present invention was provided with a video signal inputted through a plurality of paths from a television receiver. Select and select to display left and right on one screen for display and supply it to VRL, select and display all 2 screen video signals reproduced and output from VRL or combine them with video signals for other screens To display.

Description

Multi-Video Video Signal Processing Circuit of TV Receiver

1 is an input video signal processing block diagram of a general VR.

2 is an exemplary block diagram of a multi-screen video signal processing circuit of the television receiver of the present invention.

3 is an exemplary block diagram of a sample rate converter in FIG.

FIG. 4 is a block diagram of an exemplary main / sub picture processor of FIG. 2;

FIG. 5 is a horizontal extension block diagram added to the vertical interpolation and convex portion of FIG. 4 to extend two screens into one screen. FIG.

6 (a) to 6 (c) are diagrams illustrating screen configurations according to the present invention.

* Explanation of symbols for main parts of the drawings

201: Tuner 1 and intermediate frequency 202: Tuner 2 and intermediate frequency 202

203: first image selector 204: second image selector

205,206,209 A / D converter 207,208 Sample rate converter

210,211: NTSC decoder 212: main screen processing unit

213: sub-screen processing unit 214: D / A converter

215: RGB matrix 216: NTSC encoder

217: first voice selector 218: second voice selector

219,220: Voice Demodulator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input video signal processing technology of a television receiver, and in particular, synthesizes a two-screen video signal input through various paths and outputs the video signal for the two-screen video signal inputted from the V-Cal. A multi-screen video signal processing circuit of a television receiver adapted to be selectively displayed in combination with a video signal.

FIG. 1 is a block diagram of an input video signal processing of a general VR. The operation thereof is as follows.

The signal VHF / UHF _in received through the antenna is supplied directly to one side input of the high frequency output unit 113 through the antenna divider 101, and on the other hand, the tuner / intermediate frequency break 102, 103. Are recorded on the recording media of the VHS recorder 104 and 8MM recorder 105, respectively.

Meanwhile, video and audio signals input from the outside through the video input terminal V _in and the audio input terminal A _{in are} supplied to the VHS recorder 104 and the 8MM recorder 105, respectively, to the VHS or 8MM tape. Each may be recorded.

Therefore, there are five signals that can occur in V-Cal, and they are ① first tuner input signal ② second tuner signal ③ VHS tape play signal ④ 8MM tape ashing signal ⑤ external audio / video input signal (A _in ) / ( V _in ).

These signals are randomly selected by two analog multiplexers, i.e., the video multiplexer 108 and the voice multiplexer 109, respectively, which in turn is a two-screen generator 110 (ARC / DW: Aspect Ratio Converter). Double Window) is used to convert the aspect ratio and process it as a two-screen signal.

In this case, when the video signal reproduced and output from the VHS tape is a super-VHS type video signal, the two-screen generator 110 through the super-VHS selector 106 and again through a separate A / D converter 107. Supplied to.

In this case, only one image signal is selected by the image multiplexer 108 by the selection signal SEL output from the super-VHS selector 106, which is generated by the two-screen generator 110. It is used as a video signal for two screens together with the video signal of the scheme.

In addition, in response to the two-screen video signal being selected by the video multiplexer 108, the audio multiplexer 109 selects two different audio signals for five inputs, and one of them is connected to the body of the V-Cal. It is output to the separately installed phone jack (PJ) and the other is output to the audio output terminal (A _out ) side.

The two-screen generator 110 synthesizes two video signals selectively input through the above process into one video signal so as to be suitable for constituting two screens, and outputs the video signals for two-screen NTSC encoder ( 111 is encoded by NTSC and then directly output to the video output terminal (V _out ) side, and is output to the high frequency output terminal (RF _out ) side through the high frequency converter 112 and the high frequency output unit 113 on the other hand. .

However, in the conventional VRC, since two video signals are synthesized for two screens and outputted, the video output is output. There was a bug set in a disadvantage.

Accordingly, an object of the present invention is to synthesize a video signal of a plurality of input video signals in a television receiver for two screens, to process the video signal for recording on the VCD, and to reproduce the video signal for the two screens. The present invention provides a multi-screen video signal processing circuit for selectively displaying or simultaneously displaying one of the two-screen video signals.

2 is a block diagram of an exemplary embodiment of a multi-screen video signal processing circuit of a television receiver according to the present invention for achieving the above object. As shown therein, a high frequency broadcast signal input through an antenna ANT is supplied. First and second tuners and intermediate frequency stages 201 and 202 which respectively select broadcast signals of predetermined channels and detect video and audio signals of intermediate frequencies, and the first and second tuners and intermediate frequency stages ( First and second video selectors 203 and 204 for selecting an arbitrary video signal for constituting two screens from the video signals output from 201 and 202 and a plurality of video signals input from the outside; A / D converters 205 and 206 for converting analog video signals output from the first and second video selectors 203 and 204 into digital signals, and the A / D converters 205, NTSC decoder 21 for demodulating the luminance signal Y and the color signal C in the output video signal of 206; 0), 211, and a sub picture processor 213 for converting the scanning player so as to receive a video signal (Y), (C) output from the NTSC decoder 211 and to configure a sub picture; Receives the video signals (Y) and (C) output from the NTSC decoder 210, converts the scan player to be suitable for composing the main screen, and then synthesizes them with the output video signals of the sub-screen processing unit 213 to output them. A main screen processor 212, a D / A converter 214 for converting an analog main / sub picture video signal output from the main screen processor 212 into a digital signal, and the D / A converter 214 RGB matrix 215 for generating red, green, and blue signals (R), (G), and (B) and outputting them to the CPT side by receiving the video signal output from the D / A converter. NTSC, which receives the video signal output from (214) and encodes it into a signal of a type suitable for recording on a tape of V-Cal. Corresponding to the video signal selected to form two screens among the audio signals output from the coder 216, the first and second tuners, the intermediate frequency stages 201, and 202 and a plurality of audio signals input from the outside. First and second audio selectors 217 and 218 and voice demodulators 219 and 220 for selecting two audio signals and demodulating the audio signals. When described in detail with reference to the accompanying 3 to 6 as follows.

The high frequency broadcast signal input through the antenna ANT is supplied to the first tuner and the intermediate frequency band 201 and the second tuner and the intermediate frequency band 202, respectively, so that the intermediate frequency video signal and the audio signal of the selected channel are respectively supplied. Is output.

The first image selector 203 includes the image signals output from the first and second tuners, the intermediate frequencies 201 and 202, and the image signals V ₁ , V ₂ , and super- The luminance signal Y of the VHS signal S-VHS is supplied to each other, and one video signal selected by the image selection signal SEL input from the outside among the plurality of video signals supplied is an A / D converter ( 205 is converted into a digital signal and then supplied to one input of the NTSC decoder 210 through a sample rate converter 207.

Since the number of samples per horizontal line (1H) is changed to about 910 ± several samples, the sample rate converter 207 is used to keep the number constant at 910. In other words, the sample rate converter 207 is not required for a standard signal such as a good recording medium or broadcast signal.

Similar to the first image selector 203, the second image selector 204 also outputs an image signal output from the first and second tuners and intermediate frequencies 201 and 202 and an image signal input from the outside. V ₁ ), (V ₂ ) and the luminance signal (Y) of the super-VHS signal (S-VHS) are respectively supplied, and by the image selection signal (SEL) input from the outside among the plurality of image signals supplied in this way. The selected video signal is converted into a digital signal through the A / D converter 206 and then supplied to one input of the NTSC decoder 211 through the sample rate converter 208.

In addition, the color signal C of the super-VHS signal S-VHS supplied from the outside is converted into a digital signal through a separate A / D converter 209, and then the NTSC decoders 210 and 211 Each is supplied to the other input.

The NTSC decoders 210 and 211 separate the luminance signal and the color signal from the output image signals of the sample rate converters 207 and 208, and demodulate the color signal and output the respective luminance signals (the output signal therefrom). Y) and the color signal C are supplied to the main screen processing unit 212 and the sub-screen processing unit 213, respectively.

However, when the luminance signal Y of the super-VHS signal S-VHS is selected by the first image selector 203 or the second image selector 204, the NTSC decoders 210 and 211 After recognizing the fact based on the image selection signal SEL, the luminance signal of the super-VHS signal S-VHS is supplied through the path, and is supplied through the A / D converter 209. The color signal of the super-VHS signal S-VHS is demodulated and the color signal C is output together with the luminance signal Y of the NTSC system in the same manner as above.

The sub-screen processing unit 213 converts the scanning player so as to be suitable for configuring the sub-screen, and the sub-screen video signal processed here is supplied to the main screen processing unit 212 for multiplexing with the main screen video signal. In this case, the main and sub picture video signals Y and C are output to the left, right or up and down sides according to the combination form with the main picture video signal.

The video signal for the main / sub picture output from the main screen processing unit 212 is converted into an analog signal through the D / A converter 214 and then the red, green, and blue color signals R through the RGB matrix 215. Since (G) and (B) are detected and supplied to CPT, a main screen is normally displayed on the left screen of the CPT and a subscreen is displayed on the right.

In addition, the composite video signal of the main / sub picture output from the D / A converter 214 is encoded into a signal of a type suitable for recording on a tape of V-Cal via an NTSC encoder 216 and then supplied to the V-Cal. Is recorded.

Meanwhile, the processing of the audio signal is similar to the processing of the video signal in the first audio selector 217 and the second audio selector 218 in the first and second tuners and the intermediate frequencies 201 and 202. The audio signal to be output and the audio signal A ₁ , (A ₂ ) and the super-VHS signal S-VHS that are input from the outside are supplied, and the selected voice signal is the voice demodulator 219. , 220 are demodulated through each of them, and are directly supplied to the left and right speakers SP _L and SP _R and supplied to the VRC side through the audio output terminals L _out and R _out . .

FIG. 3 is a detailed block diagram showing an embodiment of the sample rate converter 207 in FIG. 2 and describes its operation as follows.

The input composite video signal CV _in is converted into a digital signal through the A / D converter 301 and then output as a composite video signal CV _out having the sample rate converted through the line memory 302.

To this end, if the fall of the composite video signal (CV _out) via a sync separator (306) after detecting the composite synchronizing signal (C _sync) with a falling edge detector 307, the composite synchronizing signal (C _sync) In order to detect and supply the write reset signal WRST to the line memory 302 in synchronization with one horizontal period 1H, the output signal of the falling edge detector 307 is not used, but about 910 ± 10 degrees. Only edge detection signals included within the interval should be used.

To this end, the falling edge detection signal output from the falling edge detector 307 is supplied to one side input of the AND gate AD3, and the output signal Q of the JK flip-flop FF1 is connected to the AND gate AD3. By supplying to the other input terminal, the falling edge detection signal output from the falling edge detector 307 is supplied only when the high signal is supplied from the JK flip-flop FF1 to the other input terminal of the AND gate AD3. It is supplied to the write reset signal WRST of the line memory 302 through the gate AD3.

In the vertical driving period, the line memory 302 uses the write reset signal WRST obtained by itself as in the above description, but the read reset signal always reads only 910 samples in other video signal sections. (RRST) should be supplied, for which a 910 module counter 310 was used.

Normally, the color carrier (4fsc) is selected through the switch 303 and supplied as the read clock signal RCLK of the line memory 302 and also supplied as the clock signal CLK of the 910 module counter 310. When the number of clocks of the signal 910f _H output from the color carrier 4fsc and the clock generator 304 differs by more than 910 per field, the clock generator 304 outputs the signal through the switch 303. The signal 910f _H is selected to be supplied to the read clock signal RCLK of the line memory 302 and the clock signal CLK of the 910 module counter 310, because the color part carrier 4fsc provides the 910 module. This is because the number of lines per field changes when the counter 310 is counted, causing the screen to shake up and down.

FIG. 4 is a detailed block diagram showing an embodiment of the main screen processing unit 212 or the sub-screen processing unit 213 in FIG. 2.

When the luminance signal Y and the color signal C separated by the NTSC decoder 210 are inputted to the main screen processing unit 212, they are processed in a form suitable for displaying the main screen through similar paths. Since the color signal C is a signal in which the color signals U and V are multiplexed, the color signal U and the color signal V are separated through the demultiplexer 408 to process them separately.

The field memories 401 and 407 serve as data buffers to solve the time difference between write and read during data interpolation and decimation.

The image signals through the field memories 401 and 407 are horizontally interpolated or interpolated between the samples by the sample memories 402 and 409 and 410 and the horizontal interpolation and deduction units 403 and 441 and 442. Data is rounded off at a constant rate.

The video signal in which the number of samples is horizontally changed is used as data for interpolating between lines or lines or extracting interpolated data by the line memories 404 and 414. Since the data amount of (U) and (V) is smaller than the data amount of the luminance signal (Y), it is multiplexed through the multiplexer 413 to share the line memory 414, and the output of the line memory 414 is shared. By separating the original through the demultiplexer 415 it is possible to reduce the number of use of the line memory. Let the data processed in this way be output data of the main screen processing unit 212.

For the main picture video signal with the changed number of horizontal and vertical data, the luminance signal Y, the color signals U, and V are lined up through the multiplexers 406 and 418 and 419 for horizontal multiplexing with the sub picture. Each screen is multiplexed to the left and right screens. Thus, the multiplexer 406 outputs the ARC processed luminance signal Y to suit two screens, and the multiplexer 418 outputs the ARC processed color signal U to suit two screens, and the multiplexer 419. In A3, the ARC-processed color signal V is output to suit two screens.

The ARC output for two screens output through the above process is converted into an analog signal through the D / A converter 214 and then encoded by the NTSC encoder 216 in the form of a composite video signal and recorded in the VRC.

FIG. 5 is a block diagram of an exemplary embodiment of the present invention for selecting one of the left and right screen video signals that have been processed after recording and displaying them on the full screen as shown in FIG. If the screen is to be displayed on one full screen, the horizontal read function is reduced by halving the data read speed of the line memories 404 and 414 in FIG. Interpolation and conduit 405, 416, 417 should be implemented in the interior, the operation thereof will be described as follows.

2 screen video signal (2V) is the sample clock signal by (CLK _s) is written in the line memory 501, by the sample clock signal (CLK _s), the second frequency division clock signal through a second frequency divider (502) The read data is input to the multiplexer 508 while the average of this and neighboring data through the sample memory 505 is also input to the other side of the multiplexer 508.

That is, by using the signal obtained by dividing the sample clock signal CLK _s into two as the selection signal of the multiplexer 508, the output value of the line memory 501 and the average value of the neighboring data are alternately selected, and as a result, Since the number doubles, the screen stretches horizontally twice.

The clock counter 503 disables the write enable signal WE of the line memory 501 in order to prevent the video signal of the screen not viewed from being stored in the line memory 501 when selecting and viewing two screens. .

That is, when viewing the left subscreen, the data of the left screen is written to the front of the line memory 501, and the data of the right screen is not read, but the data is moved to the next line. Therefore, the write enable signal WE remains high. To be. However, when viewing the right screen (sub-screen), the video signal of the left screen should not be stored in the line memory 501, so that the write enable signal WE is kept low 'during the left screen section. At this time, the selection of the left and right screens is determined by the left and right screen selection signals SEL.

For reference, (a) and (b) of FIG. 6 show that one screen of the left or right screen is displayed as it is and the other screen (broadcast signal, etc.) is displayed at another position as an example. At this time, it is possible by multiplexing horizontally using the two-screen generating function in the main / sub picture processing units 212 and 213 without stretching the recorded screen horizontally. The other screens may be halved in the horizontal direction by using the horizontal compression function in the main and sub screen processing units 212 and 213.

As described in detail above, the present invention receives a video signal input through a plurality of paths from a television receiver and selects any two video signals so that they can be displayed by dividing them left and right on one screen. It is possible to supply various video screens to viewers by reducing the cost by supplying it to VRT and selecting and displaying all the 2 screen video signals reproduced and outputted from VRL. It works.

Claims (7)

First and second selecting first and second tuners and video signals output from the intermediate frequency stages 201 and 202 and arbitrary video signals for constituting two screens from a plurality of video signals input from the outside, respectively. Image selectors 203 and 204, and A / D converters 205 and 206 for converting analog video signals output from the first and second image selectors 203 and 204 into digital signals. In the NTSC decoders 210 and 211 which demodulate the luminance signal Y and the color signal C from the output video signals of the A / D converters 205 and 206, the NTSC decoder 211 Sub-screen processing unit 213 for converting the scanning player so as to receive the output video signals (Y) and (C) to configure the sub-screen, and the video signals (Y) and (output) output from the NTSC decoder 210 (( C) is supplied with a main screen processing for converting the scanning player so as to configure the main screen and then synthesizing it with the output video signal of the sub-screen processing unit 213 to output the main screen processing; Output unit 212, a D / A converter 214 for converting an analog main / sub picture video signal output from the main screen processing unit 212 into a digital signal, and an output from the D / A converter 214. And a NTSC encoder (216) for encoding the video signal to be encoded into a signal of a form suitable for recording on a tape of V-Cal. According to claim 1, The first and second tuners and the intermediate frequency stages 201, 202 corresponding to the video signal selected to configure the two screens of the audio signal output from a plurality of externally input signals And a first and second voice selectors 217 and 218 and a voice demodulator 219 and 220 for selecting two audio signals and demodulating them. Multi-screen video signal processing circuit. The sample rate converter 207 at the rear of the A / D converters 205 and 206 to maintain a constant number of samples per horizontal line when the non-standard video signal is to be processed. And 208. The multi-screen video signal processing circuit of a television receiver, characterized by the above-mentioned. The line memory 302 of claim 3, wherein the sample rate converter 207 converts and outputs the sample rate of the composite video signal CV _in converted to the digital signal through the A / D converter 301; A synchronization separator 306 that detects the synthesis synchronization signal C _sync from the composite image signal CV _out , and a falling edge detector 307 that detects the falling edge of the synthesis synchronization signal C _sync , and one horizontal period ( The output of the JK flip-flop FF1 which inputs the outputs of the 900 counter 308 and the 920 counter 309 to supply the write reset signal WRST to the line memory 302 in synchronization with 1H). An AND gate AD3 which performs an AND combination of the outputs of the falling edge detector 307 and supplies it to the write reset signal WRST, and usually selects the color carrier 4fsc, and the color carrier 4Fsc and the clock generator. 304) when the signal (clock number differ by more than 910 per 1 field of 910f _H) outputted from the clock generation day Selecting a signal (910f _H) output from 304 to that constituted by the lead clock signal (RCLK) and 910 module counter switch 303 for supplying a clock signal (CLK) of 310 of the line memory 302 A multi-screen video signal processing circuit of a television receiver. 2. The main picture processing unit 212 according to claim 1, wherein the main picture processing unit 212 includes the field memories 401 and 407, and the field memories 401 and 407 for compensating the processing time difference between the luminance signal Y and the color signal C. Sample memory 402, 409, 410 and horizontal interpolation and converging units 403, 411, 412, in which the output video signals of the samples are horizontally interpolated between the samples and the interpolated data are deduced at a constant rate; Line memory 404, 414 which interpolates between lines or lines or extracts interpolated data for an image signal of which the number of samples is changed vertically by receiving the output image signals of the horizontal interpolation and conjugation units 403 and 411 and 412. And the output video signals of the vertical interpolation and conduction unit 405 and 416 and 417 and the vertical interpolation and conduction unit 405 and 406 and 417, the luminance signal Y and the color signal U. Tele, characterized in that composed of multiplexer (406), (418), (419) for multiplexing the (V) to the left and right screen for each line A video signal processing circuit for a multi-screen of the occlusion set. The apparatus of claim 5, wherein a demultiplexer 408, a multiplexer 413, and a demultiplexer 415 are added to reduce the number of line memories used in the color signal processing path. ), A multi-screen video signal processing circuit of a television receiver, characterized in that the vertical interpolation and the conduction unit 416 are configured in parallel. Claim 5 wherein, the sample clock signal (CLK _s) in synchronization with the two-screen image signal and the line memory 501 to store (2V), the sample clock signal (CLK _s) 2 wherein the line memory (501 divides the A divider 502 for supplying the read clock signal RCLK and the selection signal S of the multiplexer 508, a clock counter 503 for counting the sample clock signal CLK _s , and the clock A multiplexer 504 for selectively receiving the output signal of the counter 503 and a zero input and supplying the output signal to the write enable signal WE of the line memory 501, and image data directly output from the line memory 501. And a multiplexer 508 that selectively accepts an average value of out data through the sample memory 505, and a D-type flip-flop that outputs the output data of the multiplexer 508 in synchronization with the sample clock signal CLK _s . (DF11) included in the interior of the vertical interpolation and the choke unit 416 Characterized by a multi-screen television receiver video signal processing circuit of that.