KR0143569B1 - Apparatus for optimizing noise data without image signal - Google Patents

Abstract

The present invention relates to an apparatus for optimizing noise data without a video signal in a PDP television, comprising: a synchronous separator (10) for separating a synchronous signal; A signal discrimination unit 12 for determining the presence or absence of an image signal; A synchronization generator 14 for generating a synchronization signal; A signal selector 16 for selecting an output of the synchronization generator 14 when only noise exists; A vertical positioning unit 18 for setting a vertical position with a synchronization signal; A clock generator 20 for generating a clock; A three-phase buffer 21 for selecting the generated clock; A first counter 22 and a second counter 24 for generating start and end signals of the horizontal position; An AND gate 26 for ANDing the outputs of the vertical positioning unit 18, the three-phase buffer 21, the first counter 22 and the second counter 24; And an A / D converter 28 for sampling and optimizing a noise signal only within a set area, and providing a path for transmitting data normally even in a channel in which noise is scanned without a synchronization signal, thereby preventing circuit confusion. You can do this and optimize the amount of data when only noise is present.

Description

An apparatus for optimizing noise data without image signals

1 is a state diagram showing the generation of wall charges and the resulting discharge phenomenon when AC power is applied to a cell of the panel.

2 is a graph of the relationship between Vs and Vw and the resulting light output for a cell in an on state.

(b) is a graph of the relationship between Vs and Vw and the resulting light output in a cell in the off state.

Fig. 3A is a waveform diagram of a write pulse Vwr for turning off an off cell.

(b) is a waveform diagram of an erase pulse Ve for turning on an on cell.

4 is a state diagram and waveform diagram showing how addressing is performed in a 4 * 4 array.

5 is a block diagram of an apparatus for optimizing noise data without a video signal according to the present invention.

6 is a waveform diagram of an apparatus for optimizing noise data without an image signal according to the present invention.

＊ Explanation of symbols for main parts of drawing

10: synchronization separator 12: signal discriminating unit

14: synchronization generator 16: signal selector

18: vertical position setting unit 20: clock generator

21: 3 phase buffer 2: 1st counter

24: second counter 26: AND gate

28: A / D converter

The present invention relates to an apparatus for optimizing noise data without a video signal, and more particularly to an apparatus that is designed to process noise data differently from a video signal in the case of a channel where only a noise signal appears in a PDP television.

BACKGROUND A plasma display panel (hereinafter referred to as PDP) is a display device using light emission according to a discharge phenomenon in a mixed gas. The plasma display panel essentially has a performance suitable for a computer terminal, an educational system, and the like, and is partially used as a computer display.

PDPs are suitable for large-area display devices and can be colorized, so access to flat wall-mounted televisions has been made.

CRT, which is still firmly established in the display device field, has some major drawbacks. That is, since the CRT itself has a fresco structure, the size of the CRT itself is large, the operating voltage is high, and a voltage of about 10,000 V is required, and a display distortion occurs.

In order to solve the drawbacks of the CRT, flat display devices having a matrix structure have been studied.

By adopting the matrix structure, the display distortion is solved, the planar structure is adopted to solve the problem of large size, and the problem of high voltage is solved by not using the high voltage driving electron beam.

The flat panel display includes an active luminescence display (EL), a light emitting diode display (LED), a plasma display (PDP) and the like, and a passive element, a liquid crystal display (LCD) and an electrochromic display ( ECD).

Among them, the AC type PDP has been attracting attention as an active memory display panel capable of large display with high resolution.

Looking at the types of PDP can be classified as follows.

First, the PDPs are classified into AC type PDP (indirect discharge type) and DC type PDP (direct discharge type) according to the type of driving voltage applied to the discharge cell.

That is, the AC type PDP is driven by a sine wave AC voltage or a pulse voltage, while the DC type PDP is driven by a DC voltage.

In general, the two PDPs have a different structure. In the AC type PDP, the electrode is covered by the dielectric of the glass, whereas in the DC type PDP, the electrode is exposed as it is and a discharge current flows while the discharge voltage is applied.

The AC type PDP has a memory function inside the cell, but the DC type PDP has a merit such that gray scale is added to facilitate image display.

Secondly, there are two types of memory, in which the panel itself stores display information, and a refresh type that reads the display information memory outside the panel and displays it repeatedly on the panel.

Third, according to the shape of the display, the panel has a lattice-shaped electrode, and the intersection of each electrode constitutes a pixel, and the degree of freedom is relatively high, and the dot matrix type that displays characters and figures is more freedom by the relationship between the points. There is a segment type used for small display.

Fourth, according to the type of the addressing mechanism of the display discharge spot, the self-scan PDP and the self-scanning PDP, which is a functionalized panel display that provides the self-scanning function of the discharge point to the matrix type that independently addresses the cells in any place, There is a shift PDP.

PDP has the following advantages over other display devices.

Since PDP does not discharge below a certain voltage (Firing voltage), such a nonlinearity eliminates the limitation on the number of plasma display lines, which enables large-scale production and multiplexing technology for reducing the number of driving circuits.

The large matrix display has a memory function, which is necessary to eliminate high brightness and flicker, while the CRT has a lifespan of 20,000 hours, while the PDP has a lifespan of 50,000 hours.

PDP is suitable for mass production because there are no easily broken parts except glass, and its simple structure makes it possible to manufacture large panels and has a resolution of 100 Line / inch or more because of its strong nonlinearity.

Since the discharging material is a gas, the refractive index value is 1, which means that the light is not extinguished by the internal reflection and the external light is not reflected or scattered by the display material.

In addition, unlike other flat panels, the PDP is sealed with glass above 400 ° C, which means that the plasma display can operate even under high humidity conditions or the presence of reactive gases. The change is only caused by the circuit.

Referring to FIG. 1, the driving principle of the PDP, such as the generation of wall charges and the resulting discharge phenomenon when AC power is applied to a cell of the panel, will be described with reference to the AC PDP.

When a discharge starting voltage (Vf: firing voltage) is applied at t0, the gas is ionized, electrons and ions are attracted to the anode and cathode, respectively, and the attracted ions and electrons generate wall charge as shown in FIG.

The voltage at t1 is smaller than the discharge start voltage (Vf) and a voltage having a changed polarity is applied. At this time, the reduced applied voltage is called a sustain voltage (Vs), and the sustain voltage (Vs) is neon-argon-based, neon It is about 85 to 90V in AC type PDP of magnesium oxide protective film using xenon-based gas.

Sine waves, stepped waves, and giant waves have been used as the sustain voltage waveforms of AC-type PDPs. Currently, giant waves with small internal resistance and rapid rise are known to increase wall voltage. It is written.

When it goes from t0 to t1, the polarity of the sustain voltage (Vs) is changed and is combined with the wall voltage (Vw) generated by the start of discharge. Thus, the sum of the two voltages (Vs + Vw) is greater than the discharge start voltage (Vf). The secondary discharge occurs due to the increase, and the secondary discharge generates a light pulse and the wall charge is reversed.

At t2, the polarity is changed again to start the third discharge, and the third voltage discharge causes the wall voltage Vw to be reversed. At this time, the sustain voltage Vs is not discharged without the help of the wall voltage Vw.

(A) of FIG. 2 shows the relationship between the sustain voltage (Vs) and the wall voltage (Vw) when the cell is in the on state, and thus the light output (LP). (B) is when the cell is in the off state. The relationship between the sustain voltage Vs and the wall voltage Vw and the light output LP accordingly are shown.

FIG. 3 is a waveform diagram used to turn on an off cell and (b) is a waveform diagram used to turn off an on cell.

As shown in (a) of FIG. 3, a partial discharge is generated by applying a write pulse (Vwr: Write Pulse) among the address pulses between the sustain voltages (Vs), so that the wall voltage (Vw) in the off state is turned on. Similarly, as shown in (b), the erase pulse (Ve: Errase Pulse) among the address pulses enters, and the wall voltage Vw in the on state drops to 0 V level and is in the off state.

4 is a waveform diagram showing how addressing is applied to electrodes in a 4 * 4 array. Address pulses (write pulses, erase pulses) for displaying information required for a panel while a sustain voltage (Vs) is applied to all cells. Should be added.

That is, the sustain voltage is applied to all the electrodes or the address pulse is applied only to the B and D electrodes. This waveform turns the cell 6 on or off.

Among the various waveforms, the waveform corresponding to cell 6 is waveform B-D, and the waveforms applied to the other 15 cells are A-D and A-C.

In the PDP television driven as described above, the image information data is displayed on the display device in the channel where the video signal appears, but only the noise is displayed on the display device in the case of the channel where the video signal does not appear. .

As such, in the case of a channel in which no image signal is displayed and only noise, there is no horizontal sync signal Hsync and a vertical sync signal Vsync serving as reference signals.

Therefore, when there is no video signal, since there is no signal for synchronizing a clock that is synchronized with the synchronization signal when there is a video signal, the clock is free running.

If the above clock is used as the reference clock for data generation, noise cannot be accurately scanned. Therefore, if there is no image information data and only noise exists, the data generation method and the generation path are different from those of the image information data. There is a need for distinction.

Accordingly, the present invention has been made to satisfy the above necessity, and is an apparatus for optimizing noise data without image signal, which is designed to be processed differently than when image information data exists when there is no image information data and only noise exists. The purpose is to provide.

The apparatus of the present invention for achieving the above object,

A sync separator for separating the horizontal sync signal and the vertical sync signal from the input signal;

A signal discrimination unit outputting a low signal when there is an image signal according to a result of the synchronization separator, and a high signal when only noise exists;

A synchronization generator adapted to generate a synchronization signal;

A signal selector which selects an output of the sync generator from the sync separator and the sync generator when the discrimination result of the signal discriminator is high;

A vertical position setting unit adapted to set a vertical position with a synchronization signal of the synchronization generating unit selected by the signal selecting unit;

A clock generator configured to always generate a clock regardless of the presence or absence of an image signal;

A three-phase buffer configured to select a clock generated by the clock generator only when a high signal is output from the signal discriminator;

A first counter adapted to generate a signal that the horizontal position has started;

A second counter adapted to generate a signal that the horizontal position has ended;

An AND gate for performing an AND operation on the outputs of the vertical positioning unit, the three-phase buffer, the first counter, and the second counter; And

A / D conversion unit for sampling and optimizing the noise signal only within the set area of the horizontal position and vertical position.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

5 is a block diagram of an apparatus for optimizing noise data without a video signal according to the present invention, comprising: a sync separator 10 for separating a horizontal sync signal and a vertical sync signal from an input signal; A signal discriminating unit 12 outputting a low signal when there is an image signal according to a result of the synchronization separating unit 10 and a high output signal when only noise exists; A synchronization generator 14 adapted to generate a synchronization signal; A signal selection unit (16) for selecting an output of the synchronization generation unit (14) among the synchronization separation unit (10) and the synchronization generation unit (14) when the determination result of the signal determination unit (12) is high; A vertical position setting unit (18) adapted to set a vertical position with a synchronization signal of the synchronization generating unit (14) selected by the signal selecting unit (16); A clock generator 20 configured to always generate a clock regardless of the presence or absence of an image signal; A three-phase buffer 21 for selecting a clock generated by the clock generator 20 only when a high signal is output from the signal discriminator 12; A first counter 22 adapted to generate a signal that the horizontal position has started; A second counter 24 adapted to generate a signal that the horizontal position is finished; An AND gate 26 for ANDing the outputs of the vertical positioning unit 18, the three-phase buffer 21, the first counter 22 and the second counter 24; And an A / D converter 28 for sampling and optimizing the noise signal only within a set area of the horizontal position and the vertical position.

Next, the operation and effects of the present invention configured as described above will be described in detail.

When the input signal is a composite video signal, since the synchronization signal is included, the synchronization separator 10 separates the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync, but the input signal has no image signal and noise. If only present, there is not even a synchronization signal to be separated.

The signal discrimination unit 12 outputs a low signal when there is an image signal according to the result of the synchronization separator 10, and a high signal when only noise exists.

Since the image signal is for optimizing the noise signal data, the apparatus of the present invention will focus on when the output of the signal discriminating unit 12 is high.

When the determination result of the signal discriminating unit is high, that is, when only the noise without the image signal exists, the signal selecting unit 16 synchronizes the synchronization generating unit 14 between the synchronization separating unit 10 and the synchronization generating unit 14. Select the output of.

At this time, the vertical position setting unit 18 sets the vertical position with the synchronization signal of the selected synchronization generating unit 14.

In addition, when the determination result of the signal discrimination unit 12 is high, that is, when there is no image signal and only noise exists, the three-phase buffer 21 selects the clock generated by the clock generation unit 20.

The first counter 22 generates a signal indicating that the horizontal position has started, and the second counter 24 generates a signal indicating that the horizontal position has ended.

After performing an AND operation on the outputs of the vertical positioning unit 18, the three-phase buffer 21, the first counter 22, and the second counter 24 at the AND gate 26, an A / D conversion unit ( In 28), the noise signal is sampled only within the set area of the horizontal position and the vertical position to output the optimized noise signal.

FIG. 6 is a waveform diagram according to the present invention, which will be described by considering only odd fields.

As in the waveform shown in (a), the vertical position setting unit outputs a waveform that enables sampling only where desired. That is, since only 23 to 262 lines are output as high, as a result, only 23 to 262 lines are sampled.

(B) is a waveform diagram in which one period of the various periods of the horizontal synchronization signal is enlarged, a is a blanking period, b is a burst period, c is a period in which image information data exists, and d is a later level.

(C) is a clock generated by the clock generator, the actual frequency is higher but shown for simplicity for convenience of explanation.

(D) is an output waveform of the first counter, and the clock is counted after the horizontal synchronizing signal becomes high, and outputs high after n.

(E) is an output waveform of the second counter, and the clock is counted after the horizontal synchronizing signal becomes high, and is kept high only for n + m clocks.

If the AND is performed on the AND gate with four inputs (A), (B), (D), and (E), the m clock intervals are the intervals in which the image information data exists as in the waveform of (F). Only the clock is outputted and sampling is done in this interval.

As described above, the present invention provides a path for transmitting data normally even in a channel scanning only noise without a synchronization signal, thereby preventing circuit confusion and optimizing the amount of data when only noise exists. It works.

Claims (1)

A sync separator 10 for separating the horizontal sync signal and the vertical sync signal from the input signal; A signal discriminating unit 12 outputting a low signal when there is an image signal according to a result of the synchronization separating unit 10 and a high output signal when only noise exists; A synchronization generator 14 adapted to generate a synchronization signal; A signal selection unit (16) for selecting an output of the synchronization generation unit (14) among the synchronization separation unit (10) and the synchronization generation unit (14) when the determination result of the signal determination unit (12) is high; A vertical position setting unit (18) adapted to set a vertical position with a synchronization signal of the synchronization generating unit (14) selected by the signal selecting unit (16); A clock generator 20 configured to always generate a clock regardless of the presence or absence of an image signal; A three-phase buffer 21 for selecting a clock generated by the clock generator 20 only when a high signal is output from the signal discriminator 12; A first counter 22 adapted to generate a signal that the horizontal position has started; A second counter 24 adapted to generate a signal that the horizontal position is finished; An AND gate 26 for ANDing the outputs of the vertical positioning unit 18, the three-phase buffer 21, the first counter 22 and the second counter 24; And an A / D converter (28) for sampling and optimizing a noise signal only within a set area of a horizontal position and a vertical position.