KR0140345B1 - Automatic convergence regulating circuits of projection t.v - Google Patents

Abstract

A convergence adjustment circuit for automatically adjusting convergence in a projection television.

After the projection television detects the horizontal and vertical size of the video signal, it outputs the address corresponding to the position value of the video signal corresponding to the detected size and compares it with the address corresponding to the position value of the set video signal. The convergence data is automatically corrected by moving the version data.

Description

Projection Television's Automatic Convergence Control Circuit

1 is a block diagram of a convergence correction circuit according to the present invention.

2 is an image point state diagram for sector segmentation in the sector segmentation counter 30 in FIG.

* Explanation of symbols for main parts of the drawings

11: Synchronous separation part 12: Synchronous wave shaping part

13: reference horizontal pulse generator 14: horizontal counter

15: reference vertical pulse generator 16: vertical counter

17: Vertical clock generator 18, 35: MUX

19: luminance separation unit 20: D / A converter

21: mixer 22: video pulse counter

23: Image center point detection section 24: Pulse selector

25, 27, 29, 31: 1st-4th data comparator 26: screen start counter

28: variable counter 30: sector division counter

3: Sector Decoder 33: And Gate

34: address latch 36: CPU

37: Memory 38: Lookup Table

39: data buffer

This description relates to a convergence adjustment circuit for automatically adjusting the convergence in a projection television.

In general, a three-color CRT requires a convergence that focuses three beams. There are two types of convergence convergence: static convergence and dynamic convergence.

In the conventional convergence adjustment, the user recognizes the image signal on the screen with his eyes and judges whether or not it is matched with the manual adjustment. Such a conventional convergence adjustment method has a limitation of adjustment as the screen of the projection television is gradually enlarged, and the user feels eye fatigue by adjusting at a close distance to the screen, thereby lowering the adjustment efficiency.

It is therefore an object of the present invention to provide a convergence adjustment circuit for automatically adjusting convergence in a projection television.

Another object of the present invention is to provide a convergence adjustment circuit that can increase the convergence adjustment efficiency in a projection television.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a convergence correction circuit according to the present invention.

Sync Separation Unit 11, Sync Waveform Shaper 12, Reference Horizontal Pulse Generator 13, Horizontal Counter 14, Reference Vertical Pulse Generator 15, Vertical Counter 16, Vertical Clock Generator ( 17), MUX (18), an image size detector (100) for generating an address value for the horizontal and vertical size of the video signal by inputting a composite video signal, luminance separation unit (19), D / A converter 20, the mixer 21, the image pulse counter 22, the image center point detector 23, the image pulse selector 24, the first data comparator 25, the screen start counter 26, the second data comparator ( 27), a variable counter 28, a third data comparator 29, a sector partition counter 30, a fourth data comparator 31, a sector decoder 32, and an gate 32, the composite image A position detector 200 which detects only a pure luminance signal from the signal and detects a position of an image signal by a horizontal and horizontal section counting value and a horizontal and vertical clock signal; And the address latch 34 and the MUX 35, and the address values of the horizontal and vertical sizes of the image signals detected by the image size detection unit 100 are output from the position detection unit 200. The video position address output unit 300, which is latched by the detection signal and bit-transformed to output the position value of the current video signal, and the CPU 36, the memory 37, the lookup table 38, and the data buffer 39. The control unit 400 receives the position address value of the current image signal output from the image position address output unit 300 and outputs convergence data to be corrected by an error by comparing with the position value of the set image signal. Consists of.

The synchronizing separator 11 separates the horizontal synchronizing signal and the vertical synchronizing signal from the composite image signal output photoelectrically converted from the camera. The synchronous waveform shaping unit 12 waveform-forms and outputs the separated horizontal synchronous signal and the vertical synchronous signal. The vertical clock generator 17 generates a vertical clock signal. The reference horizontal pulse generator 13 inputs the waveform-shaped horizontal pulses to generate the reference horizontal pulses by the horizontal clock signal. The reference vertical pulse generator 15 inputs the waveform-shaped vertical pulses to generate the reference vertical pulses by the vertical clock signal. The horizontal counter 14 counts the number of horizontal clocks during the reference horizontal pulse section generated from the reference horizontal pulse generator 13. The vertical counter 16 counts the number of vertical clocks during the reference vertical pulse section generated from the reference vertical pulse generator 15. The MUX 18 selectively outputs the counting value of the horizontal pulse section and the counting value of the vertical pulse section by the horizontal synchronizing signal or the vertical synchronizing signal. The luminance separator 19 separates and outputs the pure luminance signal by removing the synchronization portion from the composite video signal. The D / A converter 20 converts and outputs an image level adjustment signal to an analog signal for maintaining the image data at a constant level. The synthesizer 21 mixes and outputs the luminance signal detected by the luminance separator 19 and the image level adjustment signal converted from the D / A converter 20 into an analog signal. The video pulse counter 22 calculates the magnitude of the video signal output from the mixer 21 and feeds the calculated value back to the CPU 36 to control the video level constantly. The image center point detector 23 inputs the magnitude value of the image signal calculated from the image pulse counter 22 to detect and output the center position by the center position detection control signal output from the CPU 36. The pulse selector 24 inputs the center position data output from the image center point detector 23 to detect and output the signal having the largest pulse width in comparison with the reference data output from the CPU 36. The first data comparator 25 receives the counting value of the horizontal pulse section output from the horizontal counter 14 and the counting value of the vertical pulse section output from the vertical counter 16 and outputs from the CPU 36. The reset signal is output when the horizontal and vertical start data values are compared and matched. The screen start counter 26 is loaded by the reset signal output from the first data comparator 25 to output horizontal and vertical reset pulses. The second data comparator 27 receives the horizontal clock signal and the vertical clock signal, and compares the horizontal clock signal and the vertical clock signal output from the CPU 36 and outputs a reset signal when the horizontal clock signal matches the vertical clock signal. The variable counter 28 is loaded by the reset signal output from the second data comparator 27 to vary the screen sector size. The third data comparison unit 29 receives the variable sector size value from the variable counter 28 and compares it with the sector size value output from the CPU 36 and outputs a reset signal when it matches. The sector dividing counter 30 receives the horizontal reset signal and the vertical reset signal from the screen start counter 26 and is loaded by the reset signal output from the third data comparator 29 to be perpendicular to the horizontal section reset signal. Output the interval reset signal. The fourth data comparison unit 31 receives a predetermined decoder value output from the lookup table, compares it with the positioning value output from the CPU 36, and outputs a reset signal when it matches. The sector decoder 32 receives the horizontal section reset signal and the vertical section reset signal output from the sector dividing counter 30 and outputs a decoder pulse for setting a specific portion of image data generated from the outside. The AND gate 33 performs a logical AND operation on the signal having the largest pulse width selected and output from the pulse selector 24 and the decoder pulse output from the sector decoder 32. The address latch 34 receives the horizontal or vertical section count value selected and output from the MUX 18 and latches the output value by the signal output from the AND gate 33. The MUX 35 separates the signal latched from the address latch 34 into 8 bits of data by a predetermined selection signal and outputs the data. The CPU 36 outputs an image level adjustment signal, a horizontal and vertical start data value, a center position detection control signal, a sector size value, a decoder pulse generation control signal, and a position setting value for maintaining the image data at a constant level. The 8-bit current video position outputted from the MUX 35 is recognized, and the convergence data to be corrected by the error is output by comparing with the set position value. The lookup table 38 outputs the decoder value to the fourth data comparator 31 according to the decoder pulse generation control signal of the CPU 36. The memory 37 stores various data for correcting the convergence of the present invention, and temporarily stores data generated during the convergence correction. The data buffer 39 outputs convergence data to be corrected under the control of the CPU 36.

FIG. 2 is an image point state diagram for sector division in the sector division counter 30 in FIG.

One preferred embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2 above.

The present invention captures an image signal projected on the screen of a projection television with a camera and automatically adjusts the convergence using the captured image signal. The video synchronous separator 11 separates the horizontal synchronous signal and the vertical synchronous signal from the composite video signal photoelectrically converted from the camera and outputs the horizontal synchronous signal to the synchronous waveform shaping unit 12. The synchronous waveform shaping unit 12 waveform-forms and outputs the separated horizontal synchronous signal and the vertical synchronous signal. The vertical clock generator 17 generates a vertical clock signal. The reference horizontal pulse generator 13 inputs the waveform-shaped horizontal pulses and generates the reference horizontal pulses by the horizontal clock signal of 28.63 MHz, and outputs the generated horizontal pulses to the horizontal counter 14. The reference vertical pulse generator 15 inputs the waveform-shaped vertical pulses, generates a reference vertical pulse by the vertical clock signal, and outputs the reference vertical pulses to the vertical counter 16. Since the maximum value of the horizontal pulse uses 6 bits in the program, the basic clock should be 35nsec × 64 = 2240 = nsec. Since the maximum value of the vertical pulse uses 11 bits in the program, it should be 35nsec x 2048 = 71.68μsec. As the width of this horizontal or vertical pulse increases, the variable value increases, but it is inefficient because many bits must be used. The horizontal counter 14 counts the number of horizontal clocks during the reference horizontal pulse period generated from the reference horizontal pulse generator 13 to detect the left and right sizes of the screen currently recognized by the camera. For example, one dot on the initial full screen is displayed on the left screen, and the convergence data is moved so that the displayed state is adjacent to the far left of the screen. At this time, the CPU 36 reads the count value of the nearest instant. In this way, the value on the right is also read and the values left and right are subtracted from each other to recognize the remaining value as the current screen size. The vertical counter 16 counts the number of vertical clocks during the reference vertical pulse section generated from the reference vertical pulse generator 15 to detect the vertical size of the screen currently recognized by the camera. At this time, the horizontal or vertical count value is continuously counted, and is reset by the reference horizontal signal and the reference vertical signal, and the MUX 18 is counted in the horizontal pulse section and the vertical counter (outputted from the horizontal counter 14). The counting value of the vertical pulse section output from 16) is selectively output by the horizontal synchronizing signal or the vertical synchronizing signal.

In addition, the luminance separation unit 19 removes the synchronization portion from the composite video signal and outputs the pure luminance signal separated into a high state and a low state. In this case, when the level of the peripheral portion and the central portion is equal, the image of the peripheral portion cannot be detected. Therefore, the amount of ambient light of the projection television must be increased or the level of the detected video signal must be increased. In the present invention, a method of increasing the level of the video signal is used, and the reference level of the video signal is generated from the CPU 36 to increase the level of the detected video signal. The D / A converter 20 converts an image level adjustment signal for maintaining at a constant level output from the CPU 36 into an analog signal and outputs it to the synthesizer 21. The synthesizer 21 mixes the luminance signal detected by the luminance separator 19 and the image level adjustment signal converted from the D / A converter 20 into an analog signal so as to always maintain the desired level. This not only keeps the level at the periphery and the center as well as the same brightness difference between the red, blue, and green. The video pulse counter 22 calculates the magnitude of the video signal output from the mixer 21 and feeds the calculated value back to the CPU 36 to control the video level constantly. The image center point detector 23 inputs the magnitude value of the image signal calculated from the image pulse counter 22 to detect and output the center position by the center position detection control signal output from the CPU 36. Here, the image center means that when the dot is displayed on the screen, the image is displayed on several horizontal lines when the image is read by the camera. Among them, the image part having the largest DC level in the center. The image pulse selector 24 inputs the center position data output from the image center point detector 23 to detect and output a signal having the largest pulse width in comparison with the reference data output from the CPU 36. The first data comparator 25 receives the counting value of the horizontal pulse section output from the horizontal counter 14 and the counting value of the vertical pulse section output from the vertical counter 16 and outputs from the CPU 36. The reset signal is output to the screen start counter 26 when the horizontal and vertical start data values are compared and matched. The screen start counter 26 is loaded by the reset signal output from the first data comparator 25 to output horizontal and vertical reset pulses. The second data comparator 27 receives the vertical clock signal and the vertical clock signal and compares the horizontal clock signal and the vertical clock signal output from the CPU 36 and outputs a reset signal when the vertical clock signal matches. The variable counter 28 is loaded by the reset signal output from the second data comparator 27 to vary the screen sector size. The third data comparison unit 29 receives the variable sector size value from the variable counter 28 and compares it with the sector size value output from the CPU, and outputs a reset signal to the sector division counter 30 when they match. . The sector dividing counter 30 receives the horizontal reset signal and the vertical reset signal from the screen start counter 26 and is loaded by the reset signal output from the third data comparator 29 to be perpendicular to the horizontal section reset signal. Output the interval reset signal. Referring to the specific operation of the sector division counter for outputting the horizontal section reset signal and the vertical section reset signal, the digital convergence uses a reference point of 5 points horizontally and 5 points vertically. Calculate the remaining values. The 5 x 5 point used as a reference is a screen area where the inner rectangle is actually visible in FIG. 2 on the screen, and the outer rectangle indicates an area required for convergence deflection. Convergence reference data for deflection are indicated by (⊙) and are obtained by an interpolation equation corresponding to the values y = ax ⁴ + bx ³ + cx ² + dx + e. However, in order to know which part is being adjusted, 25 points in the inner rectangle are displayed at each position. At this time, to display at the correct position and to read data only in the relevant part, a decoder is required to set the position.

The position decoder sets the value of one section by the current screen size and compares the sector of the section to be adjusted with the value output from the CPU 36 to output only the same section. At this time, the lookup table 38 outputs the decoder value to the fourth data comparator 31 according to the decoder pulse generation control signal of the CPU 36. The fourth data comparator 31 receives the decoder pulse and the predetermined decoder value output from the lookup table 38 and compares it with the positioning value output from the CPU 36 to match the reset signal with the sector decoder. Output to (32). The sector decoder 32 receives the horizontal section reset signal and the vertical section reset signal output from the sector dividing counter 30 and receives a decoder pulse for setting a specific portion of image data generated from the outside. Outputs one terminal of). The AND gate 33 multiplies the signal having the largest pulse width selected and output from the pulse selector 24 by the decoder pulse output from the sector decoder 32 and outputs the result to the clock stage of the address latch 34. The address latch 34 receives the horizontal or vertical section counting value selected and output from the MUX 18 and latches the signal by the signal output from the AND gate 33 to output to the MUX 35. The MUX 35 separates the signal latched from the address latch 34 into 8 bits of data by a predetermined selection signal and outputs the data. At this time, the CPU 36 outputs to the MUX 35. The MUX 35 separates the signal latched from the address latch 34 into 8 bits of data by a predetermined selection signal and outputs the data. At this time, the CPU 36 recognizes the 8-bit current image position output from the MUX 35 and compares the current image position with the set position value to output the convergence data to be corrected by the error to the data buffer 39. The data buffer 39 outputs convergence data to be corrected under the control of the CPU 36.

As described above, the present invention detects the horizontal and vertical size of a video signal on a projection television, and then outputs an address corresponding to the position value of the video signal corresponding to the detected size, and thus the address corresponding to the position value of the video signal set. Since the convergence is corrected by shifting the convergence data as much as the error after the comparison with the, the inconvenience of manual operation is eliminated, and the image quality deterioration due to the manual adjustment is prevented.

Claims (4)

1. An automatic convergence adjustment circuit of a projection television, comprising: image size detecting means for inputting a composite video signal to generate address values for the horizontal and vertical sizes of the video signal, and detecting only a pure luminance signal from the composite video signal; The position detection means for detecting the position of the image signal by the horizontal and horizontal section counting values and the horizontal and vertical clock signals, and the address value for the horizontal and vertical size of the image signal detected by the image size detection means. Video position address output means for latching and bit-converting by the position detection signal of the video signal output from the means and outputting the position value of the current video signal, and the position address of the current video signal output from the video position address output means. Receives a value and compares it with the position value of the set video signal to correct for error An automatic convergence adjustment circuit, comprising: control means for outputting convergence data. The apparatus of claim 1, wherein the image size detecting unit comprises: a synchronous separator 11 for separating and outputting a horizontal synchronous signal and a vertical synchronous signal from a composite video signal outputted photoelectrically from a camera; A synchronous waveform shaping section 12 for waveform shaping and outputting a synchronous signal, a vertical clock generating section 17 for generating a vertical clock signal, and a horizontal pulse shaped horizontal pulse from the synchronous waveform shaping section 12 are inputted and A reference horizontal pulse generator 13 generating a reference horizontal pulse by a clock signal, and a reference waveform generating a vertical vertical pulse by the vertical clock signal by inputting a waveform pulsed vertical pulse from the synchronization waveform shaping unit 12. The vertical pulse generator 15, the horizontal counter 14 for counting the number of horizontal clocks during the reference horizontal pulse section generated from the reference horizontal pulse generator 13, and the reference vertical pulse generator 15 The vertical counter 16 counting the number of vertical clocks during the generated reference vertical pulse section, and the counting value of the horizontal pulse section output from the horizontal counter 14 and the vertical pulse section output from the vertical counter 16. And a mux (18) for selecting and outputting a counting value by a horizontal synchronous signal or a vertical synchronous signal. 3. The position detection means according to claim 2, wherein the position detecting means includes: a luminance separation unit (19) for removing the synchronization portion from the composite video signal to separate and output the pure luminance signal, and for adjusting the image level for maintaining the image data at a constant level. A D / A converter 20 for converting and outputting a signal into an analog signal, and a luminance signal detected by the luminance separation unit 19 and an image level adjustment signal converted into an analog signal from the D / A converter 20 are mixed. A video pulse counter for calculating the magnitude of the video signal output from the mixer 21 and the mixer 21, and feeding back the calculated value to the CPU 36 to control the video level constantly. 22) and an image center point detector 23 for inputting the magnitude value of the image signal calculated from the image pulse counter 22 and detecting and outputting the center position by the center position detection control signal output from the CPU 36. And a pulse selector 24 for inputting the center position data output from the image center point detector 23 to detect and output a signal having the largest pulse width in comparison with the reference data output from the CPU 36. The counting value of the horizontal pulse section output from the horizontal counter 14 and the counting value of the vertical pulse section output from the vertical counter 16 are received, and the horizontal and vertical start data values output from the CPU 36 are compared. A screen start counter loaded with a first data comparator 25 for outputting a reset signal and a reset signal output from the first data comparator 25 for outputting horizontal and vertical reset pulses when they match. And second data for receiving the horizontal clock signal and the vertical clock signal, comparing the horizontal clock signal output from the CPU 36 with the vertical clock signal, and outputting a reset signal upon matching. (27), a variable counter 28 loaded by the reset signal output from the second data comparator 27 to vary the screen sector size, and a variable sector size value from the variable counter 28. A third data comparator 29 for receiving a reset signal when the input signal is matched with the sector size value received from the CPU 36, and a horizontal reset signal and a vertical reset signal from the screen start counter 26; A sector division counter 30 which is loaded by the reset signal output from the third data comparator 29 and outputs a horizontal section reset signal and a vertical section reset signal, and a predetermined output from the lookup table. A fourth data comparison unit 31 which receives a decoder value and compares it with the positioning value output from the CPU 36 and outputs a reset signal when the decoder value is matched, and a horizontal section output from the sector division counter 30; Reset A sector decoder 32 for receiving a signal and a vertical section reset signal and outputting a decoder pulse for setting a specific portion of externally generated image data, and having a largest pulse width selected and output from the pulse selector 24; And an AND gate (33) for performing an AND operation on the signal and the decoder pulse output from the sector decoder (32). 4. The control unit according to claim 3, wherein the control unit comprises: an image level adjustment signal, horizontal and vertical start data values, a center position detection control signal, a sector size value, a decoder pulse generation control signal, and position setting for maintaining the image data at a constant level. A CPU 36 for outputting a value and outputting convergence data to be corrected by an error by recognizing an 8-bit current image position output from the MUS 35 and comparing it with a set position value, and the CPU 36 A lookup table 38 for outputting the decoder value to the fourth data comparator 31 according to the decoder pulse generation control signal of the present invention, and various data for correcting the convergence of the present invention. Automatic conversion, characterized in that it comprises a memory (37) for temporarily storing data generated at the time and a data buffer (39) for buffering and outputting the convergence data to be corrected under the control of the CPU (36). Stud Joe Regular circuit.