KR0132957B1 - Transmitter receiver apparatus having steady source bit rate - Google Patents

Abstract

According to the present invention, after an AAL header and a payload are configured for a video, audio, etc. signal having an identity source bit rate in B-ISDN, ATM cell data is generated and transmitted to a lower layer (ATM layer), and the received ATM The purpose of the AAL is to extract the correct payload of the AAL from the cell and recover the data stream with the identity source bit rate.

Description

Transmitter / receiver and bitstream with constant source bit rate

1 is a configuration diagram of a video broadband terminal adapter system to which the present invention is applied;

2 is a video AAL-1 block diagram,

3 is a detailed block diagram of an AAL-1 transmitter;

4 is a detailed block diagram of an AAL-1 receiver;

5 is a block diagram of an AAL-1 controller;

6 is a process flow diagram of an AAL-1 bitstream.

* Explanation of symbols for the main parts of the drawings

6: System control unit 7: Codec interface unit

8: TX FIFO 9: ALL-1 transmitter

15, 20: CS transmission function block 16, 19: SAR transmission function block

10: controller 17, 18: ATM header multiplexer

The present invention relates to Asynchronous Transfer Module Adaptation (AAL-1) having an identity source bit rate for restoring a data stream having an identity source bit rate in a broadband integrated information digital network (B-ISDN). Layer-1).

In general, the B-ISD cannot support not only the AAL-1 service synchronized with the network clock but also a service having an identity source bit rate that is not synchronized with the network clock.

Accordingly, the present invention devised to solve the above problems consists of the AAL-1 header and the payload of a video, audio, etc. having a constant source bit rate in the B-ISDN, and then generates ATM cell data An AAL-1 function for transmitting to a layer (ATM layer), extracting the correct payload of AAL-1 from a received ATM cell, and restoring a data stream with an identity source bit rate is provided.

A transmission apparatus of the present invention for achieving the above object comprises: codec interface means for receiving data and outputting transmission data and transmission clock; Transmission FIFO (First In First Out) means for receiving the transmission data, the transmission clock, and the transmission read signal, respectively, the transmission clock being input by the control of the transmission start signal, and outputting transmission data and transmission flag; AAL-1 transmitting means for receiving the transmission data, the transmission flag, the transmission remaining time stamp signal, and the control signal, respectively, and output the ATM transmission data, the ATM transmission clock, the transmission flag, and the remaining time stamp read signal, respectively; Clock restoring means for receiving a network clock and the received time stamp read signal remaining with the reception clock and outputting the remaining time stamp signal to the ALL-1 transmitting means; And control means for outputting the transmission start signal and the control signal for causing the ALL-1 transmission means to transmit ATM data.

In addition, the present invention provides a receiving device having an identity source bit rate, the ATM receiving cell FIFO means for storing the transferred ATM receiving data, ATM receiving clock, and receives the receiving read signal and outputs the first data and the first receiving flag ; The first data, the first receiving flag, and the second receiving flag are input according to a control signal, and the receiving read signal, the second receiving data, the receiving write signal, the remaining time stamp writing signal, and the remaining remaining time stamp signal are output. ALL-1 receiving means; Control means for generating the control signal; Reception FIFO means for receiving the second reception data, the reception write signal, and the reception clock to output the second reception flag and output a third reception data; Codec interface means for receiving the third data and the reception clock; And clock restoring means for receiving the remaining time stamp write signal and the received remaining time stamp signal, and outputting the reception clock.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 is an overall block diagram of a video broadband terminal adapter (hereinafter referred to as B-TA) system to which the present invention is applied.

As shown in the figure, the video B-TA system includes an input unit 1 of a video camera or a VTR, an output unit 2 such as a TV, a DS3 codec unit 3, a video AAL-1 interface unit 4, and an ATM network. It consists of the interface part 5 and the system control part 6.

In the DS3 codec unit 3, the video signal and the analog audio signal from the input unit 1 are multiplexed and compressed to be encoded by B3ZS. The signal encoded by the B3ZS is made into ATM cell data using the AAL-1 header and the payload in the video AAL-1 interface unit 4, and the ATM signal is transmitted to the ATM network interface unit 5 by making the ATM cell data.

The ATM network interface unit 5 processes the ATM cell data by adding an ATM header and HEC (Header Error Control) octets to the ATM cell data, and then converts the data into an STM-1 frame via the physical layer to transmit the optical signal.

Also, the ATM cell received through the physical layer of the ATM interface unit 5 is transferred to the video AAL-1 interface unit 4. The video AAL-1 interface unit 4 checks the header of the AAL-1 at the payload of the ATM cell, processes only the correct AAL-1 payload as a bitstream, and then encodes the line with B3ZS to the DS3 codec unit 3. To pass.

The DS3 codec unit 3 decodes the B3ZS line coded signal and then demultiplexes and compresses and reproduces the video signal and the audio signal, respectively. The reproduced video and audio signals display video / audio through an output unit 2 such as a TV.

At this time, the system controller 6 is responsible for the processing and control of the protocol for the above process.

The configuration of the video AAL-1 interface of FIG. 1 will be described in detail with reference to FIG. 2.

The video AAL-1 interface block includes a DS3 codec interface unit 7, a transmission FIFO 8, an AAL-1 transmission unit 9, a control unit 10, an ATM receiving cell FIFO 11, and an AAL-1 reception unit 12. And a receiving FIFO 13 and a clock restoring unit 14.

The B3ZS signal transmitted to the DS3 codec unit 3 of FIG. 1 is decoded by the DS3 codec interface unit 7 to generate transmission data (txdata) and transmission clock (txclk) signals, and the reception FIFO 13 receives the reception data. The transmission of the transmission clock txclk signal is controlled by the control unit 10, and is stored in the transmission FIFO 8 which is a serial to parallel FIFO with a transmission clock of 44.736 Mbps. In addition, the transmission clock txclk is transmitted from the DS3 codec interface unit 7 to the clock recovery unit 14 in order to transmit the time information of the transmitting side to the receiving side.

The AAL-1 transmitter 9 reads the 44.736 Mbps bitstream stored in the transmit FIFO 8 in units of bytes, receives 47 octets of the AAL-1 payload and transmit RTS, and multiplexes with one octet of the AAL-1 header. A 48-octet ATM payload and a transmit flag (txflag) are input, and a transmit read clock (txRD) is output to the transmit FIFO (8). The ATM header data is multiplexed with the ATM header (or ATM header information) obtained from the controller 10 to make ATM cell data and transmitted to the ATM network interface 5.

In addition, the control unit 10 receives the address and data signals from the system control unit 6 and the control signals of the system control unit 6 from the system control unit 6 of FIG. 1 and transmits a control signal (transmission start signal) necessary for the video AAL-1 interface unit 4. And a loopback signal, a clear signal, and the like, and provide an ATM header value such as an assigned virtual channel (VCI) to the AAL-1 transmitter 9 and the AAL-1 receiver 12.

On the other hand, the ATM receiving cell FIFO 11 on the receiving side receives ATM cell data and outputs the ATM receiving cell data to the AAL-1 receiving unit 12, which is controlled by the controller 10. In response to the transmission, the ALL-1 payload is transmitted to the reception FIFO 13, and the reception RTS and RTS_WR signals are transmitted to the clock recovery unit 14.

The receiving FIFO 13 transmits a receiving flag to the AAL-1 receiving unit 12, and data stored in the receiving FIFO 13 is paralleled using the clock rxclk restored by the clock restoring unit 14. The received data (rxdata) is read in parellel to serial) and transmitted to the DS3 codec interface unit 7 together with the recovery clock (rxclk).

The DS3 codec interface unit 7 encodes the 44.736 Mbps recovery (rxclk) clock received from the clock restoration unit 14 and the received reception data (rxdata) of the reception FIFO 13 by B3ZS, and the DS3 codec unit ( 3) to pass.

The clock recovery unit 14 into which the network clock is input is composed of a transmission clock generator and a transmission clock recovery unit. In the transmission clock generator, the clock information of the transmitter is transmitted to the AAL-1 transmitter 9 and used by the receiver. The clock clock recovery unit receives the received clock information from the AAL-1 receiving unit 12 and restores the clock of the transmitting side.

That is, the ATM receiving cell FIFO 11 functions to store the received ATM cell from the ATM network interface unit 5 in units of bytes.

The AAL-1 receiving unit 12 reads the ATM cell stored in the ATM receiving cell FIFO 11 and checks whether it is the same as the ATM header allocated from the control unit 10 to discard the incorrect ATM payload. The correct ATM payload again checks the one-octet AAL-1 header and passes only the correct 47-octet AAL-1 payload to the receiving FIFO 13. Incorrect payloads are discarded even by the 1-bit calibration function. The time information of the transmitting end received in the AAL-1 header is transmitted to the clock restoring unit 14.

Next, the AAL-1 transmitter will be described in detail with reference to FIG. 3.

The DS3 codec interface unit 7 which receives the received clock and the B3ZS signal from the clock recovery unit 14 outputs the transmission data and the transmission clock to the transmission FIFO 8, and the transmission clock signal txclk is controlled by the control unit 10. Is transmitted to the transmission FIFO (8) by the transmission start signal. The DS3 bit stream is stored in the transmission FIFO 8 by using the transmission clock txclk as this signal as a write signal (FIFO write signal) of the transmission FIFO 8. In addition, this signal allows the transmission clock generator of the recovery unit 14 to receive the remaining 4 bit time stamp signal (RTS signal) for the transmission clock from the AAL-1 transmitter 9 to transmit the time information of the transmitter. .

The AAL-1 transmitter 9 transmits a CS (Convergence Sublayer or CS) transmission function block 15, a SAR (Segmentation Aand Reassembly) transmission function block 16 and an ATM header multiplexer 17. It is composed.

The CS transmission function block 15 reads the transmission flag (txflag) status of the transmission FIFO 8 and reads the stored data into the transmission read (txRD) clocks by 47 octets (PDU), which is the AAL-1 payload unit, and transmits the SAR. Passed to block 16. When the modulo 8 ordering coefficient is 0, the RTS-RD signal is generated to receive the 4-bit transmission RTS value from the clock restoring unit 14. The transmission RTS value is inserted into the CSI field by one bit when the sequence coefficient is odd (1, 3, 5, 7), and combined with the sequence coefficient to generate the sequence number, and transmitted to the SAR transmission function block 16.

At this time, when the sequence coefficient is even, it is assigned to 0, and the sequence number is combined with the sequence coefficient to make the sequence number and transmitted to the SAR transmission function block 16.

In the SAR transmission function block 16, a sequence number protection field is formed of a 3-bit CRC (polynomial X ³ + X + 1) for a 4-bit sequence number. One octet of AAL-1 header is generated by adding one bit of even parity for seven bits of the sequence number and the sequence number protection field. This header is multiplexed with the 47-octet AAL-1 payload received from the CS transmission function block 15 to form a 48-octet ATM load.

The ATM header multiplexing unit 17 multiplexes the 4-octet ATM header information allocated by the control unit 10 and the 48-octet ATM payload configured by the SAR transmission function block 16 to generate ATM cell data. This ATM cell data transmits the transmission data (byte unit) synchronized with the ATM transmission clock to the ATM network interface unit 5.

Also, the processing of the AAL-1 bit stream is shown in FIG.

Next, the AAL-1 receiver will be described in detail with reference to FIG.

ATM received data transmitted from the ATM network interface unit 5 is stored in the ATM receiving cell FIFO 11, which is a FIFO having a parallel to parallel structure by the ATM receiving clock.

The AAL-1 receiving unit 12 is composed of an ATM header demultiplexing unit 18, a SAR receiving function block 19, and a CS receiving function block 20 to perform the reverse process of the AAL-1 transmitting unit 9.

The ATM header demultiplexer 18 reads the reception cell data (rxPDU) by using the reception read (rxRD) clock after seeing the status (rxflag) of the reception flag (rxflag). After separating the ATM header and the 48 octet ATM payload from the received cell data, the payload is transferred to the SAR receiving function block 19 if it is correct compared with the ATM header allocated by the control unit 10, and discarded otherwise. .

The SAR reception function block 19 separates one octet of the AAL-1 header and one octet of the AAL-1 payload from 48 octets of the ATM payload of 48 octets. If the sequence number, sequence number protection field, and parity in the AAL-1 header are correct, 47 bits of AAL-1 payload and sequence number (CSI bit + sequence coefficient) 4 bits are transmitted to the CS receiving function block 20. If the AAL-1 header is corrected and is corrected by cyclic redundancy checks (CRC), the payload of sequence number 4 bits and 47 octets is transferred to the CS receiving function block 20. If calibration is not possible, discard it.

In the CS receiving function block 20, the CSI bit is stored for every odd order coefficient (1, 3, 4, 7) using the sequence number, and when the 4-bit receiving RTS is secured, the receiving RTS value is clocked together with the RTS-WR signal. Transfer to the restoration unit 14. The AAL-1 payload (rxSDU) of 47 octets is stored in the reception FIFO 13 by the rxWR signal.

The data stored in the reception FIFO 13 restores the service clock on the transmission side from the 4-bit reception RTS value by the transmission clock recovery section of the clock restoration section 14. The recovery clock rxclk reads the reception data rxdata of the reception FIFO 13 into a serial bitstream and transfers the reception data rxclk to the DS3 codec interface unit 7 together with the recovery clock rxclk.

FIG. 5 is a block diagram of the control unit. As shown in the figure, the control signal of the address, the data, and the processor are respectively input to output the video ALL-1 control signal, the transmit / receive header write signal, and the header data. Controls the ALL-1 transceiver.

The present invention made as described above relates to an AAL-1 function implementation method for providing a service of equal source bit rate. Therefore, by providing a configuration scheme for providing constant bit rate service in B-ISDN, it is possible to easily provide an equal bit rate service in B-ISDN. In particular, there is an effect that can support not only the AAL-1 service synchronized with the network clock but also a service having an identity source bit rate that is not synchronized with the network clock.

Claims (4)

A transmission apparatus having an identity source bit rate, comprising: codec interface means (7) for receiving data and outputting transmission data and a transmission clock; Transmission FIFO (First In First Out) means (8) for receiving the transmission data, the transmission clock, and the transmission read signal, respectively, the transmission clock being input by the control of the transmission start signal, and outputting transmission data and transmission flag; ALL (Asynchronous Transfer) receiving the transmission data, the transmission flag, the transmission remaining time stamp signal (RTS), and the control signal, respectively, and outputting the ATM transmission data, the ATM transmission clock, the transmission flag, and the remaining time stamp read signal (RTS_RD), respectively. Module Adaptation Layer transmission means 9; Clock restoring means (14) for receiving a network clock and the reception clock and the remaining time stamp read signal (RTS_RD) and outputting a transmission remaining time stamp signal (RTS) to the ALL transmitting means (9); And control means (10) for outputting said transmission start signal and said control signal for causing the ALL transmission means (9) to transmit ATM data. 2. The AAL transmitting means (9) according to claim 1, wherein the AAL transmitting means (9) detects the transmission flag state and reads the data stored in the transmitting FIFO means (8) in transmission load (txRD) clock by payload unit, and the sequence coefficient is 0. To generate the remaining time stamp read signal (RTS), receive the 4-bit remaining time stamp signal (RTS) from the clock recovery unit 14, and output the RTS value (Convergence Sublayer) transmission means (15). and; A segment and reassembly (SAR) 16 configured to generate an ALL header by receiving an RTS value from the CS transmission number 15 to configure an ATM payload; And ATM header multiplexing means (17) for generating ATM cell data by multiplexing the ATM header information allocated by the control means (10) and the ATM payload configured by the SAR transmitting means (16). Transmission device having a source bit rate. A receiving apparatus having an identity source bit rate, comprising: an ATM receiving cell FIFO means (11) for storing transferred ATM receiving data, ATM receiving clock, and receiving a receiving read signal (rxRD) and outputting first data and a first receiving flag; )and; The first data, the first reception flag, and the second reception flag (rxflag) are received according to a control signal, and the reception read signal rxRD, the second reception data, the reception write signal rxWR, and the remaining time stamp write are received. ALL receiving means 12 for outputting the signal RTS_WR and the received remaining time stamp signal RTS; Control means (10) for generating the control signal; Reception FIFO means (13) for receiving the second reception data, the reception write signal (rxWR) and the reception clock (rxclk), outputting the second reception flag (rxflag), and outputting a third reception data; Codec interface means (7) for receiving the third data and a reception clock (rxclk); And a clock restoring unit (14) for receiving the remaining time stamp write signal (RTS_WR) and the received remaining time stamp signal (RTS) and outputting the reception clock (rxclk). Receiving device. The ATM receiving apparatus (12) according to claim 3, wherein the ALL receiving means (12) reads the first data using a read read (rxRD) clock by viewing the state (rxflag) of the receive flag (rxflag). ATM header demultiplexing means (18) for separating the payload from the ATM and outputting only the payload if it is correct in comparison with the ATM header control signal allocated by the control means (10); It receives the output of the ATM header demultiplexing means 18 and separates the AAL payload from the 48-octet ATM payload and outputs the AAL payload and sequence number if the sequence number, sequence number protection field and parity in the AAL header are correct. SAR receiving function means 19; And receiving the second reception flag rxflag, outputting the second reception data and the reception write signal rxWR to the reception FIFO means 13, and if the reception RTS is secured, the remaining time stamp write signal RTS_WR. And a CS receiving function block (20) for transmitting a received remaining time stamp signal (RTS) to the clock restoring means (14).