KR0121970B1 - Common-bus managing method in an exchanger - Google Patents

Abstract

A common bus management method for the ATM where enables to execute the recovery easily in the interruption of the bus. The said method comprising the steps of : (a) outputting the executing result of the command according to the command input of the operator; (b) transmitting the result data using the data communication between the processor; and (c) processing the command executing result in the several processor.

Description

How to manage the common bus of an electronic changer

1 is a block diagram showing hardware for implementing a method for managing a common bus of an all-electronic exchange according to the present invention.

FIG. 2 is a flowchart illustrating a step-by-step process for transmitting instructions to a specific or multiple processors after inputting instructions according to the present invention according to FIG.

3 is a flowchart illustrating a process for transmitting result information to a requested processor after processing a corresponding command according to the type of command after receiving a request command according to the present invention according to FIG.

4 is a flow chart showing step by step processing for a result of instruction execution received by a specific or multiple processors according to the present invention according to FIG.

* Explanation of symbols for main parts of the drawings

1 network 2 operator matching processor

3: operator port 4: bus

5: multiple processors

The present invention relates to the management of a dual dual-common bus of an electronic switchboard, and more particularly, to a method of managing a common bus of an electronic switchboard, which is suitable for more easily performing a recovery method in the event of a bus failure. .

In this regard, in the related art, in order to perform the current bus state (the number of fault occurrences) and the bus switching, the system port for the operator could not output such an operation. Efficient monitor with the terminal that can be matched by using RS-232C cable for each processor, and the desired result can be output or transferred only by the command provided by the processor. And there is a problem that can not be action to cause human and time waste.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional drawback, and when using a common bus resource, a common bus of an electronic switchboard can be made to perform a recovery method more easily in the event of a failure of the bus that is most problematic. The purpose is to provide a way to manage.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention for achieving the above object is as follows.

Referring to FIG. 1, FIG. 1 is a block diagram showing hardware according to the present invention, wherein reference numeral 1 is a control interworking network (CIN) and numeral 2 is an operator matching processor for communicating with the network 1, Reference numeral 3 is an operator port (System console (PC, CRY, PRINTER, etc.) to communicate with the operator matching processor (2) via a cable such as RS-232C and reference number 4 is a communication with the network (1) It is a redundant bus that provides a data path so that the reference numeral 5 denotes each of a plurality of processors communicating with the network 1 via the redundant bus 4.

Here, n, which is not described in FIG. 1, is an arbitrary integer.

The hardware according to the present invention will be described in more detail with reference to FIGS. 2, 3, and 4 to the operation of the software.

First, the network 1 primarily operates in the system for processing communication data for communication between a plurality of processors 5 through a redundant bus 4, and mainly distributes communication data messages to a processor that desires communication. In addition, the operator matching processor (2) is a processor for operator matching. Operator messages such as PC, CRT, and PRINTER can be used to send messages generated from the system such as conformity check, result message output, and system message output through the RS-232C cable. It is a processor dedicated to input / output control for output to 3).

Next, the operator port 3 is an input / output dedicated terminal (system console) used by an actual operator, and the redundant bus 4 can operate while multiple processors 5 share the same bus resource. As a physical hardware bus to ensure reliability, it is a physical transmission / reception path that operates in redundancy to ensure reliability.

In addition, the plurality of processors 5 are processors capable of transmitting / receiving communication data using a common redundant bus 4 resource and selecting desired bus resources from the duplicated bus 4 resources to communicate desired communications. Send / receive data.

2 is a flowchart illustrating a step-by-step process for transmitting an instruction to a specific or multiple processors after inputting an instruction according to the present invention, and is a step-by-step operation of processing an instruction input from an operator to outputting an instruction execution result. If the instruction is inappropriate, the command error message is output (101). If the instruction is appropriate, it is determined whether to simultaneously or multiple processors (5) to the specific processor or multiple processors. At the same time, the command is transmitted using the communication data (102, 103, 104).

3 is a flowchart illustrating a step-by-step process for transmitting result information to a requested processor after processing a corresponding command according to a type of command after receiving a request command according to the present invention. As a step-by-step operation of transmitting the data using a sequential operation, first, when the request instruction is a bus state transmission request, information on whether the current redundant bus is normal and the information on the currently selected bus currently being operated in the form of communication data are transmitted to the processor. (110, 111, 112).

Next, when the request instruction is not a bus state transmission request but a generated fault status transmission request, the types and cumulative counts detected by all hardware and software that have occurred up to now are configured in the form of communication data and transmitted to the requested processor (113, 114, 115). .

Then, when it is not the occurrence fault status transmission request, an error message is outputted when the request is not a bus changeover, and when the bus changeover request is determined, the appropriateness of the transfer request is determined, and when appropriate, the bus is switched and the communication for informing that the command execution state is normal. The data is sent to the requesting processor (116, 117, 118, 119).

In operation 120, the processor 120 determines the appropriateness of the transfer request and transmits communication data indicating that the instruction execution state is abnormal to the requesting processor.

4 is a flow chart showing step by step processing for a result of instruction execution received from a specific or multiple processors according to the present invention, the result of the execution of a specific or multiple processors to the operator registration processor 2 through the communication data In operation 121, the processor which acquires the result data checks whether the instruction execution result is appropriate.

Subsequently, the aptitude test result outputs a command execution result to the operator port 3 to inform the operator if appropriate, and outputs an error message to the operator port 3 if the aptitude test result is not appropriate (122, 123).

As described above, the present invention provides the basic data for determining whether the bus is normal or abnormal by outputting the number of occurrences of an abnormal state up to the present bus use state or the present state of a specific processor and, if necessary, providing a specific processor or By providing the ability to switch buses to multiple processors at the same time, it is possible to more easily perform a recovery method in the event of a bus failure, which is the most problematic when using common bus 4 resources.

Claims (3)

In step 101, a command error message is output if the command is inappropriate, and if the command of step 101 is appropriate, it is determined whether to simultaneously execute a plurality of processors. A step (102, 103, 104) of transmitting instructions to only a plurality of processors or simultaneously to a plurality of processors, and outputting a result of performing the instruction according to the instruction input by the operator; A second step of performing the command and transmitting the result data using the interprocessor communication data; And a third step of processing an instruction execution result received from the specific or multiple processors. The method of claim 1, wherein the second step includes transmitting information on whether the current redundant bus is normal and information on a bus that is currently selected and operated when the request command is a bus state transmission request (110, 111, 112). ; If the request instruction is not a bus state transfer request but a generated fault state transfer request, transmitting (113, 114, 115) the types and cumulative number of faults detected by all hardware and software that have occurred up to now; If it is not the request for the transfer of the generated fault status, an error message is output if the request is not a bus changeover. If the request is a bus changeover request, the appropriateness of the transfer request is determined. Transmitting to the requested processor (116, 117, 118, 119); And determining (120) an appropriateness of the transfer request and transmitting (120) communication data indicating that an instruction execution state is abnormal to the requesting processor. The method as claimed in claim 1, wherein the third step includes checking whether the result of the execution of the processor command is appropriate when the result of the execution of the specific or multiple processors is transmitted to the processor for matching the processor (121). ; Outputting a command execution result to an operator port to inform an operator if the adequacy test result is appropriate; and outputting an error message to an operator port if the adequacy test result is not appropriate (122, 123). How to manage.