JPWO2008111408A1 - Multilayer wiring board and manufacturing method thereof - Google Patents

Multilayer wiring board and manufacturing method thereof Download PDF

Info

Publication number
JPWO2008111408A1
JPWO2008111408A1 JP2009503965A JP2009503965A JPWO2008111408A1 JP WO2008111408 A1 JPWO2008111408 A1 JP WO2008111408A1 JP 2009503965 A JP2009503965 A JP 2009503965A JP 2009503965 A JP2009503965 A JP 2009503965A JP WO2008111408 A1 JPWO2008111408 A1 JP WO2008111408A1
Authority
JP
Japan
Prior art keywords
hole
wiring board
multilayer wiring
base material
hole conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009503965A
Other languages
Japanese (ja)
Other versions
JP5212359B2 (en
Inventor
善和 及川
善和 及川
秀行 森本
秀行 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2009503965A priority Critical patent/JP5212359B2/en
Publication of JPWO2008111408A1 publication Critical patent/JPWO2008111408A1/en
Application granted granted Critical
Publication of JP5212359B2 publication Critical patent/JP5212359B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0352—Differences between the conductors of different layers of a multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1258—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

電子部品の集積度が高くなっても、実装面積を犠牲にすることなく、放熱特性を格段に高めることができ、もって信頼性を向上させることができる多層配線基板及びその製造方法を提供する。本発明の多層配線基板１０は、複数のセラミック層１１Ａを積層してなる積層体１１と、この積層体１１の側面に形成された端子電極１３と、を備え、更に、積層体１１に搭載される第１、第２、第３の電子部品５１、５２、５３に接続するために積層体１１の上面からその内部の複数のセラミック層１１Ａを貫通する放熱用ビアホール導体１７と、この放熱用ビアホール導体１７に接続され且つ積層体１１内で放熱用ビアホール導体１７と端子電極１３とを接続するように一つのセラミック層１１Ａ内で面方向にビア導体が連設されてなる連続ビアホール導体１８と、を備えている。Provided are a multilayer wiring board and a method for manufacturing the same, which can significantly improve heat dissipation characteristics without sacrificing the mounting area even when the integration degree of electronic components is increased, and thereby improve the reliability. The multilayer wiring board 10 of the present invention includes a multilayer body 11 formed by laminating a plurality of ceramic layers 11A, and terminal electrodes 13 formed on the side surfaces of the multilayer body 11, and is further mounted on the multilayer body 11. A heat dissipating via-hole conductor 17 penetrating from the upper surface of the multilayer body 11 through the plurality of ceramic layers 11A in order to connect to the first, second, and third electronic components 51, 52, and 53; A continuous via-hole conductor 18 that is connected to the conductor 17 and has via conductors arranged in a plane direction in one ceramic layer 11A so as to connect the heat-radiating via-hole conductor 17 and the terminal electrode 13 in the multilayer body 11; It has.

Description

本発明は、多層配線基板及びその製造方法に関し、更に詳しくは、電子部品の集積度が上がり、配線構造が高密度化しても放熱特性を向上させることができる多層配線基板及びその製造方法に関するものである。  The present invention relates to a multilayer wiring board and a method for manufacturing the same, and more particularly to a multilayer wiring board capable of improving heat dissipation characteristics even when the integration degree of electronic components is increased and the wiring structure is increased in density. It is.

近年、半導体素子等の電子部品の高機能化及び小型化に伴って、これらの電子部品を搭載する多層配線基板も高機能化及び小型化が進んでいる。電子部品が高機能化するほど発熱しやすく、放熱対策が極めて重要になってくる。放熱対策が講じられた多層配線基板として、例えば特許文献１、２、３に記載された技術が知られている。In recent years, with the enhancement and miniaturization of electronic components such as semiconductor elements, the multilayer wiring board on which these electronic components are mounted has also become highly functional and miniaturized. Electronic components is likely to heat enough to high-performance, heat dissipation is becomes very important. As multilayer wiring boards in which measures for heat dissipation are taken, for example, techniques described in Patent Documents 1, 2, and 3 are known.

特許文献１にはセラミック基板に関する発明が記載されている。このセラミック基板では、セラミック基板のキャビティの底面にメタライズ層が形成されており、このメタライズ層からセラミック基板の主面に達する伝熱体がキャビティの壁面の一部をなすように複数箇所に設けられている。この伝熱体は、ＡｇやＣｕを主成分とし、セラミック基板と同時焼成可能な材料によって形成されている。このような伝熱体を設けることによって、キャビティに搭載された電子部品から発生する熱をメタライズ層及び伝熱体を介して外部へ放熱している。また、このセラミック基板には図７に部分的に示すようにキャビティの底面のメタライズ層１とキャビティの底面との対向面に形成されたメタライズ層２を接続する複数のサーマルビア３が設けられ、伝熱体以外にこれらのサーマルビア３からも放熱するようにしてある。尚、図７において、Ｄは電子部品である。  Patent Document 1 describes an invention related to a ceramic substrate. In this ceramic substrate, a metallized layer is formed on the bottom surface of the cavity of the ceramic substrate, and a heat transfer body that reaches the main surface of the ceramic substrate from this metallized layer is provided at a plurality of locations so as to form part of the wall surface of the cavity. ing. This heat transfer body is mainly made of Ag or Cu and is made of a material that can be fired simultaneously with the ceramic substrate. By providing such a heat transfer body, heat generated from the electronic component mounted in the cavity is radiated to the outside through the metallized layer and the heat transfer body. Further, the ceramic substrate is provided with a plurality of thermal vias 3 for connecting the metallized layer 1 formed on the opposite surface of the bottom surface of the cavity to the metallized layer 1 on the bottom surface of the cavity, as partially shown in FIG. In addition to the heat transfer body, heat is also radiated from these thermal vias 3. In FIG. 7, D is an electronic component.

特許文献２にはセラミック配線基板に関する発明が記載されている。このセラミック配線基板では、図８に示すように、電子部品Ｄの実装位置に、複数の放熱用スルーホール４が形成され、これらの放熱用スルーホール４は放熱用導体パターン５や接地用導体パターン６に接続されている。電子部品Ｄの熱は、放熱用スルーホール４、放熱用導体パターン５及び接地用導体パターン６を介して外部へ放熱される。  Patent Document 2 describes an invention related to a ceramic wiring board. In this ceramic wiring board, as shown in FIG. 8, a plurality of heat radiating through holes 4 are formed at the mounting position of the electronic component D, and these heat radiating through holes 4 are formed as heat radiating conductor patterns 5 and grounding conductor patterns. 6 is connected. The heat of the electronic component D is radiated to the outside through the heat radiating through hole 4, the heat radiating conductor pattern 5, and the grounding conductor pattern 6.

更に、特許文献３には回路部品内蔵モジュールが記載されている。この回路部品内蔵モジュールは、電気絶縁性基板が無機フィラーと熱硬化性樹脂とを含む第１の混合物を主体として形成され、第１の混合物の無機フィラーの含有量が高く、無機フィラーによって樹脂製の電気絶縁性基板の放熱性を高めている。更に、回路部品内蔵モジュールでも電子部品の直下にサーマルビアが設けられ、このサーマルビアが電子部品の搭載面と対向する面に形成された放熱用配線パターンに接続され、更に放熱性を高めている。  Further, Patent Document 3 describes a circuit component built-in module. In this circuit component built-in module, the electrically insulating substrate is mainly formed of a first mixture containing an inorganic filler and a thermosetting resin, and the content of the inorganic filler in the first mixture is high. The heat dissipation of the electrically insulating substrate is improved. Further, even in the circuit component built-in module, a thermal via is provided directly under the electronic component, and this thermal via is connected to a heat radiation wiring pattern formed on the surface facing the mounting surface of the electronic component, thereby further improving heat dissipation. .

特開２００２−２８９７４７JP2002-289747 特開平０３−２８６５９０JP 03-286590 A 特開２００１−２４４６３８JP2001-244638

しかしながら、特許文献１、３の技術の場合には、サーマルビアホールが基板を貫通している。そのため、多層基板を製造する時には貫通ビアホール導体が形成された各基材層を積層する必要があり、製造工程で貫通ビアホール導体が基材層から脱落することがある。また、キャビティ構造を持つモジュールにおいてモジュール規模が大きくなり部品の集積度が高くなると、キャビティの面積が大きくなり、その周囲の基板部分（桟部）の幅が狭くなるため、上面に配置した電子部品の放熱用ビアホール導体を基板表裏に貫通させて設けることが難しくなる。  However, in the techniques of Patent Documents 1 and 3, the thermal via hole penetrates the substrate. Therefore, when manufacturing a multilayer board | substrate, it is necessary to laminate | stack each base material layer in which the through-via-hole conductor was formed, and a through-via-hole conductor may fall out of a base material layer at a manufacturing process. In addition, if the module scale of a module having a cavity structure increases and the degree of integration of the components increases, the area of the cavity increases and the width of the surrounding substrate portion (crosspiece) becomes narrower. It is difficult to provide the heat dissipating via-hole conductor so as to penetrate the front and back of the substrate.

また、特許文献２の技術の場合には、放熱用スルーホール４が基板の表裏を貫通することなく、放熱用スルーホール４を基板内で放熱用導体パターン５や接地用導体パターン６に接続し、放熱用導体パターン５や接地用導体パターン６を介して外部へ放熱している。しかし、この構成によると、放熱用導体パターン５や接地用導体パターン６の断面積が極めて小さいため、放熱効率が悪い。  In the case of the technique of Patent Document 2, the heat dissipation through hole 4 is connected to the heat dissipation conductor pattern 5 and the grounding conductor pattern 6 within the substrate without the heat dissipation through hole 4 penetrating the front and back of the substrate. The heat is radiated to the outside through the heat dissipating conductor pattern 5 and the grounding conductor pattern 6. However, according to this configuration, since the cross-sectional areas of the heat dissipating conductor pattern 5 and the grounding conductor pattern 6 are extremely small, the heat dissipating efficiency is poor.

本発明は、上記課題を解決するためになされたもので、電子部品の集積度が高くなっても、実装面積を犠牲にすることなく、放熱特性を格段に高めることができ、もって信頼性を向上させることができる多層配線基板及びその製造方法を提供することを目的としている。  The present invention has been made to solve the above-described problems. Even when the integration degree of electronic components is increased, the heat dissipation characteristics can be remarkably improved without sacrificing the mounting area. An object of the present invention is to provide a multilayer wiring board that can be improved and a method for manufacturing the same.

本発明の多層配線基板は、複数の基材層を積層してなる積層体と、この積層体の側面または下面に形成された端子電極と、を備えた多層配線基板であって、上記積層体に搭載される電子部品に接続するために上記積層体の一方及び／または他方の主面からその内部の上記複数の基材層のうち少なくとも一層を貫通するビアホール導体と、このビアホール導体と上記端子電極とに接続され、一つの上記基材層内で面方向に導体が連設されてなる連続ビアホール導体と、を備えたことを特徴とするものである。  The multilayer wiring board of the present invention is a multilayer wiring board comprising: a laminate formed by laminating a plurality of base material layers; and a terminal electrode formed on a side surface or a lower surface of the laminate. A via-hole conductor penetrating at least one of the plurality of base material layers inside from one and / or the other main surface of the laminate to connect to an electronic component mounted on the via, and the via-hole conductor and the terminal A continuous via-hole conductor connected to an electrode and having a conductor continuously arranged in a plane direction in one of the base material layers.

本発明の多層配線基板において、上記連続ビアホール導体が同一の上記基材層に複数形成されていることが好ましい。  In the multilayer wiring board of the present invention, it is preferable that a plurality of the continuous via-hole conductors are formed on the same base material layer.

また、本発明の多層配線基板において、上記基材層の上記連続ビアホール導体が形成されている領域が導体膜によって被覆されていることが好ましい。  In the multilayer wiring board of the present invention, it is preferable that a region of the base material layer where the continuous via-hole conductor is formed is covered with a conductor film.

また、本発明の多層配線基板において、上記導体膜は、複数の上記連続ビアホール導体に跨るように形成されていることが好ましい。  In the multilayer wiring board of the present invention, it is preferable that the conductor film is formed so as to straddle a plurality of the continuous via-hole conductors.

また、本発明の多層配線基板において、上記導体膜は、上記連続ビアホール導体と電気的に導通していることを特徴とすることが好ましい。  In the multilayer wiring board of the present invention, it is preferable that the conductor film is electrically connected to the continuous via-hole conductor.

また、本発明の多層配線基板において、上記連続ビアホール導体は、少なくとも一つの上記基材層を介して上下に配置されていることが好ましい。  In the multilayer wiring board of the present invention, it is preferable that the continuous via-hole conductors are arranged above and below via at least one base material layer.

また、本発明の多層配線基板において、上記連続ビアホール導体は、他の基材層よりも薄い基材層に形成されていることが好ましい。  In the multilayer wiring board of the present invention, the continuous via-hole conductor is preferably formed on a base material layer thinner than the other base material layers.

また、本発明の多層配線基板において、上記連続ビアホール導体が上記基材層を貫通することが好ましい。  In the multilayer wiring board of the present invention, it is preferable that the continuous via-hole conductor penetrates the base material layer.

また、本発明の多層配線基板において、上記連続ビアホール導体が上記基材層を貫通しないことが好ましい。  In the multilayer wiring board of the present invention, it is preferable that the continuous via-hole conductor does not penetrate the base material layer.

また、本発明の多層配線基板において、上記ビアホール導体の上記基材層での軸芯方向の断面積は、上記連続ビアホール導体の上記基材層での軸芯方向の断面積より大きく形成されていることが好ましい。  In the multilayer wiring board of the present invention, the cross-sectional area of the via hole conductor in the base layer direction of the base layer is formed to be larger than the cross-sectional area of the continuous via hole conductor in the base layer direction of the base layer. Preferably it is.

また、本発明の多層配線基板において、上記電子部品の外部端子電極が上記積層体の主面に露出した上記ビアホール導体に接続されていることが好ましい。  In the multilayer wiring board of the present invention, it is preferable that the external terminal electrode of the electronic component is connected to the via-hole conductor exposed on the main surface of the multilayer body.

また、本発明の多層配線基板において、上記積層体は、一方の主面にキャビティを有していることが好ましい。  In the multilayer wiring board of the present invention, the laminate preferably has a cavity on one main surface.

また、本発明の多層配線基板において、上記基材層は、低温焼結セラミック材料からなることが好ましい。  In the multilayer wiring board of the present invention, the base material layer is preferably made of a low temperature sintered ceramic material.

また、本発明の多層配線基板の製造方法は、複数の基材層を積層してなる積層体と、この積層体の側面に形成された端子電極と、を備えた多層配線基板を製造するに際し、複数の基材層のうち少なくとも一層に、上記基材層を上下に貫通する貫通孔と、この貫通孔から複数連続する第２貫通孔または半貫通孔とを上記基材層の面方向へ延びるように形成する第１の工程と、上記貫通孔、及び上記第２貫通孔または上記半貫通孔に導電性材料を充填することにより、ビアホール導体及び連続ビアホール導体を形成する第２の工程と、を備えたことを特徴とするものである。  In addition, the method for manufacturing a multilayer wiring board of the present invention, when manufacturing a multilayer wiring board comprising a laminate formed by laminating a plurality of base material layers and terminal electrodes formed on the side surfaces of the laminate. In at least one of the plurality of base material layers, a through hole penetrating the base material layer vertically and a plurality of second through holes or semi-through holes continuous from the through hole are provided in the surface direction of the base material layer. A first step of forming the via hole, and a second step of forming a via hole conductor and a continuous via hole conductor by filling the through hole and the second through hole or the half through hole with a conductive material; , Provided.

また、本発明の多層配線基板の製造方法において、上記導電性材料によって上記貫通孔、及び上記第２貫通孔または上記半貫通孔を被覆する導体膜を上記基材層上に形成する第３の工程を備えていることが好ましい。  Further, in the method for manufacturing a multilayer wiring board according to the present invention, a third method of forming a conductive film covering the through hole and the second through hole or the half through hole with the conductive material on the base material layer. It is preferable to provide the process.

また、本発明の多層配線基板の製造方法において、上記第１の工程では、上記基材層にレーザを照射することにより、上記貫通孔、及び上記第２貫通孔または上記半貫通孔を形成することが好ましい。  In the method for manufacturing a multilayer wiring board of the present invention, in the first step, the base layer is irradiated with a laser to form the through hole and the second through hole or the half through hole. It is preferable.

また、本発明の多層配線基板の製造方法において、上記基材層がキャリアフィルムによって支持されており、キャリアフィルム側からレーザを照射することにより、上記貫通孔を形成することが好ましい。  Moreover, in the manufacturing method of the multilayer wiring board of this invention, it is preferable that the said base material layer is supported by the carrier film and forms the said through-hole by irradiating a laser from the carrier film side.

また、本発明の多層配線基板の製造方法において、上記基材層がキャリアフィルムによって支持されており、上記基材層側からレーザを照射することにより、上記貫通孔及び半貫通孔を形成することが好ましい。  In the method for producing a multilayer wiring board of the present invention, the base layer is supported by a carrier film, and the through hole and the semi-through hole are formed by irradiating a laser from the base layer side. Is preferred.

また、本発明の多層配線基板の製造方法において、上記第１、第２の工程における基材層は、未焼成のセラミックシートであり、この基材層を含む未焼成の積層体を作製した後、上記未焼成の積層体を焼成する第４の工程を備えていることが好ましい。  In the method for manufacturing a multilayer wiring board according to the present invention, the base material layer in the first and second steps is an unfired ceramic sheet, and an unfired laminate including the base material layer is produced. It is preferable to include a fourth step of firing the unfired laminate.

本発明によれば、電子部品の集積度が高くなっても、実装面積を犠牲にすることなく、放熱特性を格段に高めることができ、もって信頼性を向上させることができる多層配線基板及びその製造方法を提供することができる。  ADVANTAGE OF THE INVENTION According to this invention, even if the integration degree of an electronic component becomes high, the heat dissipation characteristic can be improved significantly without sacrificing the mounting area, and the reliability can be improved. A manufacturing method can be provided.

（ａ）〜（ｃ）はそれぞれ本発明の多層配線基板の一実施形態を示す図で、（ａ）はその断面図、（ｂ）はその要部を示す平面図、（ｃ）は放熱用ビアホール導体と放熱用連続ビアホール導体を拡大して示す平面図である。(A)-(c) is a figure which shows one Embodiment of the multilayer wiring board of this invention, respectively, (a) is the sectional drawing, (b) is a top view which shows the principal part, (c) is for heat dissipation It is a top view which expands and shows a via-hole conductor and the continuous via-hole conductor for thermal radiation. （ａ）〜（ｆ）はそれぞれ図１に示す多層配線基板のビアホール導体及びこれに接続された連続ビアホール導体の形成過程を示す工程図である。(A)-(f) is process drawing which shows the formation process of the via-hole conductor of the multilayer wiring board shown in FIG. 1, respectively, and the continuous via-hole conductor connected to this. 図１に示す多層配線基板の基材層を積層する状態を示す断面図である。It is sectional drawing which shows the state which laminates | stacks the base material layer of the multilayer wiring board shown in FIG. 本発明の多層配線基板の他の実施形態の要部を示す断面図である。It is sectional drawing which shows the principal part of other embodiment of the multilayer wiring board of this invention. 図４に示す多層配線基板のビアホール導体及びこれに接続された連続ビアホール導体の形成過程を示す工程図である。FIG. 5 is a process diagram showing a process of forming via hole conductors of the multilayer wiring board shown in FIG. 4 and continuous via hole conductors connected thereto. 本発明の多層配線基板の更に他の実施形態の要部を示す断面図である。It is sectional drawing which shows the principal part of other embodiment of the multilayer wiring board of this invention. 従来の多層配線基板の要部を示す断面図である。It is sectional drawing which shows the principal part of the conventional multilayer wiring board. 従来の他の多層配線基板の要部を示す断面図である。It is sectional drawing which shows the principal part of the other conventional multilayer wiring board.

１０、１０Ａ 多層配線基板
１１ セラミック層（基材層）
１３ 端子電極
１４ ビアホール導体
１７ 放熱用ビアビアホール導体
１８ 放熱用連続ビアホール導体
１００ キャリアフィルム
１１１Ａ セラミックグリーンシート（未焼成の基材層）
１１７ 放熱用ビアホール導体部
１１８、１１８Ａ 放熱用連続ビアホール導体部
１１９ 導体面部10, 10A multilayer wiring board 11 ceramic layer (base material layer)
13 terminal electrode 14 via hole conductor 17 heat dissipation via via hole conductor 18 heat dissipation continuous via hole conductor 100 carrier film 111A ceramic green sheet (unfired base material layer)
117 Heat Dissipation Via Hole Conductor 118, 118A Heat Dissipation Continuous Via Hole Conductor 119 Conductor Surface

以下、図１〜図６に示す実施形態に基づいて本発明を説明する。尚、各図中、図１の（ａ）〜（ｃ）はそれぞれ本発明の多層配線基板の一実施形態を示す図で、（ａ）はその断面図、（ｂ）はその要部を示す平面図、（ｃ）はビアホール導体と連続ビアホール導体を拡大して示す平面図、図２の(ａ）〜（ｆ）はそれぞれ図１に示す多層配線基板のビアホール導体及び連続ビアホール導体を形成する工程を示す工程図、図３は図１に示す多層配線基板の基材層を積層する状態を示す断面図、図４は本発明の多層配線基板の他の実施形態の要部を示す断面図、図５の(ａ）〜（ｆ）はそれぞれ図４に示す多層配線基板のビアホール導体及び連続ビアホール導体を形成する工程を示す工程図、図６は本発明の多層配線基板の更に他の実施形態の要部を示す断面図である。  Hereinafter, the present invention will be described based on the embodiment shown in FIGS. In each figure, (a) to (c) of FIG. 1 are diagrams showing an embodiment of the multilayer wiring board of the present invention, (a) is a sectional view thereof, and (b) is an essential part thereof. FIG. 2C is an enlarged plan view showing a via hole conductor and a continuous via hole conductor, and FIGS. 2A to 2F form the via hole conductor and the continuous via hole conductor of the multilayer wiring board shown in FIG. 1, respectively. FIG. 3 is a cross-sectional view showing a state in which the base material layer of the multilayer wiring board shown in FIG. 1 is laminated, and FIG. 4 is a cross-sectional view showing the main part of another embodiment of the multilayer wiring board of the present invention. FIGS. 5A to 5F are process diagrams showing steps of forming via-hole conductors and continuous via-hole conductors of the multilayer wiring board shown in FIG. 4, respectively, and FIG. 6 is still another embodiment of the multilayer wiring board of the present invention. It is sectional drawing which shows the principal part of a form.

第１の実施形態
本実施形態の多層配線基板１０は、例えば図１に示すように、複数の基材層（例えばセラミック層）１１Ａが積層されてなる積層体１１と、この積層体１１内に設けられた配線パターン１２と、積層体１１の側面に形成された端子電極１３と、を備えている。積層体１１の一方の主面（上面）は全面が複数の第１、第２の電子部品５１、５２を搭載する平坦面として形成されている。積層体１１の他方の主面（下面）の中央にはキャビティ１０Ａが形成され、このキャビティ１０Ａの底面に第３の電子部品５３が搭載されている。第１、第２、第３の電子部品５１、５２、５３は、いずれも配線パターン１２を介して多層配線基板１０を搭載するマザーボード等の実装用基板の表面電極（図示せず）に接続される。第１、第３の電子部品５１、５３は、それぞれ例えばシリコン半導体素子やガリウム砒素半導体素子等の能動素子からなり、第２の電子部品５２は、例えばコンデンサ、インダクタ等の受動素子からなっている。First Embodiment A multilayer wiring board 10 of the present embodiment includes, for example, as shown in FIG. 1, a laminated body 11 in which a plurality of base material layers (for example, ceramic layers) 11 </ b> A are laminated, and the laminated body 11. The wiring pattern 12 provided and the terminal electrode 13 formed on the side surface of the multilayer body 11 are provided. One main surface (upper surface) of the multilayer body 11 is formed as a flat surface on which the plurality of first and second electronic components 51 and 52 are mounted. A cavity 10A is formed at the center of the other main surface (lower surface) of the multilayer body 11, and a third electronic component 53 is mounted on the bottom surface of the cavity 10A. The first, second, and third electronic components 51, 52, and 53 are all connected to surface electrodes (not shown) of a mounting board such as a mother board on which the multilayer wiring board 10 is mounted via the wiring pattern 12. The The first and third electronic components 51 and 53 are each composed of an active element such as a silicon semiconductor element or a gallium arsenide semiconductor element, and the second electronic component 52 is composed of a passive element such as a capacitor or an inductor. .

而して、配線パターン１２は、図１に示すように、上下のセラミック層１１Ａの界面に所定のパターンで形成された面内導体（以下、「ライン導体」と称す。）１４と、上下のライン導体１４、１４等を電気的に接続するようにセラミック層１１Ａを貫通して設けられたビアホール導体１５と、キャビティ１０Ａを囲む積層体１１内に設けられたビアホール導体１５に接続され且つ積層体１１の下面周縁部に所定のパターンで配置して形成された表面電極１６と、を含んでいる。第１、第３の電子部品５１、５３は、例えばボールグリッドアレイ構造の接続用端子が半田ボールＢを介してビアホール導体（図示せず）の端面に電気的に接続され、また、第２の電子部品５２は、外部電極が半田フィレットＦを介してビアホール導体１５の端面に電気的に接続されている。以下、ビアホール導体を含む配線パターン１２について詳述する。尚、電子部品は、ビアホール導体に直接接続されないものを含んでいても良い。  Thus, as shown in FIG. 1, the wiring pattern 12 includes in-plane conductors (hereinafter referred to as “line conductors”) 14 formed in a predetermined pattern on the interface between the upper and lower ceramic layers 11A and the upper and lower ceramic layers 11A. A via hole conductor 15 provided through the ceramic layer 11A so as to electrically connect the line conductors 14, 14 and the like, and a via hole conductor 15 provided in the laminate 11 surrounding the cavity 10A, and the laminate. 11 and the surface electrode 16 formed by being arranged in a predetermined pattern on the peripheral surface of the lower surface. In the first and third electronic components 51 and 53, for example, a connection terminal having a ball grid array structure is electrically connected to an end face of a via-hole conductor (not shown) via a solder ball B. In the electronic component 52, the external electrode is electrically connected to the end face of the via-hole conductor 15 through the solder fillet F. Hereinafter, the wiring pattern 12 including the via-hole conductor will be described in detail. The electronic component may include one that is not directly connected to the via-hole conductor.

第１、第２、第３の電子部品５１、５２、５３は、高機能化及び小型化されるにつれて発熱量が多くなり、従来にも増して効率よく放熱されなくてはならない。そのため、本実施形態の多層配線基板１０では放熱用の配線構造に特殊な工夫が施されている。  The first, second, and third electronic components 51, 52, and 53 generate more heat as they become more functional and smaller, and must be radiated more efficiently than before. For this reason, in the multilayer wiring board 10 of this embodiment, a special device is applied to the wiring structure for heat dissipation.

即ち、多層配線基板１０は、図１の（ａ）、（ｂ）に示すように、積層体１１の上面の複数箇所から内部へ垂直に延びる複数の放熱用のビアホール導体（以下、「放熱用ビアホール導体」と称する。）１７と、この放熱用ビアホール導体１７に接続された上下二段の放熱用の連続ビアホール導体（以下、「放熱用連続ビアホール導体」と称する。）１８と、を備えている。また、積層体１１にはキャビティ１０Ａの底面の複数箇所から内部へ垂直に延びる複数の放熱用ビアホール導体１７が形成され、この放熱用ビアホール導体１７には上下二段の放熱用連続ビアホール導体１８が接続されている。  That is, as shown in FIGS. 1A and 1B, the multilayer wiring board 10 includes a plurality of heat dissipation via-hole conductors (hereinafter referred to as “heat dissipation”) extending vertically from a plurality of locations on the upper surface of the multilayer body 11. And a continuous via-hole conductor for heat dissipation (hereinafter referred to as “a continuous via-hole conductor for heat dissipation”) 18 connected to the heat-dissipating via-hole conductor 17. Yes. The laminated body 11 is formed with a plurality of heat dissipation via-hole conductors 17 extending vertically from a plurality of locations on the bottom surface of the cavity 10A, and the heat dissipation via-hole conductor 17 has two continuous upper and lower heat dissipation via-hole conductors 18. It is connected.

複数の放熱用ビアホール導体１７は、同図の（ｂ）に示すように縦横に配列して形成され、それぞれの上端面に半田ボールＢを介して第１の電子部品５１が接続されている。放熱用連続ビアホール導体１８は、同図の（ａ）に示すように少なくとも一層のセラミック層１１Ａを介して上下二段の配置されている。各放熱用連続ビアホール導体１８は、同図の（ａ）、（ｃ）に示すように一つのセラミック層１１Ａを貫通するビアホール導体が互いに部分的に繋がるように複数連設してセラミック層１１Ａの面方向に延びるように形成されている。放熱用連続ビアホール導体１８の左端は放熱用ビアホール導体１７に接続され、その右端が積層体１１の右側面の端子電極１３に接続されている。放熱用連続ビアホール導体１８をグランド電極に接続すれば、グランドを強化することができる。本実施形態では放熱用連続ビアホール導体１８が上下二段に渡って設けられているが、放熱量が少なければ必要に応じて一段だけ設けても良く、また、三段以上設けても良い。  The plurality of heat radiating via-hole conductors 17 are formed so as to be arranged vertically and horizontally as shown in (b) of the figure, and the first electronic component 51 is connected to each upper end surface via a solder ball B. The heat radiating continuous via-hole conductors 18 are arranged in two upper and lower stages through at least one ceramic layer 11A as shown in FIG. A plurality of continuous via-hole conductors 18 for heat dissipation are connected in series so that via-hole conductors passing through one ceramic layer 11A are partially connected to each other as shown in FIGS. It is formed to extend in the surface direction. The left end of the heat radiating continuous via hole conductor 18 is connected to the heat radiating via hole conductor 17, and the right end thereof is connected to the terminal electrode 13 on the right side surface of the multilayer body 11. If the continuous via-hole conductor 18 for heat dissipation is connected to the ground electrode, the ground can be strengthened. In the present embodiment, the heat radiating continuous via-hole conductor 18 is provided in two upper and lower stages. However, if the amount of heat radiation is small, only one stage may be provided, or three or more stages may be provided.

このような放熱用の配線構造では、第３の電子部品５３で発生する熱は、放熱用ビアホール導体１７及び放熱用連続ビアホール導体１８を介して端子電極１３から外部へ放熱される。放熱用連続ビアホール導体１８は、セラミック層１１Ａと同じ厚さを有するため、従来の印刷による放熱用導体パターンと比較して伝熱断面積が格段に大きく、放熱効率を格段に高めることができる。また、本実施形態では同一セラミック層１１Ａ内に複数の放熱用ビアホール導体１７及びそれに連設された複数の放熱用連続ビアホール導体１８が設けられている。これにより、放熱経路が複数確保され、放熱効率を更に高めることができる。また、放熱用ビアホール導体１７と放熱用連続ビアホール導体１８は、後述するように同一プロセスで一体的に形成することができるため、位置ズレすることがなく確実に接続されて接続信頼性を確保することができる。  In such a heat dissipation wiring structure, heat generated in the third electronic component 53 is radiated from the terminal electrode 13 to the outside through the heat dissipation via-hole conductor 17 and the heat dissipation continuous via-hole conductor 18. Since the heat dissipating continuous via-hole conductor 18 has the same thickness as the ceramic layer 11A, the heat transfer cross-sectional area is significantly larger than that of a conventional heat dissipating conductor pattern by printing, and the heat dissipating efficiency can be greatly increased. In the present embodiment, a plurality of heat dissipating via-hole conductors 17 and a plurality of heat dissipating continuous via-hole conductors 18 are provided in the same ceramic layer 11A. Thereby, a plurality of heat radiation paths are secured, and the heat radiation efficiency can be further increased. Further, since the heat radiating via-hole conductor 17 and the heat radiating continuous via-hole conductor 18 can be integrally formed in the same process as will be described later, they are securely connected without misalignment to ensure connection reliability. be able to.

放熱用ビアホール導体１７は、例えば図１の（ａ）に示すように各セラミック層１１Ａに形成された略円錐台形状のビアホール導体を上下に接続して形成されている。また、放熱用連続ビアホール導体１８は、同図の（ｂ）、（ｃ）に示すように放熱用ビアホール導体１７よりセラミック層１１Ａにおける断面積の小さな円錐台状のビアホール導体が水平方向で部分的に重なるように連続してライン状に形成されている。本実施形態では、レーザ光を用いてビアホール導体用の孔を形成するため、放熱用連続ビアホール導体の側面に凹凸ができる。ビアホール導体は、いずれも円錐台形状を呈し、広い下面が接続ランドとして機能し、各セラミック層１１Ａの導体ビアホールの位置合わせが容易になる。但し、ビアホール導体は、円錐台形状に制限されるものではなく、円柱状であっても良い。尚、上下のライン導体１４を接続するビアホール導体１５も放熱用ビアホール導体１７と同様に形成されている。  For example, as shown in FIG. 1A, the heat dissipating via-hole conductor 17 is formed by vertically connecting substantially frustoconical via-hole conductors formed in each ceramic layer 11A. Further, as shown in FIGS. 2B and 2C, the heat dissipating continuous via-hole conductor 18 is a frustoconical via-hole conductor having a smaller cross-sectional area in the ceramic layer 11A than the heat-dissipating via-hole conductor 17 in a horizontal direction. Are continuously formed in a line shape so as to overlap. In the present embodiment, since the via hole conductor hole is formed using laser light, the side surface of the heat radiating continuous via hole conductor can be uneven. Each of the via hole conductors has a truncated cone shape, and the wide lower surface functions as a connection land, so that the alignment of the conductor via holes of each ceramic layer 11A is facilitated. However, the via-hole conductor is not limited to a truncated cone shape, and may be a cylindrical shape. The via-hole conductor 15 that connects the upper and lower line conductors 14 is also formed in the same manner as the heat-dissipating via-hole conductor 17.

放熱用連続ビアホール導体１８は、図１の（ａ）に示すようにセラミック層１１Ａを貫通しているため、製造段階でセラミックグリーンシートを貫通させて連続ビアホール導体部を形成すると、セラミックグリーンシートから連続ビアホール導体部が脱落しやすくなる。況して、図１に示すように同一のセラミック層１１Ａに複数行に渡って放熱用連続ビアホール導体１８が形成されている場合には、製造段階で連続ビアホール導体部が更に脱落しやすくなる。  Since the continuous via-hole conductor 18 for heat dissipation passes through the ceramic layer 11A as shown in FIG. 1A, when the continuous via-hole conductor portion is formed by penetrating the ceramic green sheet at the manufacturing stage, the ceramic green sheet The continuous via-hole conductor is easy to drop off. As shown in FIG. 1, when the continuous via-hole conductors 18 for heat dissipation are formed on the same ceramic layer 11A over a plurality of rows as shown in FIG. 1, the continuous via-hole conductor portions are more easily dropped at the manufacturing stage.

そこで、本実施形態では、図１の（ｂ）に示すように複数の放熱用連続ビアホール導体１８が配列して形成されたセラミック層１１Ａの上面には導体膜１９が形成され、この導体膜１９と放熱用連続ビアホール導体１８が接続されて一体化している。即ち、導体膜１９は同一セラミック層１１Ａに形成された複数の放熱用連続ビアホール導体１８に跨って形成されている。この導体膜１９は、放熱用連続ビアホール導体１８と同一セラミック層１１Ａに形成された放熱用ビアホール導体１７をも被覆して一体化している。このように放熱用ビアホール導体１７と放熱用連続ビアホール導体１８が導体膜１９と一体化しているため、多層配線基板１０の製造工程でセラミック層１１Ａとなるセラミックグリーンシートから放熱用ビアホール導体１７及び放熱用連続ビアホール導体１８となる導電性ペーストがセラミックグリーンシートから脱落することがなく、確実にこれらのビアホール導体１７、１８を形成することができる。  Therefore, in the present embodiment, as shown in FIG. 1B, a conductor film 19 is formed on the upper surface of the ceramic layer 11A formed by arranging a plurality of heat radiating continuous via-hole conductors 18, and this conductor film 19 is formed. And a continuous via-hole conductor 18 for heat dissipation are connected and integrated. That is, the conductor film 19 is formed across the plurality of heat radiating continuous via-hole conductors 18 formed on the same ceramic layer 11A. The conductor film 19 covers and integrates the heat radiating via-hole conductor 17 formed on the same ceramic layer 11A as the heat radiating continuous via-hole conductor 18. Since the heat dissipation via-hole conductor 17 and the heat dissipation continuous via-hole conductor 18 are integrated with the conductor film 19 in this way, the heat dissipation via-hole conductor 17 and the heat dissipation from the ceramic green sheet that becomes the ceramic layer 11A in the manufacturing process of the multilayer wiring board 10. The conductive paste that becomes the continuous via-hole conductor 18 for use does not fall off from the ceramic green sheet, and the via-hole conductors 17 and 18 can be reliably formed.

本実施形態では基材層としてセラミック層を例に挙げて説明したが、基材層はセラミック層に制限されない。基材層としては、例えば熱硬化性の樹脂からなる樹脂層であっても良い。セラミック層である場合には、セラミック材料としては、例えば低温焼結セラミック（ＬＴＣＣ：Low Temperature Co-fired Ceramic）材料を使用することができる。低温焼結セラミック材料とは、１０５０℃以下の温度で焼結可能であって、比抵抗の小さな銀や銅等と同時焼成が可能なセラミック材料である。低温焼結セラミック材料としては、具体的には、アルミナやジルコニア、マグネシア、フォルステライト等のセラミック粉末にホウ珪酸系ガラスを混合してなるガラス複合系ＬＴＣＣ材料、ＺｎＯ−ＭｇＯ−Ａｌ２Ｏ３−ＳｉＯ２系の結晶化ガラスを用いた結晶化ガラス系ＬＴＣＣ材料、ＢａＯ−Ａｌ２Ｏ３−ＳｉＯ２系セラミック粉末やＡｌ２Ｏ３−ＣａＯ−ＳｉＯ２−ＭｇＯ−Ｂ２Ｏ３系セラミック粉末等を用いた非ガラス系ＬＴＣＣ材料等が挙げられる。セラミック層１１Ａの材料として低温焼結セラミック材料を用いることによって、配線パターン１２、放熱用ビアホール導体１７、放熱用連続ビアホール導体１８及び導体膜１９としては、例えば銀または銅等の低抵抗で低融点をもつ金属を用いることができ、積層体１１と配線パターン１２等とを１０５０℃以下の低温で同時焼成することができる。In the present embodiment, the ceramic layer is described as an example of the base material layer, but the base material layer is not limited to the ceramic layer. As the base material layer, for example, a resin layer made of a thermosetting resin may be used. In the case of the ceramic layer, for example, a low temperature co-fired ceramic (LTCC) material can be used as the ceramic material. The low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 1050 ° C. or less and can be simultaneously fired with silver, copper, or the like having a small specific resistance. Specifically, as the low-temperature sintered ceramic material, a glass composite LTCC material obtained by mixing borosilicate glass with ceramic powder such as alumina, zirconia, magnesia, and forsterite, ZnO—MgO—Al 2 O 3 — Crystallized glass-based LTCC material using crystallized glass of SiO 2 , BaO—Al 2 O 3 —SiO 2 ceramic powder, Al 2 O 3 —CaO—SiO 2 —MgO—B 2 O 3 ceramic powder, etc. Non-glass type LTCC materials using By using a low-temperature sintered ceramic material as the material of the ceramic layer 11A, the wiring pattern 12, the heat dissipating via-hole conductor 17, the heat dissipating continuous via-hole conductor 18 and the conductor film 19 have a low resistance and a low melting point such as silver or copper. The laminated body 11 and the wiring pattern 12 can be simultaneously fired at a low temperature of 1050 ° C. or lower.

また、セラミック材料として、高温焼結セラミック（ＨＴＣＣ：High Temperature Co-fired Ceramic）材料を使用することもできる。高温焼結セラミック材料としては、例えば、アルミナ、窒化アルミニウム、ムライト、その他の材料にガラスなどの焼結助剤を加え、１１００℃以上で焼結されたものが用いられる。このとき、配線パターン１２、放熱用ビアホール導体１７、放熱用連続ビアホール導体１８及び導体膜１９としては、例えばモリブデン、白金、パラジウム、タングステン、ニッケル及びこれらを含む合金から選択される金属を使用する。  In addition, a high temperature co-fired ceramic (HTCC) material can be used as the ceramic material. Examples of the high-temperature sintered ceramic material include alumina, aluminum nitride, mullite, and other materials added with a sintering aid such as glass and sintered at 1100 ° C. or higher. At this time, as the wiring pattern 12, the heat dissipating via-hole conductor 17, the heat dissipating continuous via-hole conductor 18 and the conductor film 19, for example, a metal selected from molybdenum, platinum, palladium, tungsten, nickel and alloys containing them is used.

次に、図２、図３を参照しながら本発明の多層配線基板の製造方法の一実施形態について説明する。
まず、低温焼結セラミック材料（例えば、Ａｌ２Ｏ３をフィラーとし、ホウ珪酸ガラスを焼結助材として含むセラミック材料）をビニルアルコール等のバインダ中に分散させてスラリーを調製した後、このスラリーをドクターブレード法等によって、図２の（ａ）に示すようにキャリアフィルム１００上に塗布して低温焼結用のセラミックグリーンシート１１１Ａを所定の大きさで作製する。セラミックグリーンシート１１１Ａは複数の多層配線基板１０が同時に作製される大きさである。尚、図２ではキャリアフィルム１００とセラミックグリーンシート１１１Ａを上下逆にして示してある。Next, an embodiment of a method for manufacturing a multilayer wiring board according to the present invention will be described with reference to FIGS.
First, a slurry is prepared by dispersing a low-temperature sintered ceramic material (for example, a ceramic material containing Al 2 O 3 as a filler and borosilicate glass as a sintering aid) in a binder such as vinyl alcohol. Is applied onto the carrier film 100 by a doctor blade method or the like as shown in FIG. 2A to produce a ceramic green sheet 111A for low-temperature sintering with a predetermined size. The ceramic green sheet 111A has such a size that a plurality of multilayer wiring boards 10 can be produced simultaneously. In FIG. 2, the carrier film 100 and the ceramic green sheet 111A are shown upside down.

次いで、ビアホール導体１５を設けるために、例えばＣＯ２レーザ光等のレーザ光をセラミックグリーンシート１１１Ａに照射してビアホール導体用の孔を所定のパターンで形成する。ビアホール導体１５は、セラミックグリーンシート１１１Ａを上下に貫通するビアホール導体であるため、ビアホール導体用孔を所定のパターンで形成した後、図３に示すように、このビアホール導体用孔に導電性ペーストを充填してビアホール導体部１１５を形成する。ビアホール導体部１１５を形成した後、導電性ペーストを印刷して所定のパターンでライン導体部１１４を形成し、ビアホール導体部１１５とライン導体部１１４を図３に示すように接続する。ここでは、放熱用ビアホール導体１７及び放熱用連続ビアホール導体１８を形成する場合について説明する。Next, in order to provide the via-hole conductor 15, for example, laser light such as CO 2 laser light is irradiated onto the ceramic green sheet 111A to form via-hole conductor holes in a predetermined pattern. Since the via-hole conductor 15 is a via-hole conductor that vertically penetrates the ceramic green sheet 111A, after forming via-hole conductor holes in a predetermined pattern, a conductive paste is applied to the via-hole conductor holes as shown in FIG. The via hole conductor portion 115 is formed by filling. After forming the via hole conductor 115, the conductive paste is printed to form the line conductor 114 with a predetermined pattern, and the via hole conductor 115 and the line conductor 114 are connected as shown in FIG. Here, the case where the heat dissipation via-hole conductor 17 and the heat dissipation continuous via-hole conductor 18 are formed will be described.

セラミックグリーンシート１１１Ａにビアホール導体用孔を形成する場合には、例えばキャリアフィルム１００側からレーザ光を照射してビアホール導体用孔を形成する方法と、グリーンシート１１１Ａ側からレーザ光を照射してビアホール導体用孔を形成する方法がある。  When forming via hole conductor holes in the ceramic green sheet 111A, for example, a method of forming via hole conductor holes by irradiating laser light from the carrier film 100 side, and via holes by irradiating laser light from the green sheet 111A side. There is a method of forming a conductor hole.

本実施形態では、キャリアフィルム１００側からレーザ光を照射する方法を用いる。そこで、この方法について図２の（ａ）〜（ｆ）に基づいて説明する。この方法では、図２の（ａ）に示すようにキャリアフィルム１００をレーザ光Ｌの光源側に向けて配置する。  In this embodiment, a method of irradiating laser light from the carrier film 100 side is used. Therefore, this method will be described with reference to FIGS. In this method, the carrier film 100 is disposed toward the light source side of the laser light L as shown in FIG.

次いで、図２の（ｂ）に示すようにレーザ光Ｌをキャリアフィルム１００に照射し、レーザ光Ｌをキャリアフィルム１００及びセラミックグリーンシート１１１Ａを貫通させて略逆円錐台状のビアホール導体用孔Ｈを形成する。引き続き、レーザ光Ｌを図２の（ｂ）に示す位置から右方へ移動させて放熱用連続ビアホール導体１８となる部分を形成する。レーザ光Ｌの移動距離は、加工後のビアホール導体用孔にレーザ光Ｌが部分的に掛かる程度の距離に予め設定しておく。レーザ光Ｌが移動する度にキャリアフィルム１００を貫通すると共にセラミックグリーンシート１１１Ａに逆円錐台状の孔Ｈを形成する。レーザ光Ｌを移動させる度に、同図に（ｃ）に示すようにキャリアフィルム１００及びセラミックグリーンシート１１１Ａを貫通する逆円錐台状の孔Ｈが連続する孔Ｈ’ができ、最終的には同図の（ｄ）に示すように筋状の孔Ｈ”ができる。  Next, as shown in FIG. 2B, the laser beam L is irradiated onto the carrier film 100, and the laser beam L is penetrated through the carrier film 100 and the ceramic green sheet 111A so as to have a substantially inverted frustoconical via hole conductor hole H. Form. Subsequently, the laser beam L is moved to the right from the position shown in FIG. 2B to form a portion that becomes the heat radiating continuous via-hole conductor 18. The moving distance of the laser beam L is set in advance to such a distance that the laser beam L is partially applied to the processed via-hole conductor hole. Each time the laser beam L moves, the carrier film 100 is penetrated and an inverted frustoconical hole H is formed in the ceramic green sheet 111A. Each time the laser beam L is moved, a hole H ′ in which an inverted frustoconical hole H passing through the carrier film 100 and the ceramic green sheet 111A is formed as shown in FIG. A streak-like hole H ″ is formed as shown in FIG.

この時、筋状の孔Ｈ”の加工上、セラミックグリーンシート１１１Ａの厚みが５〜２５０μｍ、キャリアフィルムの厚みが２５〜１００μｍであることが好ましい。これらの厚みが上記厚みより厚いと筋状のＨ”が形成し難くなる。筋状の孔Ｈ”の幅は、３０〜５００μｍの範囲が好ましい。３０μｍ未満では放熱効果が低下し、５００μｍを超えると筋状の孔Ｈ”内への導電性ペーストの充填が難しくなる。  At this time, it is preferable that the thickness of the ceramic green sheet 111A is 5 to 250 μm and the thickness of the carrier film is 25 to 100 μm in terms of processing of the streak-shaped holes H ″. H ″ is difficult to form. The width of the streak-shaped hole H ″ is preferably in the range of 30 to 500 μm. If it is less than 30 μm, the heat dissipation effect is reduced, and if it exceeds 500 μm, it becomes difficult to fill the conductive paste into the streak-shaped hole H ″.

然る後、キャリアフィルム１１１Ａ側からセラミックグリーンシート１１１Ａに形成された筋状の孔Ｈ”内に、ＡｇまたはＣｕを主成分とする導電性ペーストを充填し、余分な導電性ペーストをキャリアフィルム１００から除去して、図２の（ｅ）に示すように放熱用ビアホール導体部１１７及び放熱用連続ビアホール導体部１１８を連続して形成する。  Thereafter, a conductive paste mainly composed of Ag or Cu is filled into the streaky holes H ″ formed in the ceramic green sheet 111A from the carrier film 111A side, and the excess conductive paste is used as the carrier film 100. Then, as shown in FIG. 2E, the heat dissipating via-hole conductor 117 and the heat dissipating continuous via-hole conductor 118 are continuously formed.

そして、セラミックグリーンシート１１１Ａを上向きにし、導電性ペーストをスクリーン印刷法等により所定のパターンで印刷して放熱用ビアホール導体部１１７及び放熱用連続ビアホール導体部１１８を導体膜部１１９で被覆する。これによって放熱用ビアホール導体部１１７及び放熱用連続ビアホール導体部１１８が導体膜部１１９と一体化する。導体膜部１１９は、図１の（ｂ）に示すようにこれらのビアホール導体部１１７、１１８の周縁領域を含む広さに形成する。導体膜部１１９がビアホール導体部１１７、１１８と一体化することで、これらのビアホール導体部１１７、１１８が形成されたシートを取り扱う時にビアホール導体部１１７、１１８がセラミックグリーンシート１１１Ａから脱落することがなく、シートの取り扱いが容易になると共に不良品率の発生を防止することができる。キャビティ１０Ａを形成する部分のセラミックグリーンシートにはビアホール導体部やライン導体部を形成した後、キャビティ１０Ａの大きさに見合った孔を開けて、図３に示すようにキャビティ部分のセラミックグリーンシートを作製する。  Then, the ceramic green sheet 111A is faced upward, and the conductive paste is printed in a predetermined pattern by a screen printing method or the like to cover the heat radiating via-hole conductor portion 117 and the heat radiating continuous via-hole conductor portion 118 with the conductor film portion 119. As a result, the heat radiating via-hole conductor 117 and the heat radiating continuous via-hole conductor 118 are integrated with the conductor film 119. As shown in FIG. 1B, the conductor film portion 119 is formed in a size including the peripheral region of the via-hole conductor portions 117 and 118. By integrating the conductor film part 119 with the via-hole conductor parts 117 and 118, the via-hole conductor parts 117 and 118 may fall off the ceramic green sheet 111A when handling the sheet on which the via-hole conductor parts 117 and 118 are handled. In addition, the sheet can be easily handled and the generation of defective products can be prevented. After forming the via hole conductor portion and the line conductor portion in the ceramic green sheet of the portion forming the cavity 10A, a hole corresponding to the size of the cavity 10A is formed, and the ceramic green sheet of the cavity portion is formed as shown in FIG. Make it.

放熱用ビアホール導体部１１７、放熱用連続ビアホール導体部１１８、導体膜部１１９及び他のビアホール導体部やライン導体部が形成されたシートを所定枚数作製した後、これらのセラミックグリーンシート１１１Ａを図３に示すように下側から上方に向けて所定の順序で積層し、所定の圧力で圧着して生の積層体を作製する。  After a predetermined number of sheets on which heat-dissipating via-hole conductor portions 117, heat-dissipating continuous via-hole conductor portions 118, conductor film portions 119, and other via-hole conductor portions and line conductor portions are formed, these ceramic green sheets 111A are shown in FIG. Are laminated in a predetermined order from the lower side to the upper side, and are pressed by a predetermined pressure to produce a raw laminated body.

その後、個々の多層配線基板に分割するためのブレイク溝を生の積層体の表面に形成した後、生の積層体を１０５０℃以下の所定の温度で焼成して焼結体を得る。この焼結体にメッキ処理を施した後、第１、第２、第３の電子部品５１、５２、５３を搭載する。更に、焼結体をブレイク溝に従って分割することによって、第１、第２、第３の電子部品５１、５２、５３を搭載した本実施形態の多層配線基板１０を複数個同時に得ることができる。  Then, after forming a break groove for dividing into individual multilayer wiring boards on the surface of the raw laminate, the raw laminate is fired at a predetermined temperature of 1050 ° C. or lower to obtain a sintered body. After the sintered body is plated, the first, second, and third electronic components 51, 52, and 53 are mounted. Furthermore, by dividing the sintered body according to the break grooves, a plurality of multilayer wiring boards 10 of the present embodiment on which the first, second, and third electronic components 51, 52, and 53 are mounted can be obtained simultaneously.

以上説明したように本実施形態によれば、複数のセラミック層１１Ａを積層してなる積層体１１と、この積層体１１の側面に形成された端子電極１３と、を備え、更に、積層体１１に搭載される第１、第２、第３の電子部品５１、５２、５３に接続するために積層体１１の上面からその内部の複数のセラミック層１１Ａを貫通する放熱用ビアホール導体１７と、この放熱用ビアホール導体１７に接続され且つ積層体１１内で放熱用ビアホール導体１７と端子電極１３とを接続するように一つのセラミック層１１Ａ内で面方向にビア導体が連設されてなる連続ビアホール導体１８と、を備えているため、放熱用連続ビアホール１８の伝熱断面積が大きく、第１、第２、第３の電子部品５１、５２、５３からの熱を効率よく端子電極１３まで導き、端子電極１３から外部へ効率よく放熱することができる。例えば、放熱用ビアホール導体１７の直径が１００μｍ、放熱用連続ビアホール導体１８の幅が７５μｍ、セラミック層１１Ａの厚さが２５μｍの時、電子部品の温度が約６８℃まで低下した。これに対して、従来の印刷による導体パターンの場合には同一の電子部品でその温度が約８０℃であった。従って、本実施形態の場合には従来の場合よりも約１２℃温度が低下し、放熱特性が向上した。  As described above, according to the present embodiment, the laminated body 11 formed by laminating the plurality of ceramic layers 11A and the terminal electrode 13 formed on the side surface of the laminated body 11 are provided. A heat radiating via-hole conductor 17 penetrating from the upper surface of the multilayer body 11 through the plurality of ceramic layers 11A therein to connect to the first, second, and third electronic components 51, 52, and 53 mounted on A continuous via-hole conductor connected to the heat-dissipating via-hole conductor 17 and having via conductors connected in the plane direction in one ceramic layer 11A so as to connect the heat-dissipating via-hole conductor 17 and the terminal electrode 13 in the laminate 11. 18, the heat transfer cross-sectional area of the heat radiating continuous via hole 18 is large, and heat from the first, second, and third electronic components 51, 52, 53 is efficiently guided to the terminal electrode 13. It can be dissipated efficiently from the terminal electrode 13 to the outside. For example, when the diameter of the heat dissipating via-hole conductor 17 is 100 μm, the width of the heat dissipating continuous via-hole conductor 18 is 75 μm, and the thickness of the ceramic layer 11A is 25 μm, the temperature of the electronic component is reduced to about 68 ° C. On the other hand, in the case of the conductor pattern by the conventional printing, the temperature was about 80 degreeC with the same electronic component. Therefore, in this embodiment, the temperature is reduced by about 12 ° C. compared to the conventional case, and the heat dissipation characteristics are improved.

また、本実施形態によれば、セラミック層１１Ａの放熱用連続ビアホール導体１８が形成されている領域が導体膜１９によって被覆されているため、導体膜１９からも放熱することができ、更に放熱特性を向上させることができる。また、導電性ペーストによって放熱用ビアホール導体用孔及び放熱用連続ビアホール用孔からなる筋状の孔Ｈ”を被覆する導体膜部１１９をセラミックグリーンシート１１１Ａに形成するため、シートを取り扱う時に、ビアホール導体部１１７、１１８がセラミックグリーンシート１１１Ａから脱落することがなく、シートの取り扱いが容易になると共に不良品率の発生を防止することができる。  In addition, according to the present embodiment, since the region of the ceramic layer 11A where the heat radiating continuous via-hole conductor 18 is formed is covered with the conductor film 19, heat can also be radiated from the conductor film 19, and further, heat dissipation characteristics. Can be improved. In addition, since the conductive film portion 119 that covers the streaky hole H ″ including the heat radiating via hole conductor hole and the heat radiating continuous via hole hole is formed on the ceramic green sheet 111A with the conductive paste, The conductor portions 117 and 118 are not dropped from the ceramic green sheet 111A, and the sheet can be easily handled and the generation of defective products can be prevented.

また、本実施形態によれば、放熱用連続ビアホール導体１８は、セラミック層１１Ａを介して上下に配置されているため、必要に連続ビアホール導体１８を増やして放熱効率を高めることができる。また、放熱用ビアホール導体１７のセラミック層１１Ａでの軸芯方向の断面積が放熱用連続ビアホール導体１８のセラミック層１１Ａでの軸芯方向の断面積より大きく形成されているため、放熱用ビアホール導体１７に対して放熱用連続ビアホール導体１８を容易且つ確実に接続することができる。また、第１、第２、第３の電子部品５１、５２、５３の外部端子電極が上下面に露出した放熱用ビアホール導体１７に接続されているため、各電子部品の狭ピッチ化に対応することができる。また、積層体１１がキャビティ１０Ａを有するため、キャビティ１０Ａ内に第３の電子部品５３を搭載することができ、電子部品の集積度を高めることができる。また、多層配線基板１０が小型化してキャビティ１０Ａの周囲の桟部の幅が狭くなっても、放熱用連続ビアホール１８をキャビティ１０Ａ以外の部分で外部へ引き出すことができ、放熱効率を低下させることがない。  Moreover, according to this embodiment, since the continuous via-hole conductor 18 for heat dissipation is arrange | positioned up and down via 11 A of ceramic layers, the continuous via-hole conductor 18 can be increased as needed and heat dissipation efficiency can be improved. Further, since the cross-sectional area in the axial direction of the ceramic layer 11A of the heat radiating via-hole conductor 17 is formed larger than the cross-sectional area in the axial direction of the ceramic layer 11A of the radiating continuous via-hole conductor 18, the heat-radiating via-hole conductor The continuous via-hole conductor 18 for heat dissipation can be easily and reliably connected to 17. Further, since the external terminal electrodes of the first, second, and third electronic components 51, 52, and 53 are connected to the heat dissipating via-hole conductors 17 exposed on the upper and lower surfaces, the pitch of each electronic component can be reduced. be able to. Moreover, since the laminated body 11 has the cavity 10A, the third electronic component 53 can be mounted in the cavity 10A, and the degree of integration of the electronic components can be increased. Further, even when the multilayer wiring board 10 is downsized and the width of the crosspieces around the cavity 10A is narrowed, the heat radiating continuous via hole 18 can be drawn to the outside at a portion other than the cavity 10A, and the heat radiation efficiency is lowered. There is no.

第２の実施形態
本実施形態の多層配線基板１０Ａは、図４に示すように放熱用連続ビアホール導体１８Ａが第１の実施形態と異なること以外は第１の実施形態に準じて構成されている。従って、ここでは放熱用連続ビアホール導体１８Ａを中心に説明し、その他の部分には第１の実施形態と同一または相当部分には同一符号を付してその説明を省略する。Second Embodiment As shown in FIG. 4, the multilayer wiring board 10A of the present embodiment is configured according to the first embodiment except that the heat dissipating continuous via-hole conductor 18A is different from the first embodiment. . Therefore, here, the description will focus on the heat radiating continuous via-hole conductor 18A, and the other parts are the same as or equivalent to those in the first embodiment, and the description thereof is omitted.

本実施形態における放熱用連続ビアホール導体１８Ａは、図４に示すようにセラミック層１１Ａを貫通せず、セラミック層１１Ａの半分位の厚みに形成されている。この放熱用連続ビアホール導体１８Ａは、第１の実施形態と比較して使用金属量が少ないため、放熱量が少なくなる。従って、この放熱用連続ビアホール導体１８Ａは、第１の実施形態で使用される電子部品より放熱量が少ない場合に適用される。本実施形態でも放熱用連続ビアホール導体１８Ａが上下二段に渡って設けられているが、一段であっても良く、また、必要に応じて三段以上設けても良い。  As shown in FIG. 4, the heat dissipating continuous via-hole conductor 18 </ b> A in the present embodiment does not penetrate the ceramic layer 11 </ b> A and is formed to have a thickness about half that of the ceramic layer 11 </ b> A. The heat radiating continuous via-hole conductor 18A uses a smaller amount of metal compared to the first embodiment, so that the heat radiation amount is reduced. Therefore, the heat radiating continuous via-hole conductor 18A is applied when the heat radiation amount is smaller than that of the electronic component used in the first embodiment. In this embodiment, the continuous via-hole conductor 18A for heat dissipation is provided in two upper and lower stages, but it may be provided in one stage, or may be provided in three or more stages as necessary.

本実施形態の放熱用ビアホール導体１８Ａを形成する場合には、例えば図５の（ａ）〜（ｆ）に示すように形成する。セラミックグリーンシート１１１Ａは第１の実施形態と同一要領で作製する。そして、図５の（ａ）に示すようにセラミックグリーンシート１１１をレーザ光Ｌの光源側に向けて配置する。更に、図５の（ｂ）に示すようにレーザ光Ｌをセラミックグリーンシート１１１Ａに向けて照射し、レーザ光Ｌをセラミックグリーンシート１１１Ａ及びキャリアフィルム１００を貫通させて略逆円錐台状のビアホール導体用孔Ｈを形成する。引き続き、レーザ光Ｌの照射エネルギーを、セラミックグリーンシート１１１を貫通しない程度の照射エネルギーに小さくして、レーザ光Ｌを図５の（ｂ）に示す位置から右方へ移動させて、同図の（ｃ）に示すように断面が逆円錐台状の溝Ｐを形成する。最終的には同図の（ｄ）に示すように細長い溝Ｐ’が形成される。最後に照射エネルギーを元に戻してキャリアフィルム１００をも貫通する孔Ｈを形成する。  In the case of forming the heat radiating via-hole conductor 18A of the present embodiment, it is formed, for example, as shown in FIGS. The ceramic green sheet 111A is produced in the same manner as in the first embodiment. And the ceramic green sheet 111 is arrange | positioned toward the light source side of the laser beam L, as shown to (a) of FIG. Further, as shown in FIG. 5B, the laser light L is irradiated toward the ceramic green sheet 111A, and the laser light L is penetrated through the ceramic green sheet 111A and the carrier film 100 so as to have a substantially inverted truncated cone-shaped via hole conductor. A hole H is formed. Subsequently, the irradiation energy of the laser beam L is reduced to an irradiation energy that does not penetrate the ceramic green sheet 111, and the laser beam L is moved to the right from the position shown in FIG. As shown in (c), a groove P having an inverted truncated cone shape is formed. Eventually, an elongated groove P 'is formed as shown in FIG. Finally, the irradiation energy is returned to the original, and the hole H penetrating the carrier film 100 is formed.

次いで、同図の（ｅ）に示すように、これらのビアホール導体用孔Ｈ、溝Ｐ’内に導電性ペーストを充填し、放熱用ビアホール導体部１１７及び放熱用連続ビアホール導体部１１８Ａを形成し、更に同図に（ｆ）に示すようにセラミックグリーンシート１１１Ａ上に導電性ペーストをスクリーン印刷法等により所定のパターンで印刷して導体面部１１９を形成する。  Next, as shown in FIG. 5E, the via hole conductor hole H and the groove P ′ are filled with a conductive paste to form a heat radiating via hole conductor portion 117 and a heat radiating continuous via hole conductor portion 118A. Further, as shown in FIG. 5F, a conductive surface portion 119 is formed by printing a conductive paste on the ceramic green sheet 111A in a predetermined pattern by a screen printing method or the like.

後は第１の実施形態と同一の要領でビアホール導体部、ライン導体部を有する複数のセラミックグリーンシートを必要に応じて作製した後、これらのセラミックグリーンシートを積層し、所定の圧力で圧着して生の積層体を作製する。その後、個々の多層配線基板に分割するためのブレイク溝を生の積層体の表面に形成した後、生の積層体を１０５０℃以下の所定の温度で焼成して焼結体を得る。この焼結体にメッキ処理を施した後、焼結体を分割して本実施形態の多層配線基板１０Ａを複数個同時に得ることができる。  After that, a plurality of ceramic green sheets having via-hole conductor portions and line conductor portions are produced as necessary in the same manner as in the first embodiment, and then these ceramic green sheets are laminated and pressure-bonded at a predetermined pressure. To produce a raw laminate. Then, after forming a break groove for dividing into individual multilayer wiring boards on the surface of the raw laminate, the raw laminate is fired at a predetermined temperature of 1050 ° C. or lower to obtain a sintered body. After the sintered body is plated, the sintered body can be divided to obtain a plurality of multilayer wiring boards 10A of the present embodiment at the same time.

従って、本実施形態によれば、放熱用連続ビアホール導体１８Ａがセラミック層１１Ａを貫通していないため、放熱効率は低下するが、従来と比較すれば放熱効率は格段に向上する。  Therefore, according to the present embodiment, since the continuous via-hole conductor for heat dissipation 18A does not penetrate the ceramic layer 11A, the heat dissipation efficiency is lowered, but the heat dissipation efficiency is significantly improved as compared with the conventional case.

第３の実施形態
本実施形態の多層配線基板は、図６に示すようにセラミック層１１Ｂ及び放熱用連続ビアホール導体１８Ｂが第１の実施形態と異なること以外は第１の実施形態に準じて構成されている。従って、ここでは放熱用連続ビアホール導体１８Ｂを中心に説明し、その他の部分には第１の実施形態と同一または相当部分には同一符号を付してその説明を省略する。Third Embodiment As shown in FIG. 6, the multilayer wiring board according to the present embodiment is configured in accordance with the first embodiment except that the ceramic layer 11B and the heat radiating continuous via-hole conductor 18B are different from the first embodiment. Has been. Therefore, here, the description will focus on the heat radiating continuous via-hole conductor 18B, and the other parts are the same as or equivalent to those in the first embodiment, and the description thereof is omitted.

本実施形態では図６に示すように放熱用連続ビアホール導体１８Ｂが形成されたセラミック層１１Ｂが他のセラミック層１１Ａよりも薄く形成されている。この放熱用連続ビアホール導体１８Ｂはセラミック層１１Ｂを貫通して形成されている。このような構成により、第２の実施形態と同様の作用効果を期することができる。  In the present embodiment, as shown in FIG. 6, the ceramic layer 11B on which the heat radiating continuous via-hole conductor 18B is formed is formed thinner than the other ceramic layers 11A. The heat radiating continuous via-hole conductor 18B is formed so as to penetrate the ceramic layer 11B. With such a configuration, the same operational effects as those of the second embodiment can be expected.

尚、本発明は上記各実施形態に何等制限されるものではない。例えば、上記各実施形態では端子電極１３がビアホール導体を半分した形態になっているが、平板状の電極であっても良い。また、放熱用ビアホール導体１７は第１、第２、第３電子部品５１、５２、５３に直接接続されているが、スペース的に余裕があれば放熱用ビアホール導体１７の上端面に接続ランドとなる表面電極を設けても良い。図示してないがビアホール導体１５についても放熱用ビアホール導体１７と同様のことが云える。また、放熱用ビアホール導体や放熱用連続ビアホール導体は回路パターンとしても使用することができ、この場合には回路パターンの抵抗損失を低減することができる。また、上記実施形態では、連続ビアホール導体と端子電極が接続しているが、連続ビアホール導体を複数のシートを積層方向に貫通するビアホール導体を介して表面電極と接続しても良い。  The present invention is not limited to the above embodiments. For example, in each of the embodiments described above, the terminal electrode 13 has a form in which a via-hole conductor is halved, but a flat electrode may be used. Further, the heat dissipation via-hole conductor 17 is directly connected to the first, second, and third electronic components 51, 52, and 53. However, if there is a space, a connection land is connected to the upper end surface of the heat dissipation via-hole conductor 17. A surface electrode may be provided. Although not shown, the same applies to the via-hole conductor 15 as the heat-dissipating via-hole conductor 17. Further, the heat radiating via hole conductor and the heat radiating continuous via hole conductor can also be used as a circuit pattern, and in this case, the resistance loss of the circuit pattern can be reduced. Moreover, in the said embodiment, although the continuous via-hole conductor and the terminal electrode are connected, you may connect a continuous via-hole conductor with a surface electrode via the via-hole conductor which penetrates a some sheet | seat in the lamination direction.

本発明は、種々の電子部品を搭載するための多層配線基板として好適に利用することができる。  The present invention can be suitably used as a multilayer wiring board for mounting various electronic components.

Claims (19)

複数の基材層を積層してなる積層体と、この積層体の側面または下面に形成された端子電極と、を備えた多層配線基板であって、上記積層体に搭載される電子部品に接続するために上記積層体の一方及び／または他方の主面からその内部の上記複数の基材層のうち少なくとも一層を貫通するビアホール導体と、このビアホール導体と上記端子電極とに接続され、一つの上記基材層内で面方向に導体が連設されてなる連続ビアホール導体と、を備えたことを特徴とする多層配線基板。  A multilayer wiring board comprising a laminate formed by laminating a plurality of base material layers and a terminal electrode formed on a side surface or a lower surface of the laminate, and connected to an electronic component mounted on the laminate In order to do so, a via-hole conductor penetrating at least one of the plurality of base material layers inside one and / or the other main surface of the laminate is connected to the via-hole conductor and the terminal electrode. A multi-layer wiring board comprising: a continuous via-hole conductor in which conductors are continuously arranged in a plane direction in the base material layer. 上記連続ビアホール導体が同一の上記基材層に複数形成されていることを特徴とする請求項１に記載の多層配線基板。  The multilayer wiring board according to claim 1, wherein a plurality of the continuous via-hole conductors are formed on the same base material layer. 上記基材層の上記連続ビアホール導体が形成されている領域が導体膜によって被覆されていることを特徴とする請求項１または請求項２に記載の多層配線基板。  3. The multilayer wiring board according to claim 1, wherein a region of the base material layer where the continuous via-hole conductor is formed is covered with a conductor film. 上記導体膜は、複数の上記連続ビアホール導体に跨るように形成されていることを特徴とする請求項３に記載の多層配線基板。  4. The multilayer wiring board according to claim 3, wherein the conductor film is formed so as to straddle the plurality of continuous via-hole conductors. 上記導体膜は、上記連続ビアホール導体と電気的に導通していることを特徴とする請求項３または請求項４に記載の多層配線基板。  5. The multilayer wiring board according to claim 3, wherein the conductor film is electrically connected to the continuous via-hole conductor. 上記連続ビアホール導体は、少なくとも一つの上記基材層を介して上下に配置されていることを特徴とする請求項１〜請求項５のいずれか１項に記載の多層配線基板。  The multilayer wiring board according to any one of claims 1 to 5, wherein the continuous via-hole conductors are arranged above and below via at least one base material layer. 上記連続ビアホール導体は、他の基材層よりも薄い基材層に形成されていることを特徴とする請求項１〜請求項６のいずれか１項に記載の多層配線基板。  The multilayer wiring board according to claim 1, wherein the continuous via-hole conductor is formed in a base material layer thinner than the other base material layers. 上記連続ビアホール導体は、基材層を貫通することを特徴とする請求項１〜請求項６のいずれか１項に記載の多層配線基板。  The multi-layer wiring board according to claim 1, wherein the continuous via-hole conductor penetrates the base material layer. 上記連続ビアホール導体は、基材層を貫通しないことを特徴とする請求項１〜請求項６のいずれか１項に記載の多層配線基板。  The multilayer wiring board according to claim 1, wherein the continuous via-hole conductor does not penetrate the base material layer. 上記ビアホール導体の上記基材層での軸芯方向の断面積は、上記連続ビアホール導体の上記基材層での軸芯方向の断面積より大きく形成されていることを特徴とする請求項１〜請求項９のいずれか１項に記載の多層配線基板。  The cross-sectional area in the axial direction in the base material layer of the via-hole conductor is formed larger than the cross-sectional area in the axial direction in the base material layer of the continuous via-hole conductor. The multilayer wiring board according to claim 9. 上記電子部品の外部端子電極が上記積層体の主面に露出した上記ビアホール導体に接続されていることを特徴とする請求項１〜請求項１０のいずれか１項に記載の多層配線基板。Multilayer wiring board according to any one of claims 1 to 10 in which the external terminal electrodes of the upper Symbol electronic components is characterized in that it is connected to the via hole conductor exposed at the main surface of the laminate . 上記積層体は、一方の主面にキャビティを有することを特徴とする請求項１〜請求項１１のいずれか１項に記載の多層配線基板。  12. The multilayer wiring board according to claim 1, wherein the laminate has a cavity on one main surface. 上記基材層は、低温焼結セラミック材料からなることを特徴とする請求項１〜請求項１２のいずれか１項に記載の多層配線基板。  The multilayer substrate according to any one of claims 1 to 12, wherein the base material layer is made of a low-temperature sintered ceramic material. 複数の基材層を積層してなる積層体と、この積層体の側面に形成された端子電極と、を備えた多層配線基板を製造するに際し、
複数の基材層のうち少なくとも一層に、上記基材層を上下に貫通する貫通孔と、この貫通孔から複数連続する第２貫通孔または半貫通孔とを上記基材層の面方向へ延びるように形成する第１の工程と、
上記貫通孔、及び上記第２貫通孔または上記半貫通孔に導電性材料を充填することにより、ビアホール導体及び連続ビアホール導体を形成する第２の工程と、
を備えたことを特徴とする多層配線基板の製造方法。When producing a multilayer wiring board comprising a laminate formed by laminating a plurality of base material layers and a terminal electrode formed on a side surface of the laminate,
At least one of the plurality of substrate layers has a through-hole penetrating the substrate layer vertically and a plurality of second through-holes or semi-through holes extending from the through-hole in the surface direction of the substrate layer. A first step of forming
A second step of forming a via-hole conductor and a continuous via-hole conductor by filling the through-hole and the second through-hole or the semi-through-hole with a conductive material;
A method of manufacturing a multilayer wiring board, comprising: 上記導電性材料によって上記貫通孔、及び上記第２貫通孔または上記半貫通孔を被覆する導体膜を上記基材層上に形成する第３の工程を備えたことを特徴とする請求項１４に記載の多層配線基板の製造方法。  15. The method according to claim 14, further comprising a third step of forming, on the base material layer, a conductive film that covers the through hole and the second through hole or the half through hole with the conductive material. The manufacturing method of the multilayer wiring board as described. 上記第１の工程では、上記基材層にレーザを照射することにより、上記貫通孔、及び上記第２貫通孔または上記半貫通孔を形成することを特徴とする請求項１４または請求項１５に記載の多層配線基板の製造方法。  The said 1st process WHEREIN: The said through-hole and the said 2nd through-hole or the said half through-hole are formed by irradiating a laser to the said base material layer, The Claim 14 or Claim 15 characterized by the above-mentioned. The manufacturing method of the multilayer wiring board as described. 上記基材層は、キャリアフィルムによって支持されており、キャリアフィルム側からレーザを照射することにより、上記貫通孔を形成することを特徴とする請求項１４〜請求項１６のいずれか１項に記載の多層配線基板の製造方法。  The said base material layer is supported by the carrier film, and forms the said through-hole by irradiating a laser from the carrier film side, The any one of Claims 14-16 characterized by the above-mentioned. Manufacturing method of multilayer wiring board. 上記基材層は、キャリアフィルムによって支持されており、上記基材層側からレーザを照射することにより、上記貫通孔及び半貫通孔を形成することを特徴とする請求項１４〜請求項１６のいずれか１項に記載の多層配線基板の製造方法。  The said base material layer is supported by the carrier film, and forms the said through-hole and a half through-hole by irradiating a laser from the said base material layer side, The Claims 16-16 characterized by the above-mentioned. The manufacturing method of the multilayer wiring board of any one of Claims 1. 上記第１、第２の工程における基材層は、未焼成のセラミックシートであり、この基材層を含む未焼成の積層体を作製した後、上記未焼成の積層体を焼成する第４の工程を備えたことを特徴とする請求項１４〜請求項１８のいずれか１項に記載の多層配線基板の製造方法。  The base material layer in the first and second steps is an unfired ceramic sheet, and after producing an unfired laminate including the base material layer, a fourth firing is performed on the unfired laminate. The method for manufacturing a multilayer wiring board according to any one of claims 14 to 18, further comprising a step.
JP2009503965A 2007-03-09 2008-02-29 Multilayer wiring board and manufacturing method thereof Active JP5212359B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009503965A JP5212359B2 (en) 2007-03-09 2008-02-29 Multilayer wiring board and manufacturing method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007060765 2007-03-09
JP2007060765 2007-03-09
JP2009503965A JP5212359B2 (en) 2007-03-09 2008-02-29 Multilayer wiring board and manufacturing method thereof
PCT/JP2008/053609 WO2008111408A1 (en) 2007-03-09 2008-02-29 Multilayer wiring board and method for manufacturing the same

Publications (2)

Publication Number Publication Date
JPWO2008111408A1 true JPWO2008111408A1 (en) 2010-06-24
JP5212359B2 JP5212359B2 (en) 2013-06-19

Family

ID=39759351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009503965A Active JP5212359B2 (en) 2007-03-09 2008-02-29 Multilayer wiring board and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP5212359B2 (en)
WO (1) WO2008111408A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110945653A (en) * 2017-08-14 2020-03-31 Tdk电子股份有限公司 LED module

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013018172A1 (en) * 2011-07-29 2013-02-07 日本碍子株式会社 Multilayer sintered ceramic wiring board, and semiconductor package including wiring board
WO2014171403A1 (en) * 2013-04-17 2014-10-23 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device
JP5859678B1 (en) * 2014-05-30 2016-02-10 株式会社メイコー Method for manufacturing printed wiring board
CN107079592B (en) * 2014-09-30 2019-06-18 株式会社村田制作所 Multilager base plate
CN206976318U (en) 2014-11-21 2018-02-06 株式会社村田制作所 Module
CN111741592B (en) 2020-06-17 2021-09-21 珠海越亚半导体股份有限公司 Multilayer substrate and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154939A (en) * 1997-07-31 1999-02-26 Kyocera Corp Wiring board
JP2003197810A (en) * 2001-12-26 2003-07-11 Kyocera Corp Electronic component
JP2003347746A (en) * 2002-05-28 2003-12-05 Kyocera Corp Multilayer circuit board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952666U (en) * 1982-09-28 1984-04-06 富士通株式会社 Semiconductor device with three-dimensional multilayer structure
JP2005159039A (en) * 2003-11-26 2005-06-16 Kyocera Corp Circuit-forming laminate and circuit board
WO2007007451A1 (en) * 2005-07-12 2007-01-18 Murata Manufacturing Co., Ltd. Multilayer wiring board and fabrication method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154939A (en) * 1997-07-31 1999-02-26 Kyocera Corp Wiring board
JP2003197810A (en) * 2001-12-26 2003-07-11 Kyocera Corp Electronic component
JP2003347746A (en) * 2002-05-28 2003-12-05 Kyocera Corp Multilayer circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110945653A (en) * 2017-08-14 2020-03-31 Tdk电子股份有限公司 LED module

Also Published As

Publication number Publication date
JP5212359B2 (en) 2013-06-19
WO2008111408A1 (en) 2008-09-18

Similar Documents

Publication Publication Date Title
JP4748161B2 (en) Multilayer wiring board and manufacturing method thereof
US8139368B2 (en) Component-containing module
KR100277400B1 (en) Board and Ceramic Package
JP5212359B2 (en) Multilayer wiring board and manufacturing method thereof
JP6539992B2 (en) Printed circuit board, semiconductor device, method of manufacturing wired circuit board, method of manufacturing semiconductor device
US7684207B2 (en) Composite electronic component
US20080047136A1 (en) Laminate ceramic circuit board and process therefor
JP3266505B2 (en) Multilayer circuit board
JP2008294253A (en) Wiring board for packaging light emitting element
JP2008172113A (en) Wiring substrate
JP5842859B2 (en) Multilayer wiring board and module having the same
JP4752612B2 (en) Manufacturing method of circuit board with protruding electrode
JP2007251017A (en) Wiring substrate, multipartite wiring substrate, and manufacturing method thereof
JP2017059831A (en) Wiring board and manufacturing method of the same
JP2004056115A (en) Multilayer wiring board
JP4057843B2 (en) Multilayer circuit board
JP2005277163A (en) Wiring board
JP2006032442A (en) Multi-layer substrate and manufacturing method therefor
CN114747301B (en) Circuit board and method for manufacturing circuit board
KR100900671B1 (en) Method of forming conductive via for multilayer interconnection substrate
JP3188911B2 (en) Multilayer ceramic substrate, method of manufacturing the same, and semiconductor package
JP2007234662A (en) Multipiece wiring board
KR20090112937A (en) Manufacturing method of multi-layer substrate
TWI354531B (en)
JP2006041242A (en) Ceramic wiring board

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110802

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111003

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120515

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120711

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121023

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121220

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130129

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130211

R150 Certificate of patent or registration of utility model

Ref document number: 5212359

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160308

Year of fee payment: 3