JP3266505B2 - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JP3266505B2
JP3266505B2 JP12480496A JP12480496A JP3266505B2 JP 3266505 B2 JP3266505 B2 JP 3266505B2 JP 12480496 A JP12480496 A JP 12480496A JP 12480496 A JP12480496 A JP 12480496A JP 3266505 B2 JP3266505 B2 JP 3266505B2
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor element
conductor layer
mounting portion
laminated substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12480496A
Other languages
Japanese (ja)
Other versions
JPH09307238A (en
Inventor
貴紀 生田
勉 小田
忠 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP12480496A priority Critical patent/JP3266505B2/en
Publication of JPH09307238A publication Critical patent/JPH09307238A/en
Application granted granted Critical
Publication of JP3266505B2 publication Critical patent/JP3266505B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は各種の電子機器・電
子装置等の電子回路モジュール等における回路基板とし
て用いられる多層回路基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board used as a circuit board in electronic circuit modules and the like of various electronic devices and devices.

【0002】[0002]

【従来の技術】近年、各種の電子機器や電子装置等に対
して小型化・薄型化・高機能化等の要求が高まってお
り、それに伴って、それら機器や装置の電子回路モジュ
ールに用いられる回路基板にも小型化・薄型化・高密度
化ならびに高速信号処理に対応した高機能化が強く要求
されている。
2. Description of the Related Art In recent years, there has been an increasing demand for various electronic devices and electronic devices to be reduced in size, thickness, and functionality, and accordingly, electronic devices and electronic devices have been used for electronic circuit modules. There is also a strong demand for small, thin, high-density circuit boards as well as for high-performance signal processing.

【0003】そのような回路基板には一般にアルミナ等
のセラミック材料を主成分とする多層回路基板が用いら
れており、回路基板のより一層の小型化・高密度化を進
めるために、IC(集積回路)等の半導体素子を基板上
に直接搭載して実装するチップオンボード(COB)技
術を採用した多層回路基板が多用されるようになってき
た。
[0003] Such a circuit board generally uses a multilayer circuit board mainly composed of a ceramic material such as alumina. In order to further reduce the size and density of the circuit board, an integrated circuit (IC) is required. 2. Description of the Related Art A multilayer circuit board employing a chip-on-board (COB) technique for mounting a semiconductor element such as a circuit) directly on a board and mounting the semiconductor element on the board has been widely used.

【0004】一方、アルミナ(Al2 3 )等を主成分
としたセラミック材料は1400〜1650℃程度の高温で焼成
しなければならないことから、多層回路基板の内部に配
線パターンを形成するには高融点金属であるタングステ
ン(W)やモリブデン(Mo)を用いなければならかっ
た。ところが、これら高融点金属は比抵抗が高いため
に、それらを使用した配線パターンでは高速信号処理を
行なう電子回路を構成できないという問題点があった。
On the other hand, since a ceramic material mainly containing alumina (Al 2 O 3 ) must be fired at a high temperature of about 1400 to 1650 ° C., it is difficult to form a wiring pattern inside a multilayer circuit board. Tungsten (W) and molybdenum (Mo), which are high melting point metals, had to be used. However, since these high-melting metals have high specific resistance, there has been a problem that an electronic circuit for performing high-speed signal processing cannot be configured with a wiring pattern using them.

【0005】これに対して、ガラスフリットにアルミナ
等の無機フィラーを添加した基板材料から成る低温焼成
多層回路基板が提案され実用化されている。この低温焼
成多層回路基板では内部配線パターンの形成には金(A
u)系・銀(Ag)系・銅(Cu)系等の低融点で比抵
抗の小さい金属材料を用いることができ、それにより高
速信号処理を行なう回路基板が実現できるものとなるこ
とから、民生機器分野での実用化を図るべく小型化・高
密度化・低コスト化に向けての開発が進められている。
On the other hand, a low-temperature fired multilayer circuit board made of a substrate material obtained by adding an inorganic filler such as alumina to glass frit has been proposed and put into practical use. In this low-temperature fired multilayer circuit board, gold (A
u) -based, silver (Ag) -based and copper (Cu) -based metal materials having a low melting point and a small specific resistance can be used, thereby realizing a circuit board for high-speed signal processing. Development for miniaturization, higher density, and lower cost is being pursued for practical use in the consumer electronics field.

【0006】そして、回路基板に搭載される半導体素子
の発熱量が素子の小型化・高密度化・高電力化に伴って
増大したため、半導体素子搭載部の直下の回路基板内部
にその熱を伝導して放熱を促進するための熱伝導を目的
としたビアホール、すなわちサーマルビアホールを多数
設けることにより半導体素子の熱的破壊や信頼性劣化の
防止が図られてきた。
Since the amount of heat generated by the semiconductor element mounted on the circuit board has increased with the miniaturization, high density, and high power of the element, the heat is transferred to the inside of the circuit board immediately below the semiconductor element mounting portion. By providing a large number of via holes for the purpose of heat conduction for promoting heat radiation, that is, thermal via holes, thermal destruction of semiconductor elements and deterioration of reliability have been prevented.

【0007】そのようなサーマルビアホールを形成した
多層回路基板の例として、例えば実開平3−96075 号に
は、図5に断面図で示すような、集積回路1と、集積回
路1を搭載する多層プリント基板2と、多層プリント基
板2の部品面パターン3と裏面パターン4に接続する複
数本の導体孔(サーマルビアホール)5とを含み、集積
回路1が部品面パターン3に搭載され、集積回路1より
発生する熱が導体孔5を通して多層プリント基板2の内
層パターン6および裏面パターン4から放熱される集積
回路放熱実装構造が提案されている。なお、7は集積回
路1の放熱を兼ねた半田付け部分であり、裏面パターン
4と内層パターン6は通常電源パターンまたはアースパ
ターンとされる。これによれば、集積回路1の実装が簡
単になり、かつ実装面積が小さくできることによってさ
らに高密度実装が可能となる効果が得られるというもの
である。
As an example of a multilayer circuit board having such thermal via holes formed therein, for example, Japanese Utility Model Laid-Open No. 3-96075 discloses an integrated circuit 1 and a multilayer mounting the integrated circuit 1 as shown in a sectional view of FIG. The integrated circuit 1 includes a printed board 2, a plurality of conductor holes (thermal via holes) 5 connected to the component side pattern 3 and the back side pattern 4 of the multilayer printed board 2, and the integrated circuit 1 is mounted on the component side pattern 3. There has been proposed an integrated circuit heat dissipation mounting structure in which heat generated from the inner layer pattern 6 and the back surface pattern 4 of the multilayer printed circuit board 2 is radiated through the conductor holes 5. Reference numeral 7 denotes a soldered portion that also serves as heat dissipation of the integrated circuit 1, and the back surface pattern 4 and the inner layer pattern 6 are usually power supply patterns or ground patterns. According to this, the mounting of the integrated circuit 1 is simplified, and the effect that the mounting area can be reduced can be obtained by further reducing the mounting area.

【0008】[0008]

【発明が解決しようとする課題】従来の多層回路基板に
おいては、実開平3−96075 号に開示されたように、集
積回路1の搭載部となる多層プリント基板2の表面は従
来、集積回路1と多層プリント基板2とを電気的に接続
するために集積回路1の接合面積より大きな面積の導体
配線である部品面パターン3を配設し、その部品面パタ
ーン3により搭載部直下の多数の導体孔5を全て覆う構
造となっていた。そのため、集積回路1を搭載する際、
搭載位置近傍の多層プリント基板2表面の部品面パター
ン3やその近傍に別途形成した画像認識用のマーク(図
示せず)を画像認識して集積回路1の位置決めを行なう
必要があった。
In a conventional multilayer circuit board, as disclosed in Japanese Utility Model Application Laid-Open No. 3-96075, the surface of the multilayer printed board 2 on which the integrated circuit 1 is mounted is conventionally the same as the integrated circuit 1. A component surface pattern 3, which is a conductor wiring having an area larger than the bonding area of the integrated circuit 1, is provided to electrically connect the circuit board and the multilayer printed circuit board 2, and a large number of conductors immediately below the mounting portion are provided by the component surface pattern 3. The structure was such that all the holes 5 were covered. Therefore, when mounting the integrated circuit 1,
It is necessary to perform image recognition of the component surface pattern 3 on the surface of the multilayer printed circuit board 2 near the mounting position and an image recognition mark (not shown) separately formed in the vicinity thereof to position the integrated circuit 1.

【0009】一方、半導体素子(集積回路1)の超小型
化が進む中で多層回路基板における半導体素子搭載部に
形成されるサーマルビアホール(導体孔5)の形成密度
は限界に近くなってきており、その限られた形成密度の
サーマルビアホールを十分活かすためには半導体素子の
搭載精度を向上させる必要がある。
On the other hand, as the miniaturization of the semiconductor element (integrated circuit 1) progresses, the formation density of thermal via holes (conductor holes 5) formed in the semiconductor element mounting portion of the multilayer circuit board is approaching its limit. In order to make full use of the limited thermal density via holes, it is necessary to improve the mounting accuracy of the semiconductor element.

【0010】しかしながら、従来のように導体孔5がそ
の上に形成された部品用パターン3で覆われている場合
は、図6(a)に示すように集積回路1の直下に多数の
導体孔5を精度良く配置させるべく導体孔5に対する集
積回路1の位置決めを正確に行なうことが難しく、基板
2の製造上のバラツキや集積回路1の搭載精度のバラツ
キ等により、図6(b)に平面図で示すように、集積回
路1が導体孔5の配列からずれて搭載されるという問題
点があった。このような半導体素子の位置ずれは半導体
素子の放熱状態を悪化させ、最悪の場合には半導体素子
が最大定格ジャンクション温度を超えてしまうことから
半導体素子本来の性能が十分発揮されなくなり、その結
果、電子回路モジュールとしての機能を低下させてしま
うという問題点があった。
However, when the conductor hole 5 is covered with the component pattern 3 formed thereon as in the prior art, a large number of conductor holes are provided immediately below the integrated circuit 1 as shown in FIG. It is difficult to accurately position the integrated circuit 1 with respect to the conductor hole 5 in order to dispose the integrated circuit 5 with high accuracy. Due to variations in the manufacture of the substrate 2 and variations in the mounting accuracy of the integrated circuit 1, the plane shown in FIG. As shown in the figure, there is a problem that the integrated circuit 1 is mounted so as to be shifted from the arrangement of the conductor holes 5. Such misalignment of the semiconductor element deteriorates the heat radiation state of the semiconductor element, and in the worst case, the semiconductor element exceeds the maximum rated junction temperature, so that the original performance of the semiconductor element cannot be sufficiently exhibited. As a result, There is a problem that the function as an electronic circuit module is reduced.

【0011】なお、このような半導体素子とサーマルビ
アホールなどの熱伝導部材との位置ずれは、多層回路基
板の表層配線の位置ずれやサーマルビアホールの形成精
度・内部および表層の配線の位置精度・多層回路基板の
各層の積層精度などが積み重なる結果、無視できないも
のとなり、上記のような問題点となって現れてくるもの
である。
The positional deviation between such a semiconductor element and a thermal conductive member such as a thermal via hole is caused by the positional deviation of the surface wiring of the multilayer circuit board, the formation accuracy of the thermal via hole, the positional accuracy of the internal and surface wiring, and the multilayer structure. As a result of the lamination accuracy of each layer of the circuit board being accumulated, it cannot be ignored and appears as the above-mentioned problem.

【0012】本発明は、上記問題点に鑑みて本発明者が
鋭意研究を進めた結果完成したものであり、その目的
は、多層回路基板への半導体素子の搭載において、半導
体素子からの発熱をサーマルビアホールなどの熱伝導部
材に効率良く伝導させて放熱させるために、半導体素子
搭載部に多数配設した熱伝導部材を半導体素子の直下に
精度良く、かつ再現性良く配置させることができる多層
回路基板を提供することにある。
The present invention has been accomplished in view of the above problems and has been accomplished by the inventors of the present invention. The object of the present invention is to generate heat from the semiconductor element when mounting the semiconductor element on a multilayer circuit board. A multi-layer circuit that can accurately and reproducibly arrange a large number of heat conducting members arranged on the semiconductor element mounting part directly under the semiconductor element in order to efficiently conduct heat to heat conduction members such as thermal via holes and radiate heat. It is to provide a substrate.

【0013】[0013]

【課題を解決するための手段】本発明の請求項1に係る
多層回路基板は、複数の低温焼成セラミック層が積層さ
れて成る積層基板と、その積層基板の表面に形成され、
一部に半導体素子が搭載される搭載部導体層と、前記搭
載部導体層と対向する前記積層基板の裏面に形成された
裏面導体層と、前記半導体素子から発生する熱を伝導す
べく前記搭載部導体層の一部から半導体素子の搭載位置
の外周領域にわたり前記積層基板を貫通して配設され、
前記搭載部導体層と前記裏面導体層とを接続する複数個
の熱伝導部材とを具備する多層回路基板であって、前記
搭載部導体層に搭載される半導体素子の外側に位置する
少なくとも1つの前記熱伝導部材の端面を、前記積層基
板の表面の前記搭載部導体層の内側に前記搭載部導体層
と区画して露出させたことを特徴とするものである。
According to a first aspect of the present invention, there is provided a multilayer circuit board comprising a plurality of low-temperature fired ceramic layers stacked on each other, and a multilayer board formed on a surface of the multilayer board.
A mounting portion conductor layer on which a semiconductor element is partially mounted, a back surface conductor layer formed on the back surface of the laminated substrate facing the mounting portion conductor layer, and the mounting portion for conducting heat generated from the semiconductor element; Disposed through the laminated substrate from a part of the partial conductor layer to an outer peripheral region of a mounting position of the semiconductor element,
A multilayer circuit board comprising a plurality of heat conductive members for connecting the mounting portion conductive layer and the back surface conductive layer, wherein at least one of the plurality of heat conductive members is located outside a semiconductor element mounted on the mounting portion conductive layer. An end surface of the heat conduction member is exposed inside the mounting portion conductor layer on the surface of the laminated substrate by partitioning the mounting portion conductor layer.

【0014】また、本発明の請求項2に係る多層回路基
板は、上記の請求項1に係る多層回路基板において、前
記複数個の熱伝導部材の各々が、前記積層基板を形成す
る低温焼成セラミック層間に配した内層導体層を介して
接続されていることを特徴とするものである。
According to a second aspect of the present invention, there is provided the multilayer circuit board according to the first aspect, wherein each of the plurality of heat conducting members is formed of a low-temperature fired ceramic forming the laminated substrate. It is characterized by being connected via an inner conductor layer disposed between the layers.

【0015】さらに、本発明の請求項3に係る多層回路
基板は、上記の請求項2に係る多層回路基板において、
前記積層基板内の前記複数個の熱伝導部材が配設された
領域の外側に、複数個の補助熱伝導部材が、前記内層導
体層から前記裏面導体層にかけて低温焼成セラミック層
を貫通して配設されていることを特徴とするものであ
る。
Further, the multilayer circuit board according to the third aspect of the present invention is the multilayer circuit board according to the second aspect,
Outside the region in which the plurality of heat conducting members are provided in the laminated substrate, a plurality of auxiliary heat conducting members are arranged so as to penetrate the low-temperature fired ceramic layer from the inner conductor layer to the back conductor layer. It is characterized by being provided.

【0016】さらにまた、本発明の請求項4に係る多層
回路基板は、上記の請求項3に係る多層回路基板におい
て、少なくとも2層以上の内層導体層が配されるととも
に、各内層導体層と前記裏面導体層との間の前記補助熱
伝導部材の個数を、裏面導体層側に向かって、かつ、補
助熱伝導部材の配設された領域の外側に向かって増加さ
せていることを特徴とするものである。
Further, the multilayer circuit board according to a fourth aspect of the present invention is the multilayer circuit board according to the third aspect, wherein at least two or more inner conductor layers are provided, and The number of the auxiliary heat conductive member between the back heat conductive layer and the back heat conductive member is increased toward the back conductive layer side and outside the region where the auxiliary heat conductive member is provided. Is what you do.

【0017】本発明の多層回路基板によれば、半導体素
子から発生する熱を伝導すべく、半導体素子が搭載され
る搭載部導体層の一部から半導体素子の搭載位置の外周
領域にわたって積層基板を貫通して配設され、搭載部導
体層と裏面導体層とを接続する複数個の熱伝導部材のう
ち、搭載部導体層に搭載される半導体素子の外側に位置
する少なくとも1つの熱伝導部材の端面を積層基板の表
面の搭載部導体層の内側に搭載部導体層と区画して露出
させたことにより、その熱伝導部材の端面を目印として
搭載部導体層の下に配設された熱伝導部材の位置を把握
することができることから、例えば半導体素子の搭載位
置を決める際の画像認識用マークとして利用すること等
により、半導体素子搭載部に多数配設した熱伝導部材を
半導体素子の直下に精度良く、かつ再現性良く配置させ
るように、半導体素子を搭載することができる。その結
果、半導体素子からの発熱をそれら複数個の熱伝導部材
により効率良く伝導させて放熱させることができるよう
になり、半導体素子の温度上昇を所望通りに抑制するこ
とができて半導体素子本来の性能を十分発揮させ、電子
回路モジュールとしての機能を十分に維持できる高信頼
性の多層回路基板を提供することができる。
According to the multilayer circuit board of the present invention, in order to conduct heat generated from the semiconductor element, the laminated board extends from a part of the mounting portion conductive layer on which the semiconductor element is mounted to an outer peripheral area of the mounting position of the semiconductor element. At least one of the plurality of heat conducting members disposed to penetrate and connect the mounting portion conductor layer and the back surface conductor layer is located outside the semiconductor element mounted on the mounting portion conductor layer. By exposing the end face inside the mounting part conductor layer on the surface of the laminated substrate, the heat conduction member disposed under the mounting part conductor layer with the end face of the heat conducting member as a mark. Since the position of the member can be grasped, for example, by using it as an image recognition mark when deciding the mounting position of the semiconductor element, a large number of heat conductive members arranged in the semiconductor element mounting portion can be directly under the semiconductor element. Accuracy, and so as to cause reproducibly arrangement, it is possible to mount the semiconductor element. As a result, heat generated from the semiconductor element can be efficiently conducted and radiated by the plurality of heat conducting members, so that the temperature rise of the semiconductor element can be suppressed as desired, and the semiconductor element inherently has an increased temperature. It is possible to provide a highly reliable multilayer circuit board that can sufficiently exhibit performance and sufficiently maintain the function as an electronic circuit module.

【0018】なお、端面を露出させる熱伝導部材の個数
は少なくとも1つであれば本発明の作用効果は十分に奏
されるが、その個数を2つ以上とすれば、搭載される半
導体素子の角度補正をそれらの熱伝導部材の端面を利用
してより容易に行なうことができるため、本発明のより
好適な態様となる。この場合の端面を露出させる熱伝導
部材の位置関係について特に限定はなく、それらの位置
関係が予め明らかであればそれによって半導体素子の搭
載位置を正確に制御することができる。
The operation and effect of the present invention can be sufficiently obtained if the number of the heat conducting members for exposing the end face is at least one. Since the angle correction can be performed more easily by using the end faces of the heat conducting members, it is a more preferable embodiment of the present invention. In this case, there is no particular limitation on the positional relationship of the heat conducting members exposing the end faces, and if the positional relationship is clear in advance, the mounting position of the semiconductor element can be accurately controlled.

【0019】また、本発明の請求項2に係る多層回路基
板によれば、複数個の熱伝導部材の各々が積層基板を形
成する低温焼成セラミック層間に配した内層導体層を介
して接続されていることから、複数個の熱伝導部材によ
る熱伝導をその内層導体層を介してより効率的に行なう
ことができるものとなり、半導体素子からの発熱をさら
に効率良く放熱させることができるものとなる。
Further, according to the multilayer circuit board of the second aspect of the present invention, each of the plurality of heat conducting members is connected via the inner conductor layer disposed between the low-temperature fired ceramic layers forming the laminated board. Therefore, the heat conduction by the plurality of heat conducting members can be more efficiently conducted through the inner conductor layer, and the heat generated from the semiconductor element can be more efficiently radiated.

【0020】さらに、本発明の請求項3に係る多層回路
基板によれば、上記の請求項2に係る多層回路基板にお
いて、複数個の補助熱伝導部材が、複数個の熱伝導部材
が配設された領域の外側に内層導体層から裏面導体層に
かけて低温焼成セラミック層を貫通して配設されている
ことから、熱伝導部材の周囲の低温焼成セラミック層に
拡散した熱をそれら補助熱伝導部材によって効率良く裏
面導体層に伝導させることができるため、半導体素子か
らの発熱をさらに一層効率良く放熱させることができる
ものとなる。
Further, according to the multi-layer circuit board according to the third aspect of the present invention, in the multi-layer circuit board according to the second aspect, the plurality of auxiliary heat conductive members are provided with the plurality of heat conductive members. Since the low-temperature-fired ceramic layer is disposed outside the inner conductor layer and extends from the inner conductor layer to the back-surface conductor layer, the heat diffused into the low-temperature-fired ceramic layer around the heat conductive member is transferred to the auxiliary heat conductive member. As a result, the heat can be efficiently transmitted to the back conductor layer, so that the heat generated from the semiconductor element can be further efficiently radiated.

【0021】さらにまた、本発明の請求項4に係る多層
回路基板によれば、上記の請求項3に係る多層回路基板
において、少なくとも2層以上の内層導体層が配される
とともに、各内層導体層と裏面導体層との間の補助熱伝
導部材の個数を、裏面導体層側に向かって、かつ、補助
熱伝導部材の配設された領域の外側に向かって増加させ
ていること、すなわち、裏面導体層側に向けて補助熱伝
導部材を階段状あるいはピラミッド状に配設させている
ことから、半導体素子の搭載部から積層基板の裏面に向
かって熱伝導部材の周囲に次第に拡散するように低温焼
成セラミック層を伝導していく半導体素子からの発熱を
さらに効率良く裏面導体層に伝導させることができるた
め、半導体素子からの発熱をさらに一層効率良く安定し
て放熱させることができるものとなり、半導体素子の動
作や機能が極めて安定した高信頼性の多層回路基板とな
る。
Further, according to the multilayer circuit board according to the fourth aspect of the present invention, in the multilayer circuit board according to the third aspect, at least two or more inner-layer conductor layers are provided and each inner-layer conductor layer is provided. The number of the auxiliary heat conducting members between the layer and the back conductor layer is increased toward the back conductor layer and toward the outside of the region where the auxiliary heat conducting member is provided, that is, Since the auxiliary heat conductive member is arranged stepwise or pyramid-shaped toward the back conductor layer side, the auxiliary heat conductive member is gradually diffused around the heat conductive member from the mounting portion of the semiconductor element toward the back surface of the laminated substrate. Since the heat generated from the semiconductor element that conducts through the low-temperature fired ceramic layer can be more efficiently transmitted to the back conductor layer, the heat generated from the semiconductor element can be more efficiently and stably radiated. It shall be, operations and functions of the semiconductor device becomes very stable and highly reliable multilayer circuit board.

【0022】[0022]

【発明の実施の形態】以下、本発明の多層回路基板につ
いて図面を参照しながら詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer circuit board according to the present invention will be described in detail with reference to the drawings.

【0023】図1は本発明の多層回路基板の一実施形態
を示す半導体素子搭載部近傍の平面図であり、図2は図
1におけるA−A’線断面図である。これらの図におい
て、11は複数の低温焼成セラミック層12が積層されて成
る積層基板であり、その表面には半導体素子13がその一
部に搭載される搭載部導体層14が、また搭載部導体層14
と対向する裏面には裏面導体層15が形成されている。な
お、図1および図2においては半導体素子13を搭載する
ためのキャビティ11aを積層基板11の上面に形成した例
を示しているが、このキャビティ11aは必ずしも必要と
するものではなく、搭載部導体層14を積層基板11の最上
層の低温焼成セラミック層12の表面に設けて半導体素子
13を積層基板11の最表面に搭載するようにしたものであ
ってもよい。
FIG. 1 is a plan view showing the vicinity of a semiconductor element mounting portion showing one embodiment of the multilayer circuit board of the present invention, and FIG. 2 is a sectional view taken along line AA 'in FIG. In these figures, reference numeral 11 denotes a laminated substrate formed by laminating a plurality of low-temperature fired ceramic layers 12, on the surface of which a mounting portion conductor layer 14 on which a semiconductor element 13 is mounted on a part thereof, and a mounting portion conductor layer 14. Tier 14
A back surface conductor layer 15 is formed on the back surface opposite to. Although FIGS. 1 and 2 show an example in which the cavity 11a for mounting the semiconductor element 13 is formed on the upper surface of the laminated substrate 11, this cavity 11a is not always necessary, and A layer 14 is provided on the surface of the uppermost low-temperature fired ceramic layer 12 of the laminated substrate 11 to form a semiconductor device.
13 may be mounted on the outermost surface of the laminated substrate 11.

【0024】16は熱伝導部材であり、搭載部導体層14の
半導体素子13が搭載された一部から半導体素子13の搭載
位置の外周領域にわたり、積層基板11を貫通して、搭載
部導体層14と裏面導体層15とを接続するように、半導体
素子13から発生する熱を裏面導体層15に伝導すべく複数
個配設されている。これら複数個の熱伝導部材16は、搭
載される半導体素子13の寸法や発熱量・積層基板11の加
工精度などに応じて、最も効率よく放熱に寄与するよう
に、例えば格子状や千鳥状など、所定の位置精度を有し
て配設される。これら複数個の熱伝導部材16により裏面
導体層15に伝導された熱は、この多層回路基板が実装さ
れるマザーボードや放熱フィン等に伝えられて放熱され
る。
Reference numeral 16 denotes a heat conductive member, which extends from the portion of the mounting portion conductor layer 14 where the semiconductor element 13 is mounted to the outer peripheral region of the mounting position of the semiconductor element 13, penetrates the laminated substrate 11, and A plurality is provided so as to connect the heat generated from the semiconductor element 13 to the back conductor layer 15 so as to connect the back conductor layer 15 to the back conductor layer 15. Depending on the dimensions of the semiconductor element 13 to be mounted, the calorific value, the processing accuracy of the laminated substrate 11, and the like, the plurality of heat conductive members 16 may be, for example, in a lattice shape or a staggered shape so as to contribute to heat radiation most efficiently. , Are arranged with predetermined positional accuracy. The heat conducted to the back conductor layer 15 by the plurality of heat conducting members 16 is transmitted to a mother board, a radiating fin, or the like on which the multilayer circuit board is mounted, and is radiated.

【0025】そして、本発明の多層回路基板において
は、熱伝導部材16のうち搭載部導体層14上に搭載された
半導体素子13の外側に位置する少なくとも1つの熱伝導
部材16の端面を搭載部導体層14と区画して積層基板11の
表面の搭載部導体層14の内側に露出させたことが特徴で
あり、本形態においては、半導体素子13を挟んでほぼ対
角線上に配置された2つの熱伝導部材16aおよび16bの
端面を露出させた例を示している。
In the multilayer circuit board according to the present invention, the end face of at least one heat conductive member 16 located outside the semiconductor element 13 mounted on the mounting portion conductor layer 14 of the heat conductive member 16 is mounted on the mounting portion. It is characterized in that it is separated from the conductor layer 14 and is exposed inside the mounting portion conductor layer 14 on the surface of the laminated substrate 11. In this embodiment, two semiconductor elements 13 are arranged substantially diagonally across the semiconductor element 13. An example is shown in which the end surfaces of the heat conducting members 16a and 16b are exposed.

【0026】従って、これら熱伝導部材16aまたは16b
の端面を目印として搭載部導体層14の下に配設された複
数個の熱伝導部材16の位置を把握することができ、半導
体素子13の搭載位置を決める際の画像認識用マークとし
て熱伝導部材16aまたは16bの端面を利用することによ
り、半導体素子搭載部に多数配設した熱伝導部材16を半
導体素子13の直下に精度良く、かつ再現性良く配置させ
ることができて、半導体素子13からの発熱をそれら熱伝
導部材16により効率良く伝導させて放熱させることがで
きるものとなる。
Therefore, these heat conducting members 16a or 16b
The position of the plurality of heat conducting members 16 disposed under the mounting portion conductor layer 14 can be grasped by using the end surface of the semiconductor device 13 as a mark, and the heat conduction as an image recognition mark when determining the mounting position of the semiconductor element 13 can be understood. By using the end face of the member 16a or 16b, a large number of the heat conducting members 16 arranged on the semiconductor element mounting portion can be accurately arranged directly under the semiconductor element 13 with good reproducibility. The heat generated by the heat conduction member 16 can be efficiently conducted and radiated.

【0027】なお、図2においては本発明の請求項2に
係る多層回路基板の場合として、低温焼成セラミック層
12の間に内層導体層17を形成し、その内層導体層17を介
して熱伝導部材16が接続されている例を示している。本
発明の請求項1に係る多層回路基板においてはこの内層
導体層17は必ずしも必要としないが、その場合であって
も、熱伝導部材16に対する半導体素子13の位置決めが精
度良く行なえるとともに、それら熱伝導部材16により効
率良く放熱が行なわれることは言うまでもない。そし
て、内層導体層17を配した場合には、熱伝導部材16によ
る熱伝導をその内層導体層17を介してより効率的に行な
うことができるものとなる。
FIG. 2 shows a low-temperature fired ceramic layer as a multilayer circuit board according to a second aspect of the present invention.
An example is shown in which an inner conductor layer 17 is formed between layers 12, and a heat conductive member 16 is connected via the inner conductor layer 17. In the multilayer circuit board according to claim 1 of the present invention, the inner conductor layer 17 is not necessarily required, but even in such a case, the semiconductor element 13 can be accurately positioned with respect to the heat conducting member 16. It goes without saying that heat is efficiently dissipated by the heat conducting member 16. When the inner conductor layer 17 is provided, the heat conduction by the heat conducting member 16 can be performed more efficiently through the inner conductor layer 17.

【0028】また、本形態においては積層基板11の表面
ないしは内部に配設された種々の導体パターン18を示
し、一方、積層基板11の表面に実装される種々の実装部
品は図示していないが、これらは多層回路基板の仕様に
応じて適宜配設・実装されるものである。
Further, in the present embodiment, various conductive patterns 18 disposed on the surface or inside of the laminated substrate 11 are shown, while various mounted components mounted on the surface of the laminated substrate 11 are not shown. These are appropriately arranged and mounted according to the specifications of the multilayer circuit board.

【0029】19は半導体素子13の放熱を兼ねた導電性接
続部分であり、ロウ材やAu−Si・Au−Sn・Pb
−Sn等の金属接合剤、あるいはAg−エポキシ等の導
電性樹脂ペースト等の高熱伝導率材料が用いられる。そ
して、半導体素子13の各電極と搭載部導体層14や導体パ
ターン18等の回路パターン配線とはワイヤボンディング
などにより電気的に接続され、さらに必要に応じてモー
ルド樹脂などにより半導体素子13を樹脂封止して、所望
の電子回路モジュールが得られる。
Reference numeral 19 denotes a conductive connecting portion which also serves as heat radiation of the semiconductor element 13, and is made of brazing material, Au-Si, Au-Sn, Pb.
A high thermal conductivity material such as a metal bonding agent such as -Sn or a conductive resin paste such as Ag-epoxy is used. Then, each electrode of the semiconductor element 13 is electrically connected to circuit pattern wiring such as the mounting portion conductor layer 14 and the conductor pattern 18 by wire bonding or the like, and further, if necessary, the semiconductor element 13 is sealed with a molding resin or the like. Then, the desired electronic circuit module is obtained.

【0030】次に、本発明の多層回路基板の他の実施形
態について図3および図4を参照しながら詳細に説明す
る。
Next, another embodiment of the multilayer circuit board of the present invention will be described in detail with reference to FIGS.

【0031】図3は本発明の多層回路基板の他の実施形
態を示す半導体素子搭載部近傍の平面図であり、図4は
図3のB−B’線断面図である。
FIG. 3 is a plan view showing the vicinity of a semiconductor element mounting portion showing another embodiment of the multilayer circuit board of the present invention, and FIG. 4 is a sectional view taken along line BB 'of FIG.

【0032】図3および図4において、21は複数の低温
焼成セラミック層22が積層されて成る積層基板であり、
その表面には半導体素子23がその一部に搭載される搭載
部導体層24が、また搭載部導体層24と対向する裏面には
裏面導体層25が形成されている。なお、図3および図4
においても半導体素子23を搭載するためのキャビティ21
aを積層基板21の上面に形成した例を示しているが、前
述のように半導体素子23を積層基板21の最表面に搭載す
るようにしたものであってもよい。
3 and 4, reference numeral 21 denotes a laminated substrate formed by laminating a plurality of low-temperature fired ceramic layers 22;
A mounting portion conductor layer 24 on which the semiconductor element 23 is mounted on a part thereof is formed on the front surface, and a back surface conductor layer 25 is formed on the back surface facing the mounting portion conductor layer 24. 3 and 4
Cavity 21 for mounting the semiconductor element 23
Although the example in which “a” is formed on the upper surface of the laminated substrate 21 is shown, the semiconductor element 23 may be mounted on the outermost surface of the laminated substrate 21 as described above.

【0033】26は熱伝導部材であり、搭載部導体層24の
半導体素子23が搭載された一部から半導体素子23の搭載
位置の外周領域にわたり、積層基板21を貫通して、搭載
部導体層24と裏面導体層25とを接続するように、半導体
素子23から発生する熱を裏面導体層25に伝導すべく複数
個配設されている。これら複数個の熱伝導部材26も、搭
載される半導体素子23の寸法や発熱量・積層基板21の加
工精度などに応じて、最も効率よく放熱に寄与するよう
に、例えば格子状や千鳥状など、所定の位置精度を有し
て配設される。そして、熱伝導部材26のうち搭載部導体
層24上に搭載された半導体素子23の外側に位置する少な
くとも1つの熱伝導部材26の端面が搭載部導体層24と区
画して積層基板21の表面の搭載部導体層24の内側に露出
されており、本形態においては、半導体素子23を囲むよ
うにほぼ四角形状に配置された4つの熱伝導部材26a〜
26dの端面を露出させている。
Reference numeral 26 denotes a heat conducting member, which extends from a portion of the mounting portion conductor layer 24 on which the semiconductor element 23 is mounted to an outer peripheral region of the mounting position of the semiconductor element 23, penetrates the laminated substrate 21, and A plurality is provided so as to connect the heat generated from the semiconductor element 23 to the back conductor layer 25 so as to connect the back conductor layer 25 to the back conductor layer 25. Depending on the dimensions of the semiconductor element 23 to be mounted, the amount of heat generated, and the processing accuracy of the laminated substrate 21, the plurality of heat conductive members 26 may also be used, for example, in a lattice shape or a staggered shape so as to contribute to heat radiation most efficiently. , Are arranged with predetermined positional accuracy. The end surface of at least one heat conductive member 26 located outside the semiconductor element 23 mounted on the mounting portion conductor layer 24 of the heat conductive member 26 is separated from the mounting portion conductor layer 24 to form a surface of the laminated substrate 21. In the present embodiment, four heat conducting members 26a to 26c are arranged in a substantially square shape so as to surround the semiconductor element 23.
The end face of 26d is exposed.

【0034】従って、これら熱伝導部材26a〜26dの端
面を目印として搭載部導体層24の下に配設された複数個
の熱伝導部材26の位置を把握することができ、半導体素
子23の搭載位置を決める際の画像認識用マークとして熱
伝導部材26a〜26dの端面を利用することにより、半導
体素子搭載部に多数配設した熱伝導部材26を半導体素子
23の直下に精度良く、かつ再現性良く配置させることが
できて、半導体素子23からの発熱をそれら熱伝導部材26
により効率良く伝導させて放熱させることができるもの
となる。
Accordingly, the positions of the plurality of heat conductive members 26 disposed under the mounting portion conductor layer 24 can be grasped by using the end faces of the heat conductive members 26a to 26d as marks, and the mounting of the semiconductor element 23 can be grasped. By using the end surfaces of the heat conductive members 26a to 26d as image recognition marks when determining the position, the heat conductive members 26 provided in a large number on the semiconductor element mounting portion can be connected to the semiconductor element.
23 can be accurately and reproducibly disposed directly below the heat conduction member 26,
Thus, heat can be efficiently conducted and heat can be dissipated.

【0035】さらに、本形態においては、低温焼成セラ
ミック層22の間に内層導体層27を形成し、その内層導体
層27を介して熱伝導部材26が接続されているとともに、
複数個の補助熱伝導部材28が、複数個の熱伝導部材26が
配設された領域の外側に内層導体層27から裏面導体層25
にかけて低温焼成セラミック層22を貫通して配設されて
いる。これにより、熱伝導部材26による熱伝導をその内
層導体層27を介してより効率的に行なうことができると
ともに、熱伝導部材26の周囲の低温焼成セラミック層22
に拡散した熱をそれら補助熱伝導部材28によって効率良
く裏面導体層25に伝導させることができるため、半導体
素子23からの発熱をさらに一層効率良く放熱させること
ができるものとなる。
Further, in this embodiment, an inner conductor layer 27 is formed between the low-temperature fired ceramic layers 22, and a heat conducting member 26 is connected via the inner conductor layer 27.
A plurality of auxiliary heat conducting members 28 are disposed outside the region where the plurality of heat conducting members 26 are disposed from the inner conductor layer 27 to the back conductor layer 25.
The low temperature fired ceramic layer 22 is provided so as to pass through. As a result, the heat conduction by the heat conducting member 26 can be performed more efficiently via the inner conductor layer 27, and the low-temperature fired ceramic layer 22 around the heat conducting member 26 can be formed.
Since the heat diffused into the semiconductor element 23 can be efficiently conducted to the back conductor layer 25 by the auxiliary heat conducting member 28, the heat generated from the semiconductor element 23 can be radiated even more efficiently.

【0036】さらにまた、本形態においては、内層導体
層27が少なくとも2層以上配されるとともに、各内層導
体層27と裏面導体層25との間の補助熱伝導部材28の個数
を、裏面導体層25側に向かって、かつ、補助熱伝導部材
28の配設された領域の外側に向かって、階段状あるいは
ピラミッド状に増加させて配設している。これにより、
半導体素子23の搭載部から積層基板21の裏面に向かって
熱伝導部材23の周囲に次第に拡散するように低温焼成セ
ラミック層22を伝導していく半導体素子23からの発熱を
さらに効率良く裏面導体層25に伝導させることができる
ため、半導体素子23からの発熱をさらに一層効率良く安
定して放熱させることができるものとなる。
Furthermore, in the present embodiment, at least two or more inner conductor layers 27 are provided, and the number of auxiliary heat conducting members 28 between each inner conductor layer 27 and the back conductor layer 25 is determined by the number of back conductors. To the layer 25 side, and the auxiliary heat conducting member
It is arranged in a stepwise or pyramid-like manner outside the region where 28 are arranged. This allows
The heat generated from the semiconductor element 23 is conducted more efficiently through the low-temperature fired ceramic layer 22 so as to gradually diffuse from the mounting portion of the semiconductor element 23 toward the back surface of the laminated substrate 21 to the periphery of the heat conductive member 23. Since the heat can be conducted to the semiconductor device 25, heat generated from the semiconductor element 23 can be further efficiently and stably radiated.

【0037】そして、これら複数個の熱伝導部材16なら
びに補助熱伝導部材28により裏面導体層25に伝導された
熱は、この多層回路基板が実装されるマザーボードや放
熱フィン等に伝えられて放熱される。
The heat conducted to the back conductor layer 25 by the plurality of heat conducting members 16 and the auxiliary heat conducting members 28 is transmitted to a mother board, a radiating fin, and the like on which the multilayer circuit board is mounted and radiated. You.

【0038】なお、本形態においても積層基板21の表面
ないしは内部に配設された種々の導体パターン29を示
し、一方、積層基板21の表面に実装される種々の実装部
品は図示していないが、これらは多層回路基板の仕様に
応じて適宜配設・実装されるものである。
In the present embodiment, various conductor patterns 29 are shown on the surface of or inside the laminated substrate 21. On the other hand, various mounted components mounted on the surface of the laminated substrate 21 are not shown. These are appropriately arranged and mounted according to the specifications of the multilayer circuit board.

【0039】また、30は半導体素子23の放熱を兼ねた導
電性接続部分であり、前述の導電性接続部分19と同様の
高熱伝導率材料が用いられる。そして、半導体素子23の
各電極と搭載部導体層24や導体パターン29等の回路パタ
ーン配線とはワイヤボンディングなどにより電気的に接
続され、さらに必要に応じてモールド樹脂などにより半
導体素子23を樹脂封止して、所望の電子回路モジュール
が得られる。
Reference numeral 30 denotes a conductive connection portion which also serves as heat dissipation of the semiconductor element 23, and is made of the same high thermal conductivity material as the conductive connection portion 19 described above. Each electrode of the semiconductor element 23 is electrically connected to circuit pattern wiring such as the mounting portion conductor layer 24 and the conductor pattern 29 by wire bonding or the like, and the semiconductor element 23 is sealed with a molding resin or the like as necessary. Then, the desired electronic circuit module is obtained.

【0040】以上の各実施形態における各構成要素につ
き、多層回路基板の製造方法に従って説明する。
Each component in each of the above embodiments will be described according to a method of manufacturing a multilayer circuit board.

【0041】まず、例えばSiO2 およびAl2 3
MgO・ZnO・B2 3 ・PbOを主成分とするガラ
ス粉末55重量%と、無機フィラーとしてのAl2 3
末45重量%とを、バインダ・可塑剤および溶剤とともに
混練してスラリー状とする。
First, for example, SiO 2 and Al 2 O 3.
Glass powder 55% by weight consisting primarily of MgO · ZnO · B 2 O 3 · PbO, and Al 2 O 3 powder 45% by weight of the inorganic filler, the slurry was kneaded with binder plasticizer, and solvent I do.

【0042】このスラリーをドクターブレード法により
シート状に成形し、低温焼成セラミック層12・22を形成
するためのグリーンシートを作製する。
The slurry is formed into a sheet by a doctor blade method to produce a green sheet for forming the low-temperature fired ceramic layers 12 and 22.

【0043】所定のグリーンシートには各低温焼成セラ
ミック層12・22の層間の電気的導通を取るための導体パ
ターン18・29としてのビアホールならびに熱伝導部材16
・26としてのサーマルビアホールを形成するためのスル
ーホールをパンチング加工により設ける。
In predetermined green sheets, via holes as conductor patterns 18 and 29 for establishing electrical continuity between the low-temperature fired ceramic layers 12 and 22 and the heat conductive member 16 are provided.
-A through hole for forming a thermal via hole as 26 is provided by punching.

【0044】次に、グリーンシートのスルーホールに銀
系・金系・銅系等の導電性材料から成る導電性ペースト
をスクリーン印刷法等により充填する。この導電性ペー
ストは、例えば、粒径が 0.5〜5μmの銀粉末と、低熱
膨張性ガラスフリットと、バインダとしてのエチルセル
ロースと、溶剤としての2,2,4-トリメチル−1,3-ペンタ
ンジオールモノイソブチレートとを均質に混練したもの
である。
Next, a conductive paste made of a conductive material such as silver, gold, or copper is filled in the through holes of the green sheet by a screen printing method or the like. This conductive paste is, for example, a silver powder having a particle size of 0.5 to 5 μm, a low thermal expansion glass frit, ethyl cellulose as a binder, and 2,2,4-trimethyl-1,3-pentanediol monohydrate as a solvent. Isobutyrate is homogeneously kneaded.

【0045】次に、所定のグリーンシートの表面に同様
の導電性ペーストを用いて所望の搭載部導体層14・24お
よび裏面導体層15・25、内層導体層17・27、導体パター
ン18・29を印刷する。ここで、搭載部導体層13・23にお
いて端面を露出させる熱伝導部材16a・16b・26a〜26
dと区画される部分は、導体層を形成しないようなパタ
ーンに印刷される。
Next, using the same conductive paste on the surface of a predetermined green sheet, desired mounting portion conductor layers 14, 24 and back surface conductor layers 15, 25, inner conductor layers 17, 27, conductor patterns 18, 29 Print. Here, the heat conduction members 16a, 16b, 26a to 26a to expose the end surfaces of the mounting portion conductor layers 13, 23 are provided.
The portion defined as d is printed in a pattern that does not form a conductor layer.

【0046】なお、これらの導体層の材料となる導電性
ペーストは、前述のビアホール用導電性ペーストに含ま
れる低熱膨張性ガラスフリットに代えて、屈伏点が 700
〜850 ℃のガラスフリットを加えたものが用いられる。
このような導電性ペーストを用いれば、導電性ペースト
の焼結開始温度とグリーンシートの焼結開始温度とを近
接させることが可能となり、反りや変形のない低温焼成
セラミック層12・22から成る積層基板11・21が得られ
る。
The conductive paste used as the material of these conductor layers is a material having a sag point of 700 instead of the low thermal expansion glass frit contained in the conductive paste for via holes.
A glass frit of ~ 850 ° C is used.
By using such a conductive paste, the sintering start temperature of the conductive paste and the sintering start temperature of the green sheet can be made close to each other, and the lamination of the low-temperature fired ceramic layers 12 and 22 without warpage or deformation can be achieved. Substrates 11 and 21 are obtained.

【0047】次に、半導体素子13・23を搭載するための
キャビティ11a・21aを形成するため、所望の深さおよ
び面積になるように所定のグリーンシートを金型により
打ち抜き加工する。
Next, in order to form the cavities 11a and 21a for mounting the semiconductor elements 13 and 23, a predetermined green sheet is punched by a mold so as to have a desired depth and area.

【0048】次に、以上のグリーンシートを所定の順に
積層し、これを熱圧着して一体化した後、約 900℃の酸
化雰囲気中においてピーク時間を30分に設定して焼成す
ると、目的とする多層回路基板が得られる。
Next, after laminating the above green sheets in a predetermined order, integrating them by thermocompression bonding, firing in an oxidizing atmosphere at about 900 ° C. with a peak time of 30 minutes was performed. Is obtained.

【0049】さらに、半導体素子13・23を搭載部導体層
14・24に前述の高熱伝導率材料を用いて、搭載部導体層
14・24の内側に端面を露出させた熱伝導部材16a・16b
・26a〜26dを利用して搭載位置制御を行ない、位置決
めして接着接合させ搭載する。
Further, the semiconductor elements 13 and 23 are mounted on the conductive layer
Use the high thermal conductivity material described above for 14
Heat conducting members 16a and 16b with end faces exposed inside 14 and 24
The mounting position is controlled by using 26a to 26d, positioned, and bonded and mounted.

【0050】最後に、半導体素子13・23の各電極と搭載
部導体層14・24や導体パターン18・29等の回路パターン
配線とを電気的に接続するためのワイヤボンディングを
行ない、半導体素子13・23を樹脂封止するためのモール
ド樹脂を形成し、電子部品搭載用の端子電極と多層回路
基板の端子電極とを半田ペーストとリフロー炉等を用い
ることにより一般的な面実装型電子部品と同様にして電
気的に接続することで、本発明の多層回路基板から成る
所望の電子回路モジュールを得ることができる。
Finally, wire bonding is performed to electrically connect the electrodes of the semiconductor elements 13 and 23 with the circuit pattern wiring such as the conductor layers 14 and 24 and the conductor patterns 18 and 29. Forming a mold resin for resin sealing 23, and connecting the terminal electrodes for mounting electronic components and the terminal electrodes of the multilayer circuit board to a general surface mount type electronic component by using a solder paste and a reflow furnace. Similarly, by electrically connecting, a desired electronic circuit module including the multilayer circuit board of the present invention can be obtained.

【0051】そして、本発明の多層回路基板によれば、
その裏面導体層15・25が、基板が表面実装されるマザー
ボードの配線導体や放熱フィンなどに半田等の高熱伝導
材料で接続接着されることで、半導体素子13・23から発
生する熱が効率良く伝導されて放散され、半導体素子13
・23の熱的破壊あるいは信頼性の低下などを防止するこ
とが出来る。
According to the multilayer circuit board of the present invention,
The back conductor layers 15 and 25 are connected and bonded to the wiring conductors and radiating fins of the mother board on which the board is surface-mounted with a high heat conductive material such as solder, so that the heat generated from the semiconductor elements 13 and 23 can be efficiently used. Conducted and dissipated, the semiconductor element 13
・ Thermal destruction of 23 or a decrease in reliability can be prevented.

【0052】なお、本発明は以上の実施形態に限定され
るものではなく、本発明の要旨を逸脱しない範囲で種々
の変更・改良を加えることは何ら差し支えない。例え
ば、熱伝導部材としてのサーマルビアホールの形状を円
形の他にも四角形や楕円形等の種々の形状としてもよ
く、板状のものとしてもよい。また、熱伝導部材を露出
させるために搭載部導体層を区画する形状も種々の形状
としてよい。
The present invention is not limited to the above embodiment, and various changes and improvements can be made without departing from the scope of the present invention. For example, the shape of the thermal via hole as the heat conducting member may be various shapes such as a square or an ellipse other than a circle, or may be a plate. Further, various shapes may be used to define the mounting portion conductor layer in order to expose the heat conductive member.

【0053】[0053]

【発明の効果】以上のように、本発明の多層回路基板に
よれば、複数個の熱伝導部材のうち半導体素子の外側に
位置する少なくとも1つの熱伝導部材の端面を積層基板
の表面の搭載部導体層の内側に搭載部導体層と区画して
露出させたことにより、その熱伝導部材の端面を目印と
して半導体素子搭載の際の位置決め用の画像認識用マー
クとして利用すること等によって、半導体素子搭載部に
多数配設した熱伝導部材を半導体素子の直下に精度良
く、かつ再現性良く配置させることができる多層回路基
板を提供することができた。その結果、半導体素子から
の発熱をそれら複数個の熱伝導部材により効率良く伝導
させて放熱させることができるようになり、半導体素子
の温度上昇を所望通りに抑制することができて半導体素
子本来の性能を十分発揮させ、電子回路モジュールとし
ての機能を十分に維持できる高信頼性の多層回路基板を
提供することができた。
As described above, according to the multilayer circuit board of the present invention, the end face of at least one of the plurality of heat conducting members located outside the semiconductor element is mounted on the surface of the laminated substrate. By separating and exposing the mounting portion conductor layer inside the portion conductor layer, the semiconductor device can be used as an image recognition mark for positioning when mounting the semiconductor element using the end surface of the heat conductive member as a mark. A multi-layer circuit board can be provided in which a large number of heat conducting members arranged in the element mounting portion can be arranged accurately and reproducibly immediately below the semiconductor element. As a result, heat generated from the semiconductor element can be efficiently conducted and radiated by the plurality of heat conducting members, so that the temperature rise of the semiconductor element can be suppressed as desired, and the semiconductor element inherently has an increased temperature. It was possible to provide a highly reliable multilayer circuit board capable of sufficiently exhibiting performance and sufficiently maintaining the function as an electronic circuit module.

【0054】また、本発明の請求項2に係る多層回路基
板によれば、複数個の熱伝導部材の各々が内層導体層を
介して接続されていることから、上記に加えて熱伝導部
材による熱伝導をより効率的に行なうことができるもの
となり、半導体素子からの発熱をさらに効率良く放熱さ
せることができる多層回路基板を提供することができ
た。
According to the multilayer circuit board of the second aspect of the present invention, since each of the plurality of heat conductive members is connected via the inner conductor layer, in addition to the above, the heat conductive member is used. Heat conduction can be performed more efficiently, and a multilayer circuit board capable of more efficiently dissipating heat generated from a semiconductor element can be provided.

【0055】さらに、本発明の請求項3に係る多層回路
基板によれば、熱伝導部材の配設領域の外側に複数個の
補助熱伝導部材が配設されていることから、熱伝導部材
の周囲の低温焼成セラミック層に拡散した熱をそれら補
助熱伝導部材によって効率良く裏面導体層に伝導させる
ことができるため、上記に加えて半導体素子からの発熱
をさらに一層効率良く放熱させることができる多層回路
基板を提供することができた。
Further, according to the multilayer circuit board of the third aspect of the present invention, since a plurality of auxiliary heat conductive members are provided outside the area where the heat conductive member is provided, the heat conductive member has a plurality of auxiliary heat conductive members. Since the heat diffused into the surrounding low-temperature fired ceramic layer can be efficiently conducted to the backside conductor layer by the auxiliary heat conducting member, in addition to the above, the heat dissipation from the semiconductor element can be further efficiently dissipated. A circuit board could be provided.

【0056】さらにまた、本発明の請求項4に係る多層
回路基板によれば、各内層導体層と裏面導体層との間の
補助熱伝導部材の個数を、裏面導体層側に向かって、か
つ、補助熱伝導部材の配設された領域の外側に向かって
増加させて配設させたことから、半導体素子からの発熱
をさらに効率良く裏面導体層に伝導させて放熱させるこ
とができるものとなり、上記に加えてさらに半導体素子
の動作や機能が極めて安定した高信頼性の多層回路基板
を提供することができた。
Further, according to the multilayer circuit board of the fourth aspect of the present invention, the number of auxiliary heat conducting members between each inner conductor layer and the back conductor layer is increased toward the back conductor layer side, and Since it is arranged to be increased toward the outside of the area where the auxiliary heat conducting member is arranged, heat generated from the semiconductor element can be more efficiently conducted to the back conductor layer and radiated, In addition to the above, a highly reliable multilayer circuit board in which the operation and function of the semiconductor element are extremely stable can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層回路基板の一実施形態を示す平面
図である。
FIG. 1 is a plan view showing one embodiment of a multilayer circuit board of the present invention.

【図2】図1のA−A’線断面図である。FIG. 2 is a sectional view taken along line A-A 'of FIG.

【図3】本発明の多層回路基板の他の実施形態を示す平
面図である。
FIG. 3 is a plan view showing another embodiment of the multilayer circuit board of the present invention.

【図4】図3のB−B’線断面図である。FIG. 4 is a sectional view taken along line B-B ′ of FIG. 3;

【図5】従来の多層回路基板の構成を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing a configuration of a conventional multilayer circuit board.

【図6】(a)および(b)は半導体素子とサーマルビ
アホールとの位置ずれを説明する平面図である。
FIGS. 6A and 6B are plan views for explaining a positional shift between a semiconductor element and a thermal via hole.

【符号の説明】[Explanation of symbols]

11、21・・・積層基板 12、22・・・低温焼成セラミック層 13、23・・・半導体素子 14、24・・・搭載部導体層 15、25・・・裏面導体層 16、26・・・熱伝導部材 17、27・・・内層導体層 28・・・・・補助熱伝導部材 11, 21 ... Laminated substrate 12, 22 ... Low temperature fired ceramic layer 13, 23 ... Semiconductor element 14, 24 ... Mounting part conductor layer 15, 25 ... Backside conductor layer 16, 26 ...・ Heat conduction members 17, 27 ・ ・ ・ Inner conductor layer 28 ・ ・ ・ ・ ・ ・ Auxiliary heat conduction members

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−63372(JP,A) 特開 平7−321471(JP,A) 特開 平6−77347(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H01L 23/12 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-63372 (JP, A) JP-A-7-321471 (JP, A) JP-A-6-77347 (JP, A) (58) Field (Int.Cl. 7 , DB name) H05K 3/46 H01L 23/12

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 複数の低温焼成セラミック層が積層され
て成る積層基板と、該積層基板の表面に形成され、一部
に半導体素子が搭載される搭載部導体層と、前記搭載部
導体層と対向する前記積層基板の裏面に形成された裏面
導体層と、前記半導体素子から発生する熱を伝導すべく
前記搭載部導体層の一部から半導体素子の搭載位置の外
周領域にわたり前記積層基板を貫通して配設され、前記
搭載部導体層と前記裏面導体層とを接続する複数個の熱
伝導部材とを具備する多層回路基板であって、前記搭載
部導体層に搭載される半導体素子の外側に位置する少な
くとも1つの前記熱伝導部材の端面を、前記積層基板の
表面の前記搭載部導体層の内側に前記搭載部導体層と区
画して露出させたことを特徴とする多層回路基板。
1. A laminated substrate formed by laminating a plurality of low-temperature fired ceramic layers, a mounting portion conductive layer formed on a surface of the laminated substrate and partially mounting a semiconductor element, and the mounting portion conductive layer. A backside conductive layer formed on the backside of the opposing laminated substrate, and penetrating the laminated substrate from a part of the mounting portion conductive layer to an outer peripheral region of a mounting position of the semiconductor element to conduct heat generated from the semiconductor element. And a plurality of heat conducting members for connecting the mounting portion conductive layer and the back surface conductive layer, wherein the multilayered circuit board is provided outside the semiconductor element mounted on the mounting portion conductive layer. Wherein the end face of at least one of the heat conductive members located on the inner surface of the laminated substrate is exposed inside the mounting portion conductor layer on the surface of the laminated substrate while being partitioned from the mounting portion conductor layer.
【請求項2】 請求項1記載の多層回路基板において、
前記複数個の熱伝導部材の各々が、前記積層基板を形成
する低温焼成セラミック層間に配した内層導体層を介し
て接続されていることを特徴とする多層回路基板。
2. The multilayer circuit board according to claim 1, wherein
A multilayer circuit board, wherein each of the plurality of heat conducting members is connected via an inner conductor layer disposed between low-temperature fired ceramic layers forming the laminated substrate.
【請求項3】 請求項2記載の多層回路基板において、
前記積層基板内の前記複数個の熱伝導部材が配設された
領域の外側に、複数個の補助熱伝導部材が、前記内層導
体層から前記裏面導体層にかけて低温焼成セラミック層
を貫通して配設されていることを特徴とする多層回路基
板。
3. The multilayer circuit board according to claim 2, wherein
Outside the region in which the plurality of heat conducting members are provided in the laminated substrate, a plurality of auxiliary heat conducting members are arranged so as to penetrate the low-temperature fired ceramic layer from the inner conductor layer to the back conductor layer. A multilayer circuit board characterized by being provided.
【請求項4】 請求項3記載の多層回路基板において、
少なくとも2層以上の内層導体層が配されるとともに、
各内層導体層と前記裏面導体層との間の前記補助熱伝導
部材の個数を、裏面導体層側に向かって、かつ、補助熱
伝導部材の配設された領域の外側に向かって増加させて
いることを特徴とする多層回路基板。
4. The multilayer circuit board according to claim 3, wherein
At least two or more inner conductor layers are arranged,
The number of the auxiliary heat conducting members between each inner conductor layer and the back conductor layer is increased toward the back conductor layer and toward the outside of the region where the auxiliary heat conducting member is provided. A multi-layer circuit board, comprising:
JP12480496A 1996-05-20 1996-05-20 Multilayer circuit board Expired - Fee Related JP3266505B2 (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12480496A JP3266505B2 (en) 1996-05-20 1996-05-20 Multilayer circuit board

Publications (2)

Publication Number Publication Date
JPH09307238A JPH09307238A (en) 1997-11-28
JP3266505B2 true JP3266505B2 (en) 2002-03-18

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