JPWO2006090650A1 - Wafer processing method - Google Patents

Abstract

The problems of the present invention are that, in the conventional process, the wafer strength after wet polishing is reduced, the wafer support is thermally deteriorated, cracks are likely to occur when the polished wafer is peeled off from the support, and after thinning It is an object of the present invention to provide a wafer processing method that can solve problems such as difficulty in testing at the wafer level and can handle wafers having various and complicated structures. In the wafer processing method of the present invention, an adhesive composition containing a compound having a molecular weight of 5000 or less as a main component is interposed as a fixing agent between a wafer surface on which a semiconductor element is formed and a support, After the composition is heated and melted to bring the wafer and the support into close contact, the wafer and the support are bonded and fixed by cooling, the back surface of the wafer is polished and thinned to 20 to 100 μm, and the composition is heated. It melt | dissolves and peels a wafer and a support body, It is characterized by the above-mentioned.

Description

  The present invention relates to a series of wafer processing methods in which the back surface of a wafer having a semiconductor element formed on the front surface is polished to reduce the thickness of the wafer, and is divided into semiconductor chips and taken out. More specifically, by adopting an adhesive method that can firmly fix the wafer to the support even under high temperature conditions in the heat treatment during or after polishing, and can easily peel the wafer after processing. The present invention also relates to a wafer processing method capable of thinning a wafer to a thickness of 100 μm or less with respect to a wafer having an internal structure formed thereon or a large area wafer.

In order to meet the demand for higher performance and higher capacity of semiconductor chips, a technique for stacking and mounting a plurality of semiconductor chips has been developed and put into practical use. As such a technique, for example, a technique of stacking a plurality of memory chips can be cited, and as a result, the storage capacity can be increased as a whole.
As a technique for stacking a plurality of semiconductor chips in this way, for example, as described in Japanese Patent Application Laid-Open No. 2001-53218 (Patent Document 1), a through via structure is formed inside a wafer, and wiring between the chips is performed. There have been proposed a method of performing the above and a method of taking a wiring from an electrode pad at the periphery of the wafer with a gold wire and laminating.

Recently, memory capacity has increased rapidly, miniaturization, and functional integration have increased rapidly, and the number of stacked wafers has increased, and the stacking of 10 layers is approaching. In response to this, thinning of the wafer has progressed accordingly, and a thickness of 100 μm or less has been required for a 300 mmφ wafer.
The thinning of the wafer is performed in a series of steps in which the wafer surface is first protected and supported by a back grind tape, then ground and polished, then pasted on a dicing tape, and the wafer is cut into semiconductor chips. Yes.

  In a series of processes for making such wafers into semiconductor chips, the main point is now the process after wet grinding using abrasive grains, and the process of removing the grinding strain layer generated on the backside of the wafer is the main process. It is being considered. For example, a wet etching method that chemically etches the ground back surface using an etchant containing nitric acid and hydrofluoric acid, a dry etching method that uses an etching gas, and free abrasive grains on the back surface of a ground semiconductor wafer. Various attempts have been made, such as a polishing method in which polishing is performed and a method of dry polishing with a felt grindstone.

Further, when the stacking of semiconductor chips progresses in this way, whether the stacked semiconductor chips are non-defective or defective affects the yield of the stacked body. Since the influence of this yield increases according to the number of stacked layers, a testing process in which a semiconductor chip is determined to be good / bad before stacking is regarded as important.
In the conventional testing process, a method of individually testing each semiconductor chip has been the mainstream, but in recent years, a method of batch testing on a wafer basis has been proposed and put into practical use. However, in order to improve the yield of the laminated body, it is considered to be most effective to test immediately before the lamination, that is, after the thinning and dicing are completed. It is a difficult situation to test.
JP 2001-53218 A

The following points have been pointed out as problems in the conventional process in realizing further thinning of the semiconductor wafer.
(1) Only wet grinding in which grinding is performed using abrasive grains leaves fine scratches on the wafer, resulting in insufficient wafer strength after processing, and cracking during handling or chipping during dicing.
(2) Attempts have been made to remove the scratches (grind strain layer) made by wet grinding by dry polishing, but the wafer support may be thermally deteriorated by heat generated by dry polishing, particularly for large area wafers. Is remarkable.
(3) When the wafer after thinning is peeled from the support, the thinner the wafer, the worse the balance between the strength of the wafer itself and the adhesive strength with the support, and the more difficult it is to peel off and the easier it is to crack. This is particularly noticeable for large-area wafers because the area to be peeled off is large.
(4) Since testing at the wafer level cannot be performed after thinning, defects in thinning and dicing greatly affect the yield of the chip stack.

  Therefore, an object of the present invention is to provide a wafer thinning process that can solve the above-mentioned problems in the conventional process and can cope with wafers having various and complicated structures.

  The present inventors have intensively studied to solve the above problems. As a result, when the back surface of the roughly ground semiconductor wafer is polished and thinned to 20 to 100 μm, a composition containing a compound having a molecular weight of 1000 or less as a main component as a fixing agent is used. ) And the support, and found that the above problems can be solved by selecting materials and processes according to the temperature environment of the wafer, the dicing method, the wafer surface structure, and the required adhesion strength, etc. .

  For example, in the conventional method of thinning a wafer after thinning it using a dicing tape, a low melting point fixing agent that can be easily attached to the dicing tape is selected and used to remove the grinding strain layer. As a method, it is preferable to carry out by a reactive ion etching (RIE) method capable of controlling the temperature of the wafer, in addition to a CMP type wet polishing and chemical etching method in which the wafer temperature is not easily raised.

On the other hand, in the “tip dicing” method in which a cutting groove having a predetermined thickness is formed in advance before grinding, since the fixing agent is thoroughly impregnated into the cutting groove, the permeability is good and the melt viscosity is low. Select and use a fixative. In this case, since the fixing agent is also removed in the polishing step, CMP type wet polishing or physical polishing with a felt grindstone is preferable.
Similarly, if the wafer structure is complicated and has significant irregularities, specifically, a wafer with a via structure that penetrates in the film thickness direction, a wafer with a bump structure for wiring connection, etc., the permeability is the same. A fixing agent having a good melt viscosity and a low melt viscosity is preferred.

The present invention is based on the above findings, and is specifically as follows.
The wafer processing method according to the present invention contains, as a main component, a compound having a molecular weight of 1000 or less as a fixing agent for fixing the wafer and the support between the wafer surface on which the semiconductor element is formed and the support. After the adhesive composition is interposed, the composition is heated and melted to bring the wafer and the support into close contact, and then the wafer and the support are bonded and fixed by cooling, and the back surface of the wafer is polished and thinned. And the composition is heated and melted to separate the wafer and the support.

  The compound having a molecular weight of 1000 or less preferably has crystallinity. The compound having a molecular weight of 1000 or less is preferably a compound having a steroid skeleton and / or a hydroxyl group in the molecule or a derivative thereof. Furthermore, the compound having a molecular weight of 1000 or less preferably has a melting temperature of 50 to 300 ° C. and a melting temperature width of the composition of 30 ° C. or less.

In the wafer processing method according to the present invention, in the step of polishing the wafer back surface, the wafer can be thinned to 20 to 100 μm.
Further, when the adhesive strength at 25 ± 2 ° C. of the composition is A (MPa) and the adhesive strength at a temperature 20 ° C. lower than the melting temperature of the composition is B (MPa), the adhesive strengths A and B are It is preferable to satisfy the following formula (1).
0 <A-B <0.5 (MPa) (1)
The composition is preferably in the form of a tablet.

The wafer may have a semiconductor element formed in a region partitioned by a plurality of dicing streets on the surface, and cutting grooves may be formed in the dicing streets. In this case, it is thinned until the above-mentioned cutting groove is exposed, and is cut into semiconductor chips, and can be peeled from the support in units of the semiconductor chips.
The wafer is a wafer in which a hole having a predetermined depth is formed on the surface, the inner wall of the hole is covered with an insulating film, and a conductive electrode material is embedded in the hole covered with the insulating film. It may also have a protruding electrode for conduction.

The wafer may be a wafer on which at least one selected from a structure, a wiring, and an element is formed on the back surface.
In the wafer processing method of the present invention, after the wafer is thinned, the polished surface may be further processed to form at least one selected from a structure, a wiring, and an element.

ADVANTAGE OF THE INVENTION According to this invention, the processing method which grind | polishes the wafer back surface rough-ground and thins to 20-100 micrometers is provided, for example, the following effects are acquired.
(1) Since the heat resistance of the fixing agent is superior to the case of using a conventional tape support, the burden on the cooling mechanism during polishing is reduced.
(2) Since the hardness of the adhesive layer is high, chipping is small in dicing after wafer thinning.
(3) Since a hard support can be used, even a large area wafer is not warped, and the thinned wafer can be easily peeled off from the support.
(4) Since the crystalline composition used in the present invention has a very low melt viscosity, it is possible to follow the shape of a wafer having a complicated shape, and the thin thickness of the wafer having a complicated shape, which has been difficult with a conventional tape support. Can be realized.

It is a model figure of the wafer processing method performed in Example 1 of this invention. It is a SEM image of the solder bump formed in Example 2 of the present invention. It is a model figure of the wafer processing method performed in Example 2 of this invention. It is the model figure of the wafer used in Example 4 of this invention. It is the schematic which shows the measuring method of the adhesive strength in an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Wafer 2 ... Semiconductor element 3 ... SUS board | substrate 4 ... Fixing agent 5 ... Dry film resist 6 ... Through-hole 7 ... Solder bump 8 ... Cutting groove (80 micrometers) )
9 ... Glass substrate 10 ... Fixing agent 11 ... Insulating resin film 12 ... Wafer piece (3 mm square, 70 μm thick)
13: Wafer piece (5mm □, 70μm thickness)
14 ... Cutting groove 15 ... Via (50μm □, Depth 80μm)

Hereinafter, the wafer processing method according to the present invention will be described in detail.
In the wafer processing method of the present invention, the wafer surface on which the semiconductor element is formed and the support are bonded and fixed using a specific fixing agent, and the wafer back surface is ground and polished to reduce the thickness.
<Fixing agent>
The fixing agent used in the present invention is an adhesive composition containing, as a main component, a compound having crystallinity in order to impart cohesive force to the composition, preferably a tablet-like adhesive composition. Has a molecular weight of 1000 or less, preferably 150 to 800, more preferably 200 to 600. When the molecular weight of the compound exceeds the above range, the solubility of the compound in a solvent is lowered, and peeling / cleaning with the solvent may be insufficient.

The melting temperature of the above compound is 50 to 300 ° C, preferably 55 to 250 ° C, more preferably 100 to 200 ° C. Here, the melting temperature refers to a peak temperature in a main melting peak curve measured by a differential scanning calorimeter (DSC). When the melting temperature of the compound is in the above range, the heat-resistant temperature at the time of adhesion can be improved.
In addition, the above compound does not damage the wiring and insulating film formed on the semiconductor wafer, does not become a contamination source, and does not denature the adhesive when melted. It is a neutral compound that does not have an active functional group, and an alkali metal or the like that diffuses into the medium and adversely affects insulation properties (for example, Na, K, Ca, Fe, Cu, Ni, Cr, Al, etc.) It is desirable that the metal-free treatment be performed until the sum of the metal contents of) reaches 100 ppm or less, preferably 10 ppm or less. In addition, what is contained with a stable form, such as a metal oxide, is not this limitation.

  Examples of such compounds include nitro compounds such as 1,3,5-trinitrobenzene, 2,3,6-trinitrophenol, and 2,4,5-trinitrotoluene. From the viewpoints of high properties, excellent heat resistance during melting, and little coloration, an organic compound composed only of C, H, and O elements not containing an N element is preferable. Specific examples include aromatic compounds, aliphatic compounds, and alicyclic compounds as exemplified below.

  Examples of the aromatic compound include 9H-xanthene, benzofuran-3 (2H) -one, 1,5-diphenyl-2,4-pentadien-1-one, di-2-naphthyl ether, cis-1,8 -Terpine, 2,3-dimethylnaphthalene, 1,2-naphthalenediol, di-1-naphthylmethane, biphenyl-2,2'-diol, di-1-naphthyl ether, bis (diphenylmethyl) ether, 9,10 -Dihydroanthracene, 2,3,5,6-tetramethyl-p-benzoquinone, 2,6-dimethylnaphthalene, syringaldehyde, vanillyl alcohol, 1,3-diphenylisobenzofuran, 2,3'-dihydroxybenzophenone, Isohydrobenzoin, 4,4'-dimethylbiphenyl, 1,3-naphthalenediol, 4-phenanthrol, 3,3-diphenylphthalide, pentamethylphenol, hexaethylbenzene, 3,4-dihydroxybenzene Zophenone, 2,4-dihydroxybenzaldehyde, p-hydroxybenzophenone, 4,5,9,10-tetrahydropyrene, 2,3,4-trihydroxybenzophenone, hematoxylin, 2-isopropyl-5-methylhydroquinone, 1,9- Diphenyl-1,3,6,8-nonatetraen-5-one, 9-phenylfluorene, 1,4,5-naphthalenetriol, 1-anthrol, 1,4-diphenyl-1,3-butadiene, galvinoxyl, pyrene , 9-phenylanthracene, triphenylmethanol, 1,1′-binaphthyl, m-xylene-2,4,6-triol, 4,4′-methylenediphenol, hexamethylbenzene, dibenzo-18-crown-6, Diphenoquinone, biphenyl-4-ol, 1H-phenalene, 10-hydroxyanthrone, flavonol, benzoanthrone, 9H-xanthen-9-one, tetraphenylfuran 2-methylanthraquinone, 4-hydroxy-1-naphthaldehyde, 1,7-naphthalenediol, 2,5-diethoxy-p-benzoquinone, curcumin, 2,2′-binaphthyl, 1,8-dihydroxyanthraquinone, 1, 4-naphthalenediol, 1-hydroxyanthraquinone, 3,4-dihydroxyanthrone, o-terphenyl, m-terphenyl, p-terphenyl, 4,4'-dihydroxybenzophenone, anthracene, 2,4,6-trihydroxy Acetophenone, 1,8-anthracenediol, tetraphenylethylene, 1,7-dihydroxy-9-xanthenone, 2,7-dimethylanthracene, epicatechin, naringenin, 2-anthrol, 1,5-naphthalenediol, benzylidenephthalide 2-phenylnaphthalene, cis-decahydro-2-naphthol (cisoid), (2R, 3R) -2,3-bis (diphenylphosphino) Tan, trans-1,2-dibenzoylethylene, trans-1,4-diphenyl-2-butene-1,4-dione, bis (2-hydroxyethyl) terephthalate, fluoranthene, biphenylene, isovanillin, fluorene, 9-ant Roll, p-phenylene diacetate, trans-stilbene, biphenyl-3,3'-diol, 2,5-dihydroxybenzophenone, pinol hydrate, benzoin, hydrobenzoin, 1,2-bis (diphenylphosphino) ethane, 2,4-dihydroxybenzophenone, 1,8-naphthalenediol, 1,2-naphthoquinone, 2,4'-dihydroxybenzophenone, 5-hydroxy-1,4-naphthoquinone, 1-phenanthrol, anthrone, 9-fluorenol, tri Phenylphosphine oxide, benzo [a] anthracene, 1,2-anthracenediol, 2,3-naphthalenediol, 2, 4, 6 -Trihydroxybenzophenone, di-2-naphthyl ketone, 3,3'-dihydroxybenzophenone, arbutin, 1,2,3,5-benzenetetraol, diphenylquinomethane, 2-phenanthrol, 2,3,4-tri Hydroxyacetophenone, capsanthin, 1,3,5-triphenylbenzene, 3,4,5-trihydroxybenzophenone, benzo [a] pyrene, triphenylmethyl peroxide, hexestrol, 1,1,2,2-tetraphenyl -1,2-ethanediol, 1,8-dihydroxy-3-methylanthraquinone, camphorquinone, 2,2 ', 5,6'-tetrahydroxybenzophenone, esculin, 3,4'-dihydroxybenzophenone, 2,4, 5-trihydroxyacetophenone, 9,10-phenanthrenequinone, 1,1,2,2-tetraphenylethane, rutin, (-)-hesperetin, 2,3 ', 4 4 ', 6-pentahydroxybenzophenone, 7-hydroxycoumarin, dl-hesperetin, ninhydrin, triptycene, fluorescein, chrysene, diethylstilbestrol, dibenzo [a, h] anthracene, pentacene, 1,6-dihydroxyanthraquinone, 3, 4 ', 5,7-tetrahydroxyflavone, 2,6-anthracenediol, genistein and the like can be mentioned.

  Examples of the aliphatic compound include ribitol, D-arabitol, furyl, γ-carotene, β-carotene, cantharidin, pentaerythritol, trans, trans-1,4-diacetoxybutadiene, D-glucitol, D-mannitol, Idose, decanal, α-carotene, 2,4,6-trimethylphloroglucinol, galactitol, echrin, echilenin, trans-1,2-cyclobentanediol, manol, 1-heptadecanol, 1-octadecanol, Examples include 1-icosanol, dihydroxyacetone, γ-terpineol, 1-hexacosanol, 1-hentriacontanol and stearone.

  Examples of the alicyclic compounds include coprostanol, thymosterol, ergocalciferol, β-sitosterol, lanosterol, 11-deoxycorticosterone, cholestanol, cholesterol, testosterone, ergosterol, stigmasterol, estradiol, cortisyl Costerone, epicholestanol, androsterone, 17α-hydroxy-11-deoxycorticosterone, gitoxigenin, epicoprostanol, calciferol, progesterone, dehydroepiandrosterone, 7-dehydrocholesterol, agnosterol, 11-dehydrocorticostero , Prednisolone, digitoxigenin, estrone, β-estradiol, cortisone, D-fructose (α form), D-lyxose (α form), D-lyxose (β form), Somaltose, D-talose (beta form), D-talose (alpha form), D-allose (beta form), D-mannose (beta form), D-mannose (alpha form), D-xylose (alpha form) D -Galactose (beta form), L-fucose (alpha form), D-glucose (alpha form), 2-deoxy-D-glucose, maltotriose, D-altro-heptulose, L-arabinose (pyranose alpha form), D-arabinose, cafestall, L-arabinose (pyranose β form), D-galactose (alpha form), lycopene, aucbin, sucrose, freedelin, cis-1,3,5-cyclohexanetriol, D-inositol, lutein, diosgenin , Tigogenin, zeaxanthin, myo-inositol, cellobiose, gibberellin A3, hematein, betulin, D-fructose (β form), D-altrose (β form), dibenzo-24-crown-8, methyl-D-glucopyranoside (β Form), D-digitalose, Rinomycin, methyl-D-galactopyranoside (α form), α, α-trehalose, bixin (all trans form), palatinose, trans-1,4-terpine, D-quinoboose (α form), D-glycero- D-galacto-heptose, D-fucose (α form), D-glucose (β form), D-manno-heptulose, D-glycero-D-gluco-heptose, sophorose, salsasapogenin, L-sorbose, D- altro-3-heptulose, twistin, (+)-borneol, inositol, (-)-isoborneol, L-arabinose (furanose form), L-galactose (alpha form), alpha-santonin, methyl-D-galactopyrano Examples thereof include side (β form), cyclopentadecanone, δ-valerolactone, cis-2-methylcyclohexanol, and compounds represented by the following chemical formulas (1) to (8).

  Among the above compounds, from the viewpoint of tablet processability, cholesterol, coprostanol, timosterol, ergocalciferol, β-sitosterol, lanosterol, 11-deoxycorticosterone, cholestanol, testosterone, ergosterol, stigmasterol, Estradiol, corticosterone, epicholestanol, androsterone, 17α-hydroxy-11-deoxycorticosterone, gitoxigenin, epicoprostanol, calciferol, progesterone, dehydroepiandrosterone, 7-dehydrocholesterol, agnosterol, 11- Dehydrocorticosterone, prednisolone, digitoxigenin, estrone, β-estradiol, cortisone, and compounds represented by the above chemical formulas (1) to (8) Which compound has a steroid skeleton; trans-1,2-cyclobentanediol, manol, 1-heptadecanol, 1-octadecanol, 1-icosanol, γ-terpineol, 1-hexacosanol, 1-hentriacontanol Particularly preferred are hydroxyl group-containing compounds such as: and derivatives thereof, o-terphenyl, m-terphenyl, p-terphenyl, and biphenyl. An ester derivative is not preferable because it has a low melting point and may become acidic when thermally decomposed and may erode the adhesive surface.

The above compounds may be used alone or in combination of two or more, and the content in the adhesive composition is 70% by weight or more, preferably 80% by weight or more, particularly preferably 90% by weight. It uses so that it may become above. When the content is lower than the above range, the melting temperature may not be sharp and the melt viscosity may be increased.
The adhesive composition containing the above compound as a main component has a melting temperature range of 1 to 30 ° C., preferably 1 to 20 ° C., particularly preferably 1 to 10 ° C., and the melting temperature of the composition. The melt viscosity in is 0.0001 to 0.1 Pa · s, preferably 0.001 to 0.05 Pa · s, particularly preferably 0.001 to 0.01 Pa · s. Here, the melting temperature range refers to the difference between the temperature at the start point and the temperature at the end point in the main melting peak curve measured by a differential scanning calorimeter (DSC). When the melting temperature range and the melt viscosity are in the above ranges, the external force applied when the wafer is peeled from the support can be reduced, and the ease of peeling is improved.

  Since the melting temperature range and melt viscosity of the composition strongly depend on the melting temperature range and melt viscosity of the compound, it is desirable to use a compound having a narrow melting temperature range and a low melt viscosity. That is, the compound as the main component is preferably a compound having a melting temperature of 50 to 300 ° C., a melting temperature width of 1 to 30 ° C., and a melt viscosity at the melting temperature of 0.0001 to 0.1 Pa · s.

In addition, it is preferable to purify the compound in order to narrow the melting temperature range of the compound, reduce the melt viscosity, and further reduce the amount of free metal ions. As a method for purifying a compound, for example,
(A) A method in which the compound is dissolved in a solvent, and the purity is increased by gradually distilling off the solvent and recrystallization, and (b) the compound is dissolved in the solvent and the solution is brought into contact with an ion exchange resin. Examples include a method of reducing the metal content by removing free metal.

In the fixing agent used in the present invention, in order to adjust the wettability and adhesion to the substrate, or to adjust the melt viscosity of the adhesive composition, to improve the tableting processability of the composition, If necessary, a surface tension adjusting agent such as a nonionic surfactant and a release agent can be added within a range that does not impair the intended function.
Examples of the nonionic surfactant that can be added include a fluorine-based surfactant having a fluorinated alkyl group such as a perfluoroalkyl group, and a polyether alkyl-based surfactant having an oxyalkyl group. A silicone releasing agent can be used as the releasing agent.

Examples of the fluorosurfactant include C ₉ F ₁₉ CONHC ₁₂ H ₂₅ , C ₈ F ₁₇ SO ₂ NH— (C ₂ H ₄ O) ₆ H, “F-top EF301, EF303, and EF352” ( Shin-Akita Kasei Co., Ltd.), “Megafac F171, F173” (Dainippon Ink Co., Ltd.), “Asahi Guard AG710” (Asahi Glass Co., Ltd.), “Florard FC-170C, FC430,” “FC431” (manufactured by Sumitomo 3M), “Surflon S-382, SC101, SC102, SC103, SC104, SC105, SC106” (manufactured by Asahi Glass Co., Ltd.), “BM-1000, 1100” "(Manufactured by B.M-Chemie)", "Schseggo-Fluor" (manufactured by Schwegmann), "FS1265" (Toray Dow Corning Siri) Corn) and the like.

  Examples of the polyether alkyl surfactant include polyoxyethylene alkyl ether, polyoxyethylene allyl ether, polyoxyethylene alkyl phenyl ether, polyoxyethylene fatty acid ester, sorbitan fatty acid ester, polyoxyethylene sorbitan fatty acid ester, oxy An ethylene oxypropylene block polymer etc. are mentioned. Specifically, “Emulgen 105, 430, 810, 920”, “Leodol SP-40S, TW-L120, Emanol 3199, 4110”, “Exel P-40S, Bridge 30, 52” 72, 92 ”,“ Alassell 20, Emazole 320, Tween 20, 60, Merge 45 ”(above, manufactured by Kao Corporation),“ Noniball 55 ”(manufactured by Sanyo Chemical Co., Ltd.),“ SH-28PA, Commercially available products such as “-190, -193, SZ-6032, SF-8428” (manufactured by Toray Dow Corning Silicone Co., Ltd.) can be used.

  Nonionic surfactants other than the above include, for example, polyoxyethylene fatty acid esters, polyoxyethylene sorbitan fatty acid esters, polyalkylene oxide block copolymers, and the like. Specifically, “Chemistat 2500” (Sanyo Kasei) Kogyo Co., Ltd.), “SN-EX9228” (San Nopco Co., Ltd.), “Nonal 530” (Toho Chemical Co., Ltd.), and other commercial products can be used.

In addition, low-volatility such as dimethyl silicone oil KF965 (manufactured by Shin-Etsu Chemical), SH200 (manufactured by Toray Dow Silicone), methylphenyl silicone oil KF54, KF50 (manufactured by Shin-Etsu Chemical) Thus, silicone oil having excellent heat resistance acts effectively and can be used.
The surface tension adjusting agent can be used in an amount of 0.1 to 50 parts by weight, preferably 1 to 30 parts by weight, based on 100 parts by weight of the compound. When the amount used exceeds the above range, there is a problem that the hardness of the adhesive at room temperature is too low, or the tackiness is too high, making tableting difficult. On the other hand, if the amount is less than the above range, the effect of improving wettability and / or adhesiveness may not be exhibited.

  In order to control the gap between the substrates to be bonded, the above-mentioned immobilizing agent is optionally mixed with a metal oxide such as aluminum oxide, zirconium oxide, titanium oxide, silicon oxide, or polystyrene crosslinked particles (for example, Sekisui Chemical Co., Ltd.). Fine particles having a narrow particle size distribution, such as “Micropearl SPN, SPS series” manufactured by the same company, etc.) in a range of 0.01 to 10% by weight, preferably 0.01 to 5% by weight, based on the entire composition. Also good. When the content exceeds the above range, when melted, the fine particles are difficult to spread in the adherend surface, and the problem that the gap between the substrates cannot be controlled due to the aggregation of the fine particles may occur, which is lower than the above range. Then, the effect of controlling the gap may not appear.

The adhesive strength of the adhesive composition is 0.5 MPa or more, preferably 1 MPa or more, particularly preferably 5 MPa or more at 25 ± 2 ° C. If the adhesive strength is lower than the above range, the bonded surface may be partially peeled depending on the processing conditions after bonding, and the in-plane uniformity of the processing may be impaired.
When the adhesive strength at 25 ± 2 ° C. of the adhesive composition is A (MPa) and the adhesive strength at a temperature 20 ° C. lower than the melting temperature of the composition is B (MPa), the adhesive strength A and When B satisfies the relational expression of 0 <AB <0.5 (MPa), the temperature dependence of the adhesive strength is small, and a good adhesive state can be maintained in a wide range below the melting temperature. The measurement method and conditions will be described later.

<Immobilization method>
In the wafer processing method of the present invention, the adhesive composition (fixing agent) is heated and melted and applied to a wafer or the like, and the wafer and the support are bonded and adhered, and then cooled, Adhesive fixing to the support.
In order to apply the adhesive composition to a wafer or the like, the “melting temperature + 2 ° C.” to “melting temperature + 50 ° C.” of the composition, preferably “melting temperature + 2 ° C.” to “melting temperature + 30 ° C.”, particularly preferably Can be applied by heating in the range of “melting temperature + 5 ° C.” to “melting temperature + 20 ° C.”. If the heating temperature is lower than the above range, the adhesive may not be sufficiently spread in the adherend surface and uneven adhesion may occur. If the heating temperature exceeds the above range, volatilization and decomposition of the adhesive may partially proceed. The desired adhesive properties may not be obtained.

  The amount of the fixing agent applied can be arbitrarily selected according to the size of the adhesion surface of the wafer or the like to be used and the degree of adhesion required in the processing step. For example, the thickness of the adhesive layer is 0 It is desirable to apply in an amount of 0.01 μm to 2 mm, preferably 0.05 μm to 1 mm, more preferably 0.1 μm to 0.5 mm. If the thickness of the adhesive layer is less than the above range, the adhesive layer may not be sufficiently bonded. If the thickness exceeds the above range, the adhesive strength may be reduced, peeling off from the adhesive surface, and material failure of the adhesive may occur. Note that the thickness of the adhesive layer can be adjusted by the amount of the adhesive and the pressure at the time of bonding.

As a method of bonding the wafer and the support,
(I) a method in which an adhesive composition is applied to one or both of a wafer and a support and the both are bonded together; and (ii) a tablet-like adhesive composition is interposed between the wafer and the support. Examples of the method include bonding the wafer and the support by heating in that state and melting the adhesive composition. The method (ii) is preferably performed under a reduced pressure of 200 Torr or less in order to remove bubbles in the adhesive and make the thickness of the adhesive layer constant.

After bonding the wafer and the support as described above, the wafer is cooled to a melting temperature or lower, preferably “melting temperature −20 ° C.” or lower, particularly preferably “melting temperature −40 ° C.” or lower. And the support are firmly bonded to each other.
The processing of the wafer fixed on the support as described above is preferably performed at a temperature lower than the melting temperature of the used adhesive composition.

<Peeling method>
In the wafer processing method of the present invention, the wafer (including a semiconductor chip) is peeled from the support after the wafer processing described later. In this peeling step, by heating at least one of the wafer and the support above the melting temperature of the used adhesive composition, the adhesive composition is melted and the wafer can be peeled from the support. .

When the adhesive remains on the peeled surface, it can be removed by washing with a solvent capable of dissolving the adhesive composition. Such a solvent is not particularly limited as long as it can dissolve the adhesive composition. For example,
Alcohols such as isopropanol, butanol, hexanol, ethanol, methanol, ethylene glycol, diethylene glycol, propylene glycol, dipropylene glycol, phenol, t-amyl alcohol, cyclohexanol;
n-pentane, cyclopentane, n-hexane, cyclohexane, n-heptane, cycloheptane, n-octane, cyclooctane, n-decane, cyclodecane, dicyclopentadiene hydride, benzene, toluene, xylene, durene, indene, decalin Hydrocarbon solvents such as tetralin, tetrahydronaphthalene, decahydronaphthalene, squalane, ethylbenzene, t-butylbenzene, trimethylbenzene;
Ketones such as acetone, methyl ethyl ketone, methyl isobutyl ketone, cyclopentanone, cyclohexanone; ethers such as ethyl ether, ethylene glycol dimethyl ether, ethylene glycol diethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, tetrahydrofuran, dioxane;
Ethyl acetate, butyl acetate, ethyl butyrate, ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ether acetate, ethylene glycol monoacetate, diethylene glycol monomethyl ether acetate, diethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate Esters such as dipropylene glycol monomethyl ether acetate, dipropylene glycol monoethyl ether acetate; and
A polar solvent such as dimethylformamide, dimethylacetamide, N-methylpyrrolidone, hexamethylphosphomide, dimethylsulfoxide, γ-butyrolactone, chloroform, methylene chloride, a photoresist stripping solution, or the like can be used.

In these, isopropanol, ethanol, methanol, acetone, methyl ethyl ketone, and tetrahydrofuran are preferable. Moreover, the said solvent may be used independently, or 2 or more types may be mixed and used for it.
Examples of the cleaning method include a method of immersing a wafer in a cleaning solution, a method of spraying a cleaning solution on the wafer, and the like. Although the temperature of a washing | cleaning liquid is not specifically limited, Preferably it is 20-80 degreeC, More preferably, it is 30-50 degreeC.

  The material of the support used in the present invention is not particularly limited, but when used in a semiconductor process, a material having no eluted metal is preferable. For example, a ceramic substrate such as silicon carbide or alumina, or a metal substrate such as silicon or stainless steel can be preferably used. In order to make the molten adhesive composition easily spread uniformly on the support, it is also preferable to apply the above-mentioned surfactant on the support surface or to form a fine groove pattern in advance.

  The fine groove pattern on the support can be formed using a photosensitive resin or by plating. A pattern formed by a plating method is preferred from the viewpoint of resistance at high temperatures and repeated use. If the pattern shape is controlled to a pattern height corresponding to the bonding film thickness, the pattern can be used as a column for controlling the bonding gap, and the in-plane accuracy of the bonding can be easily improved. Furthermore, by setting the in-plane pattern design according to the flow direction of the adhesive composition (flowing from the center toward the periphery, etc.), control of bubbles and wet spread within the surface during bonding You can also

<Processing process>
The wafer bonded to the support is set together with the support in a back grinding apparatus, and is roughly ground until the thickness of the wafer reaches about 100 μm. Thereafter, the grinding distortion layer generated by grinding is removed, and processing is performed to a desired thickness of 20 to 100 μm. There is no restriction | limiting in particular about the rough grinding method at this time, A well-known method can be used. As a method for removing grinding distortion, a felt grindstone method, a plasma etching method, a CMP method, a chemical etching method, or the like can be selected.

As the felt grindstone used in the felt grindstone method, for example, a grindstone produced by impregnating a felt material described in JP-A-2002-283221, JP-A-2002-283212, etc. with an abrasive is suitably used. Can be used.
In the plasma etching method, JP-A-6-338479, JP-redisplay 98/016950, JP 2003-100718 discloses a device shown like in JP-A-2003-229418 using, CF _4, An etching gas such as C ₄ F ₈ or C ₅ F ₈ (octafluorocyclopentene) can be used. As the plasma etching method, the reactive ion etching (RIE) method capable of controlling the temperature of the wafer and performing anisotropic etching is preferable in that the processing speed and the temperature applied to the wafer are small.

The CMP method is used for flattening even during device formation. When polishing the back surface, polishing is performed by switching to a simple slurry in which silicon fine particles are dispersed in water in order to eliminate contaminating ions as much as possible. Can do.
The chemical etching method is carried out using an about 40-50% KOH solution, HF / nitric acid mixed solution, etc. as an etching solution, and is made into an apparatus like “GL-210S” manufactured by SEZ, which can be used. .

Processing until a wafer that has been polished to a desired thickness is mounted as a semiconductor chip differs depending on the application of the semiconductor chip, but in the present invention, a process that could not be achieved is bonded to the support. It is possible to perform in the state. An example of such a process is shown below.
(1) A resist pattern is formed on the polished surface, and the wafer is etched using the resist pattern as a mask, thereby forming desired structures such as cavities, holes (including through holes), protrusions, grooves, and the like on the back surface of the wafer.

(2) An organic film layer is applied to the polished surface and baked to form an ion contamination preventing film on the polished surface.
(3) The wafer is diced without being attached to the dicing tape by selecting a fixing agent having a desired hardness and adhesive strength.
(4) Using a through via as an inspection electrode, a wafer level burn-in test is performed after thinning.

(5) The wafer in which the cutting groove is formed in the dicing street by the first dicing is thinned until the cutting groove is exposed according to the above processing method, and the semiconductor chip that has been cut into pieces is picked up at the same time as the fixing agent is melted, The fixing agent remaining on the chip is utilized as an underfill agent or a chip bonding agent and mounted on the package substrate.
<Wafer>
The semiconductor wafer used in the wafer processing method of the present invention is not particularly limited, and a semiconductor wafer according to the application and processing method can be used. The semiconductor wafer may have a large area or have various and complicated structures on the surface. .

For example, the process (5) includes a semiconductor element formed in a region partitioned by a plurality of dicing streets, and a cutting groove corresponding to the thickness of the semiconductor chip is formed on the dicing streets by first dicing. The formed semiconductor wafer can be used.
In the process (4), a hole having a predetermined depth is formed on the surface, the inner wall of the hole is covered with an insulating film, and a conductive electrode material is embedded in the hole covered with the insulating film. A semiconductor wafer can be used.

Further, the semiconductor wafer may have conductive bump electrodes such as solder bumps formed on the surface.
[Example]
Hereinafter, the present invention will be described more specifically based on examples in which some of the above-described examples are practiced, but the present invention is not limited to these examples.

  The compounds used in the following examples were prepared in advance in a THF solution, added with 20 parts by weight of an ion exchange resin, stirred and mixed for 10 hours, and then purified by deionization. Na, K, Ca , Fe, Cu, Ni, Cr and Al were used after confirming that their metal contents were 1 ppm or less. Moreover, the measurement of the melting temperature, the melting temperature width, the melt viscosity, and the adhesive strength was performed as follows.

<Melting temperature and melting temperature range>
Using a differential scanning calorimeter (“RDC220” manufactured by Seiko), the value in air was measured at 2 ° C./min. The peak temperature of the main melting peak curve was defined as the melting temperature, and the temperature difference between the start point and the end point of the melting peak curve was defined as the melting temperature width.
<Melt viscosity>
Using an E-type viscometer (manufactured by Toki Sangyo Co., Ltd.), it was measured at the melting temperature.

<Adhesive strength>
As adhesive strength specific to each adhesive composition, adhesive strength A (MPa) at 25 ± 2 ° C. and adhesive strength B (MPa) at a temperature 20 ° C. lower than the melting temperature of the adhesive composition are measured as follows. Then, the difference in adhesive strength (AB) was determined.
As shown in FIG. 5, a silicon wafer piece (50 mm × 12 mm) having a thickness of 650 μm and a non-alkali glass piece (50 mm × 12 mm) having a thickness of 0.7 mm are formed on the surface of the silicon wafer (surface polished in a product state). Prepare a test piece (adhesive area: 12 mm x 12 mm, adhesive thickness: 10 μm) with each adhesive composition as the adhesive surface, hold the end vertically, grab the edge, and pull it up and down with a constant load The tensile shear strength when both substrates were peeled was measured, and the value was taken as the adhesive strength. The silicon wafer (baresilicon) and non-alkali glass ("# 1737" manufactured by Corning) used for preparing the test piece were previously washed with RCA [W. Kern, DAPuotinen, RCA Review, 31, p187 (1970) Reference] was used. Specifically, the silicon wafer is placed in an SC-1 solution (H ₂ O: NH ₄ OH: H ₂ O ₂ = 5: 1: 1) at 80 ° C. for about 10 minutes to remove organic contamination and metal contamination. This was washed with ultrapure water. Next, the silicon oxide film formed on the silicon wafer in the previous step was removed using a solution of HF: H ₂ O ₂ = 1: 50. After that, it was washed again with ultrapure water, and further, residual metal contamination was removed in a SC-2 solution (H ₂ O: HCl: H ₂ O ₂ = 6: 1: 1) 80 ° C. Washed with pure water and dried.

The measurement was performed using a Tensilon type tensile tester at a tensile speed of 1.67 × 10 ⁻⁴ m / s and a predetermined temperature. In order to keep the test piece at a predetermined temperature, a glass tube (heater for sample heating) wrapped with a ribbon heater is arranged so as not to touch the test piece, and the temperature of the thermocouple attached to the test piece becomes a predetermined temperature. The heating of the ribbon heater was controlled with a temperature controller. In addition, the upper left figure of FIG. 5 is the figure which looked at the test piece for adhesive strength measurement from the top, and the lower left figure is the figure which looked at this test piece from the side. Further, the adhesive strength when the silicon wafer actually used in each example and the substrate were bonded was also measured in the same manner.

(Example 1)
Cholesterol (molecular weight: 386.7, melting temperature: 150 ° C., melting temperature range: 1 ° C., melt viscosity: 2 mPa · s, difference between adhesive strength A at 25 ° C. and adhesive strength B at 130 ° C .; 0.2 MPa) 0 354 g was weighed into a columnar pressure molding machine having a diameter of 10 mm, and a pressure of 200 kg · cm ⁻² was applied for 3 minutes to obtain a cylindrical tablet having a diameter of 10 mm and a thickness of 5.5 mm.

  The obtained tablet was placed on a 6-inch silicon wafer (thickness: 650 μm) on which a plurality of semiconductor elements were formed, and a square SUS substrate having a thickness of 0.7 mm and a side of 20 cm was placed thereon and placed in a vacuum oven. . In addition, the SUS board | substrate used as a support body used what carried out the hydrophobization process of the surface by spin-coating and drying the 5% isopropyl alcohol solution of hexamethyldisilazane. When the vacuum oven (10 Torr) was heated to 160 ° C. at a rate of 1 ° C./min, the tablet melted at a wafer temperature of about 148 ° C. and became liquid. At this point, the vacuum suction was stopped, and when the molten cholesterol was degassed under a reduced pressure of 10 Torr for 2 minutes, the cholesterol spread over the entire surface of the wafer. When the bonded sample was taken out from the vacuum oven, the sample was rapidly cooled, so that cholesterol was immediately crystallized, and both substrates were firmly bonded. A 6-inch silicon wafer having the same specifications as described above and a SUS substrate were adhered to each other to produce a test piece similar to that shown in FIG. 5, and the tensile shear strength was measured. The adhesive strength was 5 MPa (25 ° C.).

  Next, using a commercially available polishing apparatus, the back surface of the wafer bonded to the SUS substrate was roughly ground, and then polished by a disc grinder “Polisher DFP8140” using a felt grindstone method to make the wafer thickness 100 μm. After polishing, a dry film resist was laminated on the polished surface of the wafer adhered to the SUS substrate to form a 50 μm square pattern. During this time, stress of laminating temperature (100 ° C.), alkali development and drying (120 ° C.) was applied to the wafer, support and fixing agent, but the wafer was firmly adhered to the support.

Next, through-holes reaching the wafer surface were formed by RIE using CF ₄ as an etching gas using a 50 μm square hole pattern as a mask. Thereafter, the SUS substrate is heated to melt the immobilizing agent, the wafer is removed from the support, and washed by immersing in isopropyl alcohol at 40 ° C. for 1 minute to have a 100 μm-thick wafer having a through-hole vacated from the back surface. Got.

The obtained wafer was diced as usual, and the defect rate of the semiconductor chip was compared with the case where the through hole was not formed, and the defect rate did not change even when new backside processing was performed to provide the through hole. . A model diagram of the above processing method is shown in FIG.
(Example 2)
In Example 1, instead of a 6-inch silicon wafer on which a semiconductor element is formed, a solder bump (FIG. 2) having a height of 65 μm is formed on the wafer surface by using a thick film resist (“THB series” manufactured by JSR Corporation). Using a 6-inch wafer with a concavo-convex pattern in which cutting grooves (5 mm square) with a depth of 80 μm were formed in advance by dicing, and a compound (molecular weight; 404) represented by the above chemical formula (8) was used instead of cholesterol. 0.7, melting temperature: 223 ° C., melting temperature range: 1 ° C., melt viscosity: 1 mPa · s) 1.5 g, release agent “KF54” (manufactured by Shin-Etsu Silicone), 0.15 g, and fine silicon dioxide particles ( Shionogi & Co., Ltd., average particle size; 2 μm) 0.09 g mixture (melting temperature: 223 ° C., melting temperature range: 1 ° C., melt viscosity: 1 mPa · s, at 25 ° C. A tablet was formed using the difference between the adhesive strength A and the adhesive strength B at 203 ° C. (0.3 MPa), a glass substrate was used instead of the SUS substrate, and the heating temperature of the vacuum oven was 240 ° C. In the same manner as in Example 1, a wafer was bonded to a glass substrate. When the concavo-convex pattern of the wafer was observed with a microscope from the glass substrate surface, the fixing agent uniformly penetrated into the groove portion of the pattern, and bubbles were not observed. Moreover, when the same 6-inch silicon wafer with a concavo-convex pattern as above and a glass substrate were adhered to produce a test piece similar to FIG. 5 and the adhesive strength was measured, the tensile shear strength was 4.5 MPa (25 ° C.). there were.

Next, the wafer was ground and polished to a thickness of 100 μm in the same manner as in Example 1, and then polished by a felt grindstone method using “Polisher DFP8140” manufactured by Disco Corporation to reduce the thickness to 70 μm. During polishing, the wafer was firmly fixed without being peeled off from the crow substrate of the support.
In order to protect the polished surface with an insulating film, a photosensitive insulating film (“WPR1100” manufactured by JSR Corporation) of 2 μm was applied to the polished surface by spin coating, and the dicing groove portion was removed by exposure-development. Next, a wafer piece that was separately thinned to a thickness of 70 μm and cut into 3 mm squares was placed thereon. The laminate is heated to 240 ° C. to melt the fixing agent, and the insulating film “WPR1100” is used as an adhesive to cure a 5 mm square wafer piece (70 μm thickness) with solder bumps and a 3 mm square wafer piece (70 μm thickness). The bonded laminate was displaced from the support.

A small piece in which a 3 mm square wafer piece was laminated on a 5 mm square wafer piece was immersed in t-amyl alcohol at 40 ° C. for 3 minutes to remove the fixing agent. The solder bumps formed on the 5 mm square wafer side kept the initial state, and there was no dropout. A model diagram of the process is shown in FIG.
(Example 3)
The wafer thinned to a thickness of 100 μm in Example 1 and formed with through holes was set as it was in a dicing apparatus (“DAD321” manufactured by Disco Corporation), and dicing grooves were formed in units of semiconductor elements. At this time, the semiconductor chip was not peeled off in small pieces and was fixed to the SUS substrate with a fixing agent. Next, the SUS substrate is heated to 170 ° C., the semiconductor chips are individually picked up by vacuum tweezers and separated from the SUS substrate as a support, and the fixing agent adhered to the element surface is immersed in 40 ° C. isopropanol for 3 minutes. Removed.

The chipping defect of the cut edge part of the surface (semiconductor element surface) of each semiconductor chip is compared with the case of using a normal dicing tape (“River Alpha No. 3193M” manufactured by Nitto Denko Corporation). The rate was reduced by about 30%.
Example 4
As shown in FIG. 4, a hole of 50 μm □ and a depth of 80 μm is further drilled in the 6-inch silicon wafer on which the semiconductor element of Example 1 is formed, and a silicon nitride film is formed on the wall surface and element surface of the hole. Twenty via structures filled with copper plating and serving as through wirings were formed at equal intervals around a 3 mm square element. This wafer is ground and polished to 100 μm in the same manner as in Example 1, and then the front surface of the polished surface is uniformly etched with a reactive ion etching apparatus “RIE-10NR” manufactured by Samco, and etched to a thickness of 80 μm where copper appears on the surface. Went. The thinned wafer together with the support (SUS substrate) was placed in a clean oven adjusted under a nitrogen atmosphere and held at 140 ° C. for 20 hours, but the wafer was held without being displaced from the support.

The above results show that the wafer level burn-in test is normally performed at 125 ° C., so if the pre-formed through copper wiring is used as the test terminal of the semiconductor element, the operation in the thinned state, that is, the chip state immediately before mounting Indicates that the test can be performed.
(Example 5)
1-octadecanol 1.5 g (molecular weight: 270.5, melting temperature: 60 ° C., melting temperature range: 1 ° C.) was used as the immobilizing agent for the 6-inch wafer with a concavo-convex pattern used in Example 2 and a glass substrate. Bonding was performed using a melt viscosity of 1.5 mPa · s, a difference between an adhesive strength A at 25 ° C. and an adhesive strength B at 40 ° C. (0.1 MPa). For the bonding, a tablet-shaped fixing agent is placed on the wafer, placed in a vacuum oven and heated to 80 ° C. at 10 Torr, and then the distance between the bottom surface of the wafer and the bottom surface of the glass substrate is 1425 μm [= 75 μm + wafer thickness ( 650 μm) + glass substrate thickness (700 μm)], each substrate was held and returned to normal pressure and cooled to solidify the immobilizing agent. When the concavo-convex pattern of the wafer was observed with a microscope from the glass substrate surface, the fixing agent uniformly penetrated into the groove portion of the pattern, and bubbles were not observed.

In the same manner as in Example 1, the bonded sample was roughly ground on the back surface of the wafer so that the wafer thickness was 50 μm, and then polished by a felt grindstone method using “Polisher DFP8140” manufactured by Disco Corporation. The wafer thickness was 30 μm. It was. A 5 mm square dicing groove provided in advance on a 6-inch wafer appeared on the polished surface, and it was confirmed that the groove was filled with a fixing agent.
The thinned sample with the glass substrate down was placed on a hot plate and heated to 80 ° C. The chip divided into 5 mm squares can be easily picked up with vacuum tweezers, and the edge portion of the chip is kept intact.

(Comparative Example 1)
A back grind tape (“BGE-164VC” manufactured by Toyo Adtec Co., Ltd.) was applied to the surface of a 6-inch wafer with a concavo-convex pattern used in Example 2, and grinding and polishing were performed in the same manner as in Example 5 to obtain a wafer thickness of 30 μm. did. When the polished surface was observed, there were many defects at the edge portions of the 5 mm square dicing grooves provided in advance, and there were residues of abrasive in the grooves. Chips cut into 5mm squares could not be peeled off from the tape with vacuum tweezers, and the chips were broken when trying to remove them.

(Comparative Example 2)
Using a 6-inch wafer and a glass substrate with the same concave / convex pattern as in Example 5 and using a water-soluble silicone wax (“KF6004” manufactured by Shin-Etsu Chemical Co., Ltd.) having a melting temperature of 45 ° C. as a fixing agent, vacuum was applied in the same manner as in Example 5. Under heating, both substrates were bonded together. When observing the groove portion of the concavo-convex pattern of the wafer from the glass substrate surface, no bubbles were observed. However, when the polished surface after grinding and polishing was performed in the same procedure as in Example 5, there was a gap in the dicing groove portion. There was a chipping at the chip edge portion of that portion. Further, since KF6004 is water-soluble, there was a portion where KF6004 in the dicing groove was partially dissolved and separated by cleaning the polished surface. In order to protect the polished surface with an insulating film, a photosensitive insulating film (“WPR1100” manufactured by JSR Co., Ltd.) 2 μm was applied to the polished surface by spin coating. The immobilizing agent dissolved in WPR1100 was spin coated. Sometimes the chips were scattered.

From Comparative Examples 1 and 2, the conventional method cannot obtain a chip thinned to a thickness of 30 μm with a high yield, and the polished surface can be additionally processed, for example, the back surface of the chip can be protected with an insulating film. could not.

Claims (13)

As a fixing agent for fixing the wafer and the support between the wafer surface on which the semiconductor element is formed and the support, an adhesive composition containing a compound having a molecular weight of 1000 or less as a main component is interposed.
After the composition is heated and melted to bring the wafer and the support into close contact, the wafer and the support are bonded and fixed by cooling,
By thinning the backside of the wafer,
A wafer processing method, wherein the composition is heated and melted to separate the wafer and the support.   2. The wafer processing method according to claim 1, wherein the compound is a compound having a steroid skeleton or a hydroxyl group in the molecule or a derivative thereof.   2. The wafer processing method according to claim 1, wherein the compound is a compound having a steroid skeleton and a hydroxyl group in the molecule or a derivative thereof.   The melting temperature at the melting peak value measured with the differential scanning calorimetric analyzer of the above compound is 50 to 300 ° C., and the temperature difference between the starting point and the ending point of the melting peak value measured with the differential scanning calorimetric analyzer of the above composition The wafer processing method according to claim 1, wherein a melting temperature range represented by: is 30 ° C. or less.   The wafer processing method according to claim 1, wherein in the step of polishing the back surface of the wafer, the wafer is thinned to 20 to 100 μm. When the adhesive strength at 25 ± 2 ° C. of the composition is A (MPa) and the adhesive strength at a temperature 20 ° C. lower than the melting temperature of the composition is B (MPa), the adhesive strengths A and B are represented by the following formulas: The wafer processing method according to claim 1, wherein (1) is satisfied.
0 <A-B <0.5 (MPa) (1)   The wafer processing method according to claim 1, wherein the composition is in the form of a tablet.   2. The wafer processing method according to claim 1, wherein the wafer has a semiconductor element formed in a region partitioned by a plurality of dicing streets on the surface.   9. The wafer processing method according to claim 8, wherein a cutting groove is formed in the dicing street.   10. The wafer processing method according to claim 9, wherein the wafer is thinned by polishing until the cutting groove is exposed, and is cut into semiconductor chips, which are separated from the support in units of the semiconductor chips.   The wafer is a wafer in which a hole having a predetermined depth is formed on a surface, an inner wall of the hole is covered with an insulating film, and a conductive electrode material is embedded in the hole covered with the insulating film. The wafer processing method according to claim 1.   The wafer processing method according to claim 1, wherein the wafer has a conductive electrode for conduction. 2. The wafer processing method according to claim 1, wherein after the wafer is thinned by the polishing, the polishing surface is further processed to form at least one selected from a structure, a wiring, and an element. 3.