JPWO2005020573A1 - Data string sample and hold method, apparatus, and semiconductor integrated circuit - Google Patents

Abstract

The storage capacity of a storage medium is minimized, and data before the arrival of a trigger signal and data after the arrival of a trigger signal are clearly separated and managed independently. Area definition data storage means for storing area definition data for defining a first storage area and a second storage area in a primary storage medium, and incoming data in the first storage area Instead of stopping the data write to the first storage area after waiting for the trigger signal to arrive, and Second write control means for writing data that has arrived after the arrival of the signal into the second storage area.

Description

  The present invention relates to a sample-and-hold method suitable for various data analysis applications and the like, and in particular, among a series of continuously arriving data, a series existing in a predetermined section before and after the arrival timing of a predetermined trigger signal. The present invention relates to a method for surely sampling and holding only the data.

  If it is possible to sample and hold only a series of data existing in a predetermined section before and after the arrival timing of a predetermined trigger signal among a series of data that arrives continuously, it is convenient for various data analysis applications.

  For example, when a security camera is attached to the entrance to monitor a visitor, the arrival of the visitor is detected based on a separately provided sensor or a change in the image itself, and this is used as a trigger from the detected security camera. It is conventionally known to store video data for a certain period (see Patent Document 1). At this time, if not only video data for a certain period after detection but also video data for a certain period before detection can be stored, by reproducing the video based on both the stored video data, Visitors can be observed in more detail.

  In addition, while monitoring the state of the object based on the measurement data from a plurality of measuring instruments, triggered by the fact that the feature quantity indicated by the measurement data coincides with the feature quantity at the time of the event occurrence that is assumed in advance, It is also known in the field of monitoring systems that measurement data for a certain period is stored. At this time, if it is possible to save not only the measurement data for a certain period after the trigger occurrence but also the measurement data for a certain period before the trigger occurrence, both the saved measurement data can be used to verify the event occurrence detection accuracy. It is effective in predicting the occurrence of events.

Furthermore, while the vehicle state is monitored based on measurement data from a plurality of measuring instruments, the occurrence of the trigger is triggered by the fact that the feature values indicated by the measurement data match the feature values at the time of the accident. If it is possible to save not only the measurement data for a certain period of time but also the measurement data for a certain period before the occurrence of the trigger, both of the saved measurement data are effective for investigating the cause of the accident.
JP-A-4-32390

  The problem to be solved by the present invention is to reliably sample and hold only a series of data existing within a predetermined section before and after the arrival timing of a predetermined trigger signal among a series of data that continuously arrive. An object of the present invention is to provide a sample hold method and apparatus.

  Another problem to be solved by the present invention is that the storage capacity of the storage medium required to achieve the above-mentioned problem is minimized, and a series included in a predetermined section before the arrival timing of the trigger signal. And a sample-and-hold method and apparatus capable of clearly separating a series of data included in a predetermined section after the arrival timing of a trigger signal and independently managing the data.

  Still another problem to be solved by the present invention is to reliably sample and hold only a series of data existing within a predetermined section before and after the arrival timing of a predetermined trigger signal among a series of data that continuously arrive. Another object of the present invention is to provide a highly versatile semiconductor integrated circuit suitable for the purpose of doing so.

  Still other problems of the present invention will be easily understood by those skilled in the art by referring to the following description.

  The sample and hold method of the present invention is a method for sampling and holding only a series of data existing within a predetermined section before and after the arrival timing of a predetermined trigger signal, among a series of data that arrives continuously. This method prepares a primary storage medium in which a first storage area corresponding to a front section of the arrival timing of the trigger signal and a second storage area corresponding to a rear section of the arrival timing of the trigger signal are defined. A second step of continuing the operation of writing a series of incoming data to the first storage area while cyclically incrementing addresses until the trigger signal arrives, and the trigger signal arrives A third step of writing a series of data that arrived after the arrival of the trigger signal to the second storage area instead of stopping the data writing to the first storage area after waiting for Configured.

  According to such a configuration, a series of data that has arrived before the arrival of the trigger signal is stored in the first storage area of the primary recording medium, and a series of data that has arrived after the arrival of the trigger signal is stored in the first storage area of the primary recording medium. Is stored in the second storage area. Therefore, according to this method, the required storage capacity of the storage medium is kept to the minimum necessary, and the series of data included in the predetermined section before the arrival timing of the trigger signal and the predetermined section after the arrival timing of the trigger signal Can be managed independently by separating them clearly from the series of data contained in the.

  At this time, if the primary storage medium is a non-volatile storage medium suitable for high-speed storage such as an opto-memory, or a volatile storage medium such as DRAM backed up by a power source, the power is cut off when the trigger signal arrives. Even if this occurs, it is possible to reliably sample and hold a series of data existing in a predetermined section before and after the arrival timing of the trigger signal.

  The sample hold method of the present invention waits for the completion of the third step to transfer the data written in the first and second storage areas of the primary storage medium to the secondary storage medium. You may make it have a 4th step further.

  According to such a configuration, a series of data that arrived before the arrival of the trigger signal stored in the first storage area of the primary recording medium and the arrival of the trigger signal stored in the second storage area of the primary recording medium A series of data that has arrived thereafter is transferred to the secondary recording medium. Therefore, according to this method, the required storage capacity of the storage medium is kept to the minimum necessary, and the series of data included in the predetermined section before the arrival timing of the trigger signal and the predetermined section after the arrival timing of the trigger signal The series of data contained in the data can be clearly separated and each can be managed safely independently, and the sample-and-hold data string is finally stored on the secondary recording medium, so the next sample-and-hold standby operation Will not be disturbed.

  At this time, if the primary storage medium is a volatile storage medium suitable for high-speed storage such as DRAM, and the secondary storage medium is a non-volatile storage medium such as flash memory or hard disk, the storage speed is increased and the storage is performed. Both data security and satisfaction can be satisfied.

  In the two inventions described above, the storage capacity of the first storage area is preferably an integral multiple (more preferably twice) of the storage capacity of the second storage area. In this way, when image data, audio data, and the like divided into frame units are targeted, a data string of data stored in the first storage area and data stored in the second storage area ( Frame) can be easily compared.

  By the way, it is assumed that each of a series of data that continuously arrives is fixed length data and indefinite length data. The former corresponds to raw data such as temperature, humidity, and speed. The latter corresponds to compressed data having a different data length for each frame such as MPEG4. It is not preferable to manage indefinite-length data in one-to-one correspondence with memory addresses from the viewpoint of saving memory capacity. In such a case, the first and second steps include a step of measuring the data length of individual indefinite length data that arrives in succession, and control data including the measured data length in the storage area. And adding to each of the indefinite length data to be written to. According to such a configuration, since the beginning and the end of the indefinite length data can be specified by the control data, the indefinite length data can be densely packed in the memory regardless of the memory address, and the memory capacity can be saved.

  In addition, there are many cases where each of a series of data that arrives continuously is divided into frames. In such frame format data, control data necessary for data reproduction is added to the end or the beginning of the frame, so the data belonging to one frame is divided into two at the timing of the arrival of the trigger signal. If they are separate files, it is essential to combine both files for playback. Data files sampled and held by this type of sample-and-hold method can be provided to insurance companies as evidence in the event of a traffic accident, so the files before and after the accident can be handled completely separately. Is required. In such a case, in the first step, in the operation of writing a series of incoming data in the first storage area while cyclically moving the address, the frame being written ends when the trigger signal arrives. In the second step, the operation of writing a series of data that has arrived after the arrival of the trigger signal in the second storage area in the second step is performed after the frame being written is terminated when the trigger signal arrives. May be started. According to such a configuration, since the two separated files are separated at a frame break, there is no need to combine both files at the time of data reproduction. As a result, the situation before and after the trigger timing is the boundary. Can be managed completely independently.

  The sample hold device of the present invention is a device for sample-holding only a series of data existing within a predetermined section before and after the arrival timing of a predetermined trigger signal, among a series of data arriving continuously. The apparatus includes a primary storage medium, a first storage area corresponding to a preceding section of the arrival timing of the trigger signal in the primary storage medium, and a second storage area corresponding to a rear section of the arrival timing of the trigger signal. The area definition data storage means for storing the area definition data for defining the data and the incoming series of data are written in the first storage area defined by the area definition data while the address is cyclically incremented. Instead of stopping the writing of data to the first storage area after waiting for the trigger signal to arrive, the first write control means for continuing the operation until the trigger signal arrives. Second write control means for writing a series of data that has arrived since the arrival into the second storage area defined by the area definition data; Composed of Te.

  According to such a configuration, a series of data that has arrived before the arrival of the trigger signal is stored in the first storage area of the primary recording medium, and a series of data that has arrived after the arrival of the trigger signal is stored in the first storage area of the primary recording medium. Is stored in the second storage area. Therefore, according to this method, the required storage capacity of the storage medium is kept to the minimum necessary, and the series of data included in the predetermined section before the arrival timing of the trigger signal and the predetermined section after the arrival timing of the trigger signal Can be managed independently by separating them clearly from the series of data contained in the.

  At this time, if the primary storage medium is a non-volatile storage medium suitable for high-speed storage such as an opto-memory, or a volatile storage medium such as a power-backed DRAM, the power is cut off upon arrival of a trigger signal. Even if this occurs, it is possible to reliably sample and hold a series of data existing in a predetermined section before and after the arrival timing of the trigger signal.

  The sample hold device of the present invention further includes a secondary storage medium and data transfer control means for transferring data written in the first and second storage areas of the primary storage medium to the secondary storage medium. You may do it.

  According to such a configuration, a series of data that arrived before the arrival of the trigger signal stored in the first storage area of the primary recording medium and the arrival of the trigger signal stored in the second storage area of the primary recording medium A series of data that has arrived thereafter is transferred to the secondary recording medium. Therefore, according to this method, the required storage capacity of the storage medium is kept to the minimum necessary, and the series of data included in the predetermined section before the arrival timing of the trigger signal and the predetermined section after the arrival timing of the trigger signal The series of data contained in the data can be clearly separated and each can be managed safely independently, and the sample-and-hold data string is finally stored on the secondary recording medium, so the next sample-and-hold standby operation Will not be disturbed.

  At this time, if the primary storage medium is a volatile storage medium suitable for high-speed storage such as DRAM, and the secondary storage medium is a non-volatile storage medium such as flash memory or hard disk, the storage speed is increased and the storage is performed. Both data security and satisfaction can be satisfied.

  The sample and hold device of the present invention may have region definition data generating means for internally generating region definition data based on externally input data. Here, as described above, the “area definition data” defines the first storage area corresponding to the front section and the second storage area corresponding to the rear section on the primary storage medium. For example, it means the top address and end address of the area, the maximum number of bytes from the start address, and the like. According to such a configuration, the area definition data can be appropriately set by providing input data from the outside.

  At this time, both the data indicating the capacity of the first storage area and the data indicating the capacity of the second storage area are included in the input data from the outside, and the area definition data generating means The area definition data may be generated based on the data. According to such a configuration, the capacity of the first storage area and the capacity of the second storage area can be individually set to arbitrary sizes by giving input data from the outside.

  Further, although the data indicating the capacity of the first storage area is included in the input data from the outside, the data indicating the capacity of the second storage area is not included. The area definition data may be generated based only on the data indicating the capacity of the area. According to such a configuration, by providing an appropriate correlation between the capacity of the first storage area and the capacity of the second storage area in advance, input data indicating only the capacity of the first storage area can be obtained. It is possible to appropriately set the first storage capacity and the second storage capacity simply by giving.

  In the two inventions described above, the storage capacity of the first storage area is preferably an integral multiple (more preferably twice) of the storage capacity of the second storage area. In this way, when image data, audio data, or the like divided into frame units is targeted, the first storage area can be obtained by making the capacity of the second storage area correspond to the size of the frame, for example. The collation process between the data strings of the data stored in the data storage and the data stored in the second storage area is facilitated.

  Further, as described above in connection with the sample-and-hold method, the first and second write control means are used in order to cope with the case where each of a series of continuous data is indefinite length data. Includes means for measuring the data length of individual indefinite-length data that arrives before and after, means for adding control data including the measured data length to each of the indefinite-length data to be written in the storage area, and May be included.

  Furthermore, in order to cope with the case where each of a series of data that arrives continuously is data divided in units of frames, the first write control means stores the series of data that arrives in the first storage area. The operation of writing while cyclically incrementing the address is continued until the frame being written is completed when the trigger signal arrives, and the second write control means has a series of operations that have arrived since the arrival of the trigger signal. The operation of writing the data in the second storage area may be started after the frame being written ends when the trigger signal arrives.

  From another aspect, the present invention provides a highly versatile semiconductor integrated circuit suitable for carrying out the above method and apparatus. The semiconductor integrated circuit includes a first port to which a series of data to be sampled is input, a second port to which a predetermined trigger signal is input, and a third port connected to a predetermined primary storage medium. A port, a fourth port for outputting a series of sampled and held data, and an area definition for defining a first storage area and a second storage area in a primary storage medium connected to the third port Area definition data storage means for storing data and a series of data input from the first port are written to the first storage area of the storage medium connected to the third port while the address is cyclically incremented. The first write control means that continues the operation until the trigger signal is input from the second port, and waits for the trigger signal to be input from the second port, to the first storage area of the storage medium Day of A second write control means for writing a series of data that has arrived after the arrival of the trigger signal to the second storage area of the storage medium instead of stopping the writing; and a primary storage medium connected to the third port. Data read control means for controlling the data stored in the first storage area and the second storage area to be sent to the fourth port.

  According to such a configuration, in a state where the primary storage medium is connected to the third port, only a series of data to be sampled is given to the first port, and a predetermined trigger signal is given to the second port. Thus, the first and second storage areas are appropriately defined in the primary storage medium, and when the trigger signal arrives, the first storage area of the primary storage medium stores a data string in a certain interval immediately before the trigger signal arrives. As a result, a data string in a certain interval immediately after the arrival of the trigger signal is stored in the second storage area of the primary storage medium. Thereafter, these data strings stored in the primary storage medium are read out from the fourth port.

  At this time, if the primary storage medium is a non-volatile storage medium suitable for high-speed storage such as an opto-memory, or a volatile storage medium such as a power-backed DRAM, the power is cut off when the trigger signal arrives. Even if a vehicle collision accident (for example, when used as a data logger for a vehicle) occurs, a series of data existing in a predetermined section before and after the arrival timing of the trigger signal can be reliably sampled and held. .

  Note that the first to fourth ports described above do not necessarily mean that they are independent ports, and one port may realize the function of two or more ports. For example, one port may be used as a function of a first port for inputting a series of data to be sampled and a second port for inputting a predetermined trigger signal.

  In the semiconductor integrated circuit of the present invention, power is supplied not only to the inside of the semiconductor integrated circuit but also to an externally connected storage medium and an externally connected oscillator that supplies an operation clock to the semiconductor integrated circuit. You may make it have a power supply control part to supply. According to such a configuration, it is not necessary to prepare a power source on the storage medium and the clock oscillator side, so that the design can be facilitated accordingly. At this time, if an external terminal for connecting a supercapacitor for holding the power supplied from the power supply control unit for a predetermined time in the event of a power failure is provided, a spar capacitor having an appropriate capacity is externally connected thereto. Thus, even if a power failure occurs with the arrival of the trigger signal, the reliability of the sample hold processing operation can be ensured by maintaining the functions of the operation clock oscillator and the storage medium normally.

  In the semiconductor integrated circuit of the present invention, a fifth port to which control data is input, and region definition data generation for internally generating the region definition data based on the control data input from the fifth port Means may be further included. According to such a configuration, by providing appropriate control data to the fifth port from the outside, it is possible to easily set an appropriate storage area in accordance with various sampling data.

  At this time, both the data indicating the capacity of the first storage area and the data indicating the capacity of the second storage area are included in the control data from the outside, and the area definition data generating means 2 The area definition data may be generated based on one data. According to such a configuration, the capacity of the first storage area and the capacity of the second storage area can be individually set to arbitrary sizes by giving control data from the outside.

  The external control data includes the data indicating the capacity of the first storage area, but does not include the data indicating the capacity of the second storage area. The area definition data may be generated based only on data indicating the capacity of one area. According to such a configuration, by providing an appropriate correlation between the capacity of the first storage area and the capacity of the second storage area in advance, the control data indicating only the capacity of the first storage area It is possible to appropriately set the first storage capacity and the second storage capacity simply by giving.

  A semiconductor integrated circuit according to another aspect of the present invention includes a first port to which a series of data to be sampled is input, a second port to which a predetermined trigger signal is input, and a predetermined primary storage medium A third port connected to, a fourth port connected to a predetermined secondary storage medium, a fifth port for reading sampled and held data, and a third port. In addition, an area definition data storage means for storing area definition data defining the first storage area and the second storage area in the primary storage medium, and a series of data input from the first port A first write control means for continuing the write operation while cyclically incrementing the address in the first storage area of the primary storage medium connected to the port until a trigger signal is input from the second port; From the port Instead of waiting for the input of the rigger signal and stopping the writing of data to the first storage area of the primary storage medium, a series of data that has arrived after the arrival of the trigger signal is stored in the second storage of the primary storage medium. Second write control means for writing to the area, and secondary storage medium connected to the fourth port for data written to the first and second storage areas of the primary storage medium connected to the third port Data transfer control means for transferring the data to the fifth port, and data read control means for controlling the data stored in the secondary storage medium connected to the fourth port to the fifth port. Composed.

  According to such a configuration, in a state where the primary storage medium is connected to the third port and the secondary storage medium is connected to the fourth port, a series of data to be sampled is stored in the first port. The first and second storage areas are appropriately defined in the primary storage medium only by giving predetermined trigger signals to the two ports, respectively. Further, when the trigger signal arrives, the first storage area of the primary storage medium is provided. Is stored in the second storage area of the primary storage medium, and in the second storage area of the primary storage medium, the data string in the predetermined section immediately after the arrival of the trigger signal is stored, and these data strings are further transferred to the secondary storage medium. Will be transferred. Thereafter, these data strings stored in the secondary storage medium are read out from the fourth port.

  At this time, if the primary storage medium is a volatile storage medium suitable for high-speed storage such as DRAM, and the secondary storage medium is a non-volatile storage medium such as flash memory or hard disk, the storage speed is increased and the stored data is saved. Both safety and satisfaction can be satisfied.

  In the semiconductor integrated circuit according to the present invention, not only the semiconductor integrated circuit but also externally connected primary and secondary storage media, and an externally connected operation clock supplied to the semiconductor integrated circuit. You may make it have a power supply control part which supplies power also to the oscillator to perform. According to such a configuration, since it is not necessary to prepare a power source on the primary and secondary storage media and the clock oscillator side, the design can be facilitated accordingly. At this time, if an external terminal for connecting a supercapacitor for holding the power supplied from the power supply control unit for a predetermined time in the event of a power failure is provided, a spar capacitor having an appropriate capacity is externally connected thereto. Thus, even if a power failure occurs with the arrival of the trigger signal, the function of the operation clock oscillator and the primary and secondary storage media are maintained normally, thereby guaranteeing the certainty of the sample hold processing operation. be able to. For example, even if a situation in which the power is cut off with the arrival of the trigger signal (for example, a vehicle collision accident when used as a data logger for a vehicle) occurs, within a predetermined interval before and after the arrival timing of the trigger signal. Thus, it is possible to reliably sample and hold a series of data existing in the primary storage medium, and to transfer the data to the secondary recording medium and save it.

  In the semiconductor integrated circuit of the present invention, a sixth port to which control data is input, and region definition data generation for internally generating the region definition data based on the control data input from the sixth port Means may be further included. According to such a configuration, by providing appropriate control data to the sixth port from the outside, it is possible to easily set an appropriate storage area according to various sampling data.

  At this time, both the data indicating the capacity of the first storage area and the data indicating the capacity of the second storage area are included in the control data from the outside, and the area definition data generating means 2 The area definition data may be generated based on one data. According to such a configuration, the capacity of the first storage area and the capacity of the second storage area can be individually set to arbitrary sizes by giving control data from the outside.

  The external control data includes the data indicating the capacity of the first storage area, but does not include the data indicating the capacity of the second storage area. The area definition data may be generated based only on data indicating the capacity of one area. According to such a configuration, by providing an appropriate correlation between the capacity of the first storage area and the capacity of the second storage area in advance, the control data indicating only the capacity of the first storage area It is possible to appropriately set the first storage capacity and the second storage capacity simply by giving.

  In the two inventions described above, the storage capacity of the first storage area is preferably an integral multiple (more preferably twice) of the storage capacity of the second storage area. In this way, when image data, audio data, or the like divided into frame units is targeted, the first storage area can be obtained by making the capacity of the second storage area correspond to the size of the frame, for example. The collation process between the data strings of the data stored in the data storage and the data stored in the second storage area is facilitated.

  Further, as described above in connection with the sample-and-hold method, the first and second write control means are used in order to cope with the case where each of a series of continuous data is indefinite length data. Includes means for measuring the data length of individual indefinite-length data that arrives before and after, means for adding control data including the measured data length to each of the indefinite-length data to be written in the storage area, and May be included.

  Furthermore, in order to cope with the case where each of a series of data that arrives continuously is data divided in units of frames, the first write control means stores the series of data that arrives in the first storage area. The operation of writing while cyclically incrementing the address is continued until the frame being written is completed when the trigger signal arrives, and the second write control means has a series of operations that have arrived since the arrival of the trigger signal. The operation of writing the data in the second storage area may be started after the frame being written ends when the trigger signal arrives.

  According to the sample and hold method and apparatus of the present invention, it is possible to reliably sample and hold only a series of data existing within a predetermined section before and after the arrival timing of a predetermined trigger signal, among a series of continuously arrived data. be able to.

  Further, according to the sample and hold method and apparatus of the present invention, the storage capacity of the required storage medium is kept to the minimum necessary, and a series of data and trigger signal included in a predetermined section before the arrival timing of the trigger signal is obtained. A series of data included in a predetermined section after the arrival timing can be clearly separated and managed independently.

  Furthermore, according to the semiconductor integrated circuit for sample and hold of the present invention, in a state where the primary storage medium and / or the secondary storage medium are respectively connected to the predetermined ports, a series of data to be sampled is stored in the first port. In addition, the first and second storage areas are appropriately defined in the primary storage medium only by giving a predetermined trigger signal to the second port, respectively. A data string in a certain interval immediately before the arrival of the trigger signal is stored in the storage area, and a data string in a certain interval immediately after the arrival of the trigger signal is stored in the second storage area of the primary storage medium, respectively. After being transferred to the secondary storage medium, these data strings stored in the primary storage medium or the secondary storage medium can be read out from a predetermined port.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Needless to say, the technical scope of the present invention is not limited by the following embodiments, but only by the description of the scope of claims.

  A block diagram of a sample and hold device according to the present invention is shown in FIG. As shown in the figure, this sample and hold device includes a semiconductor integrated circuit 1 specially designed for sample and hold, a DRAM 2 that functions as a primary storage medium, and a flash memory (FLASH) that functions as a secondary storage medium. 3 and a clock oscillator 4 for supplying an operation clock to the semiconductor integrated circuit 1.

  The semiconductor integrated circuit 1 is provided with a plurality of external ports. The port P11 is a port to which a series of data to be sampled is input in parallel. In the figure, parallel input data is indicated by a symbol P-DATA (IN). The port P12 is a port to which a series of data to be sampled is input serially. In the figure, S-DATA (IN) is parallel input data. Thus, in this semiconductor integrated circuit 1, a series of data to be sampled can be input as both parallel data and serial data.

  The port P2 is a port to which a predetermined trigger signal is input. In the figure, TRG is a trigger signal. As will be described in detail later, in this semiconductor integrated circuit 1, within a predetermined period before and after arrival of the trigger signal TRG in a series of sample target data strings input from either the port P11 or the port P12. Only existing data strings can be sampled and held.

  The port P3 is a port for connecting the DRAM 2 which is a primary storage medium. As will be described in detail later, as a result of executing the sample and hold process, a data string existing within a certain period before and after the arrival of the trigger signal TRG is first stored in the DRAM 2 as the primary storage medium. The power supply PW2 for the DRAM 2 is supplied from the semiconductor integrated circuit 1.

  The port P4 is a port for connecting a flash memory (FLASH) 3 that is a secondary storage medium. As will be described in detail later, the sample hold data stored in the DRAM 2 is transferred and stored in the flash memory (FLASH) 3 upon completion of the sample hold processing. The power supply PW3 of the flash memory (FLASH) 3 is also supplied from the semiconductor integrated circuit 1.

  The port P5 is a port for reading hold data to the outside. In the figure, H-DATA (OUT) is the read sample hold data. In this embodiment, the sample hold data H-DATA (OUT) is read from the flash memory (FLASH) 3 and output from the port P5 to the outside.

  The port P6 is a port for sending control data and the like from the personal computer (PC) to the semiconductor integrated circuit 1. In this embodiment, USB is used as a communication method with a personal computer (PC), but the communication method is not limited to this.

  The port P 7 is a port for supplying the operation clock CLK 0 generated by the clock oscillator 4 to the semiconductor integrated circuit 1. That is, as will be described in detail later, the semiconductor integrated circuit 1 is composed of a clock synchronous wired logic circuit, and an operation clock CLK0 required for the operation is supplied from the clock oscillator 4 via the port P7. Is done. The power supply PW4 for the clock oscillator 4 is also supplied from the semiconductor integrated circuit 1 side.

  Next, typical external terminals will be described. The external terminal T1 is a terminal for supplying the power supply VDD to the semiconductor integrated circuit 1. The power supply VDD supplied from the external terminal T1 is supplied to the power supply control unit 180 inside the semiconductor integrated circuit 1. The power supply control unit 180 outputs four systems of power supplies PW1 to PW4 by performing voltage stabilization and voltage adjustment based on the power supply VDD thus obtained. Among them, the power supply PW1 is supplied to each circuit inside the semiconductor integrated circuit 1. The power supply PW2 is supplied to the DRAM 2 connected to the port P3 as described above. The power supply PW3 is supplied to the flash memory (FLASH) 3 connected to the port P4 as described above. The power source PW4 is supplied to the clock oscillator 4 connected to the port P7 as described above. External terminals T2 and T3 are terminals for externally connecting the supercapacitor 5. The electric charge stored in the supercapacitor 5 is used to hold the four power sources PW1 to PW4 output from the power supply control unit 180 for a predetermined time during a power failure. In this example, even if the power supply VDD is cut off immediately after the trigger signal TRG arrives, the power supplies PW1 to PW4 are normally held at least until the sample hold operation and the transfer operation are completed. Thus, the capacity of the supercapacitor 5 is determined.

  Next, the internal configuration of the semiconductor integrated circuit 1 will be described in detail. The semiconductor integrated circuit 1 includes a memory control unit 110, a control CPU 120, a header addition control unit 130, a data bit control unit 140, a serial / parallel conversion unit 150, and a serial / parallel switching control unit 160. In addition, the OR gate 170 and the power supply control unit 180 (described above) are included, and the interface circuits 101 to 105 are included corresponding to the ports P12, P11, P2 to P7 described above. .

  The memory control unit 110 transfers the parallel input data P-DATA (IN) from the port P11 or the serial input data S-DATA (IN) from the port P12 to the first and second storage areas of the DRAM 2 (details will be described later). A control function for DMA transfer, a control function for DMA transfer (transfer) of data stored in the first and second storage areas of the DRAM 2 to a predetermined area of the flash memory (FLASH) 3, a flash memory (FLASH) ) It is composed of a clock-synchronized wired logic circuit that realizes a control function for reading data stored in the predetermined area 3 from the port P5 to the outside. The memory controller 110 includes a DMA controller (DMAC) 110a and a flash memory (FALSH) 110b. The DMA controller (DMAC) 110a is used for the various data transfer functions described above. The flash memory 110b stores area definition data for defining first and second storage areas in the DRAM 2, area definition data for defining storage areas in the flash memory (FLASH) 3, and the like. . These storage area definition data can be rewritten from an external personal computer (PC) via the control CPU 120, as will be described in detail later. As a result, the semiconductor integrated circuit 1 is provided with versatility capable of supporting an arbitrary data string and sample hold specification. The function of the memory control unit 110 will be described in detail later with reference to the flowcharts of FIGS. 5 and 6.

  The control CPU 120 is mainly composed of a microprocessor, and (1) based on input data from a user while communicating with a personal computer (PC) connected to the port P6 via the USB interface 105. Functions for executing various setting processes, (2) Centrally managing the memory control unit 110, the header addition control unit 130, and the data bit control unit 140, thereby controlling various system support processes. . A flash memory (FLASH) 120 a is built in the control CPU 120. The flash memory (FLASH) 120a stores various types of data captured from a user via a personal computer (PC). The function of the control CPU 120 will be described in detail later with reference to the flowcharts of FIGS.

  The header addition control unit 130 adds header information to each data of the parallel input data P-DATA (IN) supplied from the port P11 or the serial input data S-DATA (IN) supplied from the port P12. (See FIG. 4B). In the figure, 403 is a data portion and 404 is a header portion. The header information added here includes at least numerical information indicating the order of a series of incoming data. The numerical information is cyclically added between a predetermined minimum value and a maximum value, and the process of later reading and organizing the sample hold data is based on the numerical information indicating the data order. Done.

  The data bit control unit 140 is under the control of the control CPU 120 and realizes data bit control for the header addition control unit 130, the serial / parallel conversion unit 150, the parallel interface 101, and the serial interface 102. By realizing these data bit controls, the header addition control unit 130 performs addition of header information on the designated bit, and the serial / parallel conversion unit 150 performs serial / parallel conversion on the data bit string. Appropriately, the interface 101, 102 properly recognizes the input data bits.

  The serial / parallel converter 150 is a circuit for converting serial input data S-DATA (IN) supplied to the port P12 and taken in via the serial interface 102 into parallel data. The parallel data thus obtained is ORed. The data is supplied to the header addition control unit 130 described above via the gate 170.

  The serial / parallel switching control unit 160 is a circuit that selectively activates either the parallel interface 101 or the serial interface 102 under the control of the data bit control unit 140. When the serial / parallel switching control unit 160 functions appropriately, the input data handled by the semiconductor integrated circuit 1 can be set to either serial or parallel.

  The clock control unit 190 receives the operation clock (CLK0) supplied from the clock oscillator 4 via the port P7, the clock CLK (P) fetched from the parallel interface 101, and the clock CLK (S) fetched from the serial interface 102. ) And generate and output n control clocks CLK1 to CLKn. Control clocks CLK1 to n obtained in this way are supplied to each circuit in the semiconductor integrated circuit 1 as necessary, and contribute to the normal operation of the clock synchronous wired logic circuit. The clock controller 190 includes a phase locked loop circuit (PLL) 190a. The phase-locked loop circuit (PLL) 190a synchronizes various clocks or contributes to the frequency synthesis operation.

  Next, the function of the control CPU 120 will be described in more detail with reference to the flowcharts of FIGS. As described above, the control CPU 120 is configured to mainly execute system support processing and various setting processing.

  A general flowchart showing the operation of the control CPU is shown in FIG. In the same figure, when processing is started by turning on the power (Power on), it communicates with a personal computer (PC) connected to the port P6 via the USB interface 105, and information sent from the personal computer (PC) is displayed. This is received and stored in the flash memory 120a (step 201). This information also includes control information of the operation mode flag, which allows the operation mode of the control CPU 120 to be switched from the personal computer (PC) side. Subsequent to this reception process (step 201), an operation mode determination process is executed (step 202). If the operation mode is determined to be a setting mode, various setting processes (step 203) are executed. If the mode is determined, system support processing (step 204) is executed. In the various setting processes (step 203), setting processes according to the arrival speed of the sample target data, the data format, the pre-trigger hold period, the post-trigger hold period, and other various sample hold specifications are executed. As will be described in detail later, the various setting processing (step 203) includes region definition data generation processing relating to the first storage region and the second storage region. On the other hand, in the system support process (step 204), as described above, the system in the semiconductor integrated circuit 1 is supported by comprehensively managing the memory control unit 110, the header addition control unit 130, and the data bit control unit 140. Is executed.

  A detailed flowchart of the various setting processes (step 203) is shown in FIG. This flowchart shows only the storage area definition data generation process in various setting processes. When the processing is started in the figure, the command word is read out from the received data from the personal computer (PC) and is decoded (step 301). Here, only when it is determined that the decoded instruction is a storage area definition instruction (YES in step 302), the following processing is executed, whereas when it is determined that it is another instruction (step 302). In step 302 NO), the processing of the corresponding other command is executed.

  If it is determined that the instruction is a storage area definition command (YES in step 302), then the type of designation method is determined. In this embodiment, with respect to sample-holding a data string existing in a predetermined section before and after the trigger timing, both the front and rear sections are individually specified to define a storage area, and only the front section For the rear section, it is possible to select two designation methods when the system automatically sets according to a preset algorithm. If it is determined that both sides are designated (step 303), then the type of use data is determined (step 304). In this example, it is possible to select whether to specify the data sequence of the front interval and the rear interval of the trigger timing by specifying “time” or “data count”. Here, when the type of use data is determined as “time”, conversion processing from time to the number of data is performed (step 305), whereas when the use data type is determined as “number of data”, The usage data is left as it is. Subsequently, a first storage area is defined in the DRAM 2 based on the number of front data obtained in this way (step 306). The definition of the first storage area is performed by calculating the start address AD11 and the end address AD12 of the first storage area 401, as shown in FIG. Subsequently, a second storage area in the DRAM 2 is defined based on the rear data number. The definition of the second storage area is performed by obtaining the start address AD21 and the end address AD22 of the second storage area 402 in the DRAM 2, as shown in FIG. The storage area definition data (AD11, AD12, AD21, AD22) obtained by the above processing (steps 306, 307) is sent to the memory control unit 110 and stored in the flash memory 110b in the memory control unit 110. Thereafter, the memory controller 110 appropriately refers to the storage area definition data (AD11, AD12, AD21, AD22) stored in the flash memory 110b, thereby transferring data from the data input ports P11, P12 to the DRAM 2, Data transfer processing from the DRAM 2 to the flash memory (FLASH) 3 and data transfer processing from the flash memory (FLASH) 3 to the data output port P5 are executed.

  Next, the operation of the memory control unit 110 will be described. A general flowchart showing the operation of the memory control unit is shown in FIG. In the figure, when the process is started, it is determined whether a sample hold instruction is given from the control CPU 120 (step 501) or a read instruction is given (step 502), and a sample hold instruction is given. In this case (step 501 YES), sample hold processing (step 503) is executed, whereas when a read instruction is given (step 502 YES), hold data read processing (step 504) is executed. In the hold data reading process (step 504), the hold data H-DATA (OUT) stored in the flash memory 3 is transferred to the data output port P5.

  A detailed flowchart of the sample and hold process is shown in FIG. When the process is started in the figure, a formatting process is first executed to format the DRAM 2 and the flash memory (FLASH) 3 (step 601).

  Subsequently, after setting the first address AD11 and the end address AD12 of the first storage area to the DMA controller (DMAC) 110a, the DMA controller (DMAC) 110a is started (step 603), and a header is added. Processing for DMA transfer of the data string fetched from the control unit 130 to the first storage area 401 in the DRAM 2 is started. At this time, if the parallel port P11 is selected by the operation of the S / P switching control unit 160, the parallel input data P-DATA (IN) is transferred to the first storage area 401 in the DRAM 2. Conversely, if the serial input port P12 is selected, the serial input data S-DATA (IN) is transferred to the first storage area 401 in the DRAM 2. In this way, a series of data strings coming from the parallel input port P11 or the serial input port P12 is sequentially written from the start address AD11 to the end address AD12 of the first storage area 401 shown in FIG. It will be. On the other hand, during the execution of the DMA transfer process, the arrival of the trigger signal TRG (step 604) and the confirmation of the coincidence between the transfer address AD and the end address AD12 (step 605) are always performed, and the transfer address AD is stored in the first storage area. Whenever it matches the tail address AD12 of 401 (YES in step 605), the DMA controller (DMAC) 110a is restarted (step 603). As a result, when data writing from the start address AD11 to the end address AD12 is completed in the first storage area 401, the write address returns to the start address AD11 again, and the overwrite process on the first storage area 401 is repeated. Will be executed. That is, the data string coming from the data input port P11 or P12 is cyclically incremented by the write address AD with respect to the first storage area 401 defined in the DRAM 2 by the action of the memory control unit 110. As the data is written, so-called FIFO (First In First Out) processing is performed.

  In this state, when the trigger signal TRG comes to the port P2 and the arrival of the trigger is confirmed (step 604 YES), the start address AD21 and the end address AD22 of the second storage area 402 are sent to the DMA controller (DMAC) 110a. Is set (step 606), the DMA controller (DMAC) 110a is activated (step 607), and the DMA transfer processing for the second storage area 402 is started. Thus, the data string supplied to the data input port P11 or P12 is transferred and stored in the second storage area 402 in the DRAM 2 after passing through the header addition control unit 130. Thereafter, when the transfer destination address AD coincides with the end address AD22 of the second storage area 402 (YES in Step 608), the transfer process to the second storage area 402 in the DRAM 2 ends.

  Thus, the first storage area 401 stores a series of data in a predetermined section before the arrival of the trigger signal TRG, whereas the second storage area 402 stores in the predetermined section after the arrival of the trigger signal TRG. Data will be stored.

  Subsequently, a series of data in a predetermined section before and after the trigger arrival stored in the first storage area 401 and the second storage area 402 in the DRAM 2 is transferred (transferred) to a predetermined area in the flash memory (FLASH) 3. And saved. Thereafter, even if the power is turned off, a series of data in the flash memory (FLASH) 3 is surely stored.

  Thereafter, returning to FIG. 5, if a read instruction is given from a personal computer (PC) or the like (YES in step 502), hold data read processing (step 504) is executed and stored in a predetermined area in the flash memory 3. The hold data H-DATA (OUT) is read out from the output port P5. At this time, if the data in the flash memory 3 is rearranged in the order of arrival based on the header information (header part 403) and then read out from the output port 5 as hold data H-DATA (OUT), then This eliminates the trouble of rearranging the hold data, and makes it easier to handle the hold data.

  In this embodiment, since the supercapacitor 5 is connected between the external terminals T2 and T3, even if the power supply VDD supplied to the external terminal T1 is cut off, 4 is output from the power supply control unit. The power supplies PW1 to PW4 of the system are normally held until at least after the trigger signal arrives, data writing to the second storage area 402 and data transfer from the DRAM 2 to the flash memory (FLASH) 3 are completed. Therefore, even if this sample hold device is used as a vehicle accident recording device, for example, even if a trigger occurs due to an accident and the power is cut off at the same time, various data at the time of the accident Sample and hold for a predetermined period before and after, and transfer and store this in the flash memory 3 to help investigate the cause of the accident The ability.

  FIG. 7 is a diagram for explaining the operation of the present invention. Assume that arbitrary analog data arrives in time series as shown in FIG. At this time, as shown in FIG. 5B, for example, when the trigger signal is generated when the value of the input data exceeds a predetermined threshold value TH, as shown in FIG. Only the data string existing in the section of T1 seconds immediately before arrival and T2 seconds immediately after the trigger is sampled and held as shown in FIG. In this example, the relationship of T1 = 2 × T2 is set. Therefore, if it is used as a vehicle accident recording device, etc., a trigger signal is generated by an airbag start signal simultaneously with the accident, and if a sample hold device is started, a series of data relating to T1 seconds before the accident and T2 seconds after the accident is obtained. Since the sample and hold can be stored in the flash memory (FLASH) 3, if the device is housed in a relatively robust case, the stored data in the flash memory (FLASH) 3 can be read after the accident to investigate the cause of the accident. Can be useful.

  In the above embodiment, the flash memory (FLASH) 3 is provided as the secondary storage medium to ensure the storage reliability of the sample hold data. For example, the capacity of the supercapacitor 5 is increased, If the storage data of the DRAM 2 can be held, for example, for one week to one month, it is not always necessary to provide a secondary storage medium. In that case, the transfer process (step 609) from the DRAM 2 to the flash memory (FLASH) 3 can be omitted in the detailed flowchart of the sample hold process shown in FIG.

  As described above, according to this embodiment, the data string to be sampled is port P11 or P12, the trigger signal is port P2, the DRAM 2 is port P3, the flash memory (FLASH) 3 is port P4, Only by connecting the clock oscillator 4 to the port P7, the first storage area 401 and the second storage in the DRAM 2 are transferred only to a series of data strings existing in a predetermined section before and after the arrival of the trigger signal TRG. It is possible to sample and hold the area 402 and immediately save the contents to the flash memory (FLASH) 3. Thereafter, if a read command is given from the personal computer (PC), the sample hold data stored in the flash memory (FLASH) 3 can be read out to the port P5 by the action of the memory control unit 110. Each piece of data read at this time includes header information by the action of the header addition control unit 130, and a numerical value indicating the order of the data is added to the header information. The output sample hold data can be easily rearranged in time series.

  The DRAM 2, the flash memory (FLASH) 3, and the clock oscillator 4 are all supplied with power from the power control unit 180 in the semiconductor integrated circuit 1, and the power control unit 180 holds the power sources PW1 to PW4 for a certain time after a power failure. Therefore, even when this sample and hold device is applied to, for example, a vehicle accident recording device, the trigger signal is generated by an accident and the sample and hold process is started. Even if the power supply VDD is interrupted, the operations of the DRAM 2, the flash memory (FLASH) 3, and the clock oscillator 4 are all maintained normally. Can be made.

  Moreover, since the control CPU 120 including a microprocessor is built in the semiconductor integrated circuit 1 to enable communication with a personal computer (PC), switching of the input ports (P11, P12), setting of the number of data bits, and storage are performed. Various settings such as area setting can be easily performed based on input data from a personal computer (PC), and a highly versatile semiconductor integrated circuit can be realized.

  In particular, in this embodiment, as shown in FIG. 3, a port P6 to which control data is input and a region in which region definition data is internally generated based on the control data input from the port P6. Since the control CPU 120 as the definition data generation means is provided, an appropriate storage area can be easily set in accordance with various sampling data by providing appropriate control data to the sixth port from the outside. .

  That is, both the data indicating the capacity of the first storage area and the data indicating the capacity of the second storage area are included in the control data from the outside, and the area definition data generating means generates the two data. If the area definition data is generated based on (step 303 “both sides”), the capacity of the first storage area and the capacity of the second storage area can be individually set by giving control data from the outside. It can be set to any size. On the other hand, although the data indicating the capacity of the first storage area is included in the control data from the outside, the data indicating the capacity of the second storage area is not included. If the area definition data is generated based only on the data indicating the capacity of the area (step 303 “front side”), an appropriate value is previously set between the capacity of the first storage area and the capacity of the second storage area. By providing the correlation, the first storage capacity and the second storage capacity can be appropriately set only by giving control data indicating only the capacity of the first storage area. Furthermore, since “time” and “number of data” can be selectively used as types of use data, it is possible to select appropriate use data according to the type of analysis target data.

  4, regarding the capacity relationship between the first storage area 401 and the second storage area 402, the storage capacity of the first storage area 401 is an integral multiple of the storage capacity of the second storage area 402 (from (Preferably twice). In this way, when image data, audio data, or the like divided into frame units is targeted, the first storage area can be obtained by making the capacity of the second storage area correspond to the size of the frame, for example. The collation process between the data strings of the data stored in the data storage and the data stored in the second storage area is facilitated.

  Next, another embodiment (second embodiment) of the sample hold device according to the present invention will be described with reference to FIGS. FIG. 10 shows a configuration diagram (second embodiment) of a sample hold device (semiconductor integrated circuit) according to the present invention. In this embodiment, the function as the sample and hold device is realized by software by the CPU.

  As shown in FIG. 10, the semiconductor integrated circuit 1a includes a CPU 1001 incorporating a microprocessor, a system ROM, etc., a working memory 1002 constituted by a RAM, a setting information memory 1003 constituted by a flash memory, a PC A communication control unit 1004 that supports USB for communication with a (personal computer), a data input interface 1005 for inputting serial data, a data input interface 1006 for inputting parallel data, and sampled and held data A data output interface 1007 for outputting a column to the outside, a trigger input interface 1008 for inputting an external trigger signal TRG, a primary memory interface 1009 for connecting to an external DRAM 2, an external And a secondary memory interface 1010 for connection with the LASH memory 3. Reference numeral 1011 denotes a CPU bus.

  In the DRAM 2 as the primary memory, a temporary storage area shown in FIG. 11A, a BEFORE (hereinafter simply referred to as “B”) area and an AFTER (hereinafter simply referred to as “A” shown in FIG. 11B). A region) is provided. In this example, the ratio of the storage capacity of the B area to the A area to the temporary storage area is set to about 2 to 1 to 0.5.

  As will be described in detail later, in the temporary storage area, as shown in FIG. 11 (a), unit data 1101 of indefinite length is densely stored without a gap from the beginning, and similarly, the B area The unit data 1102 of indefinite length is densely stored in the area 1103 and the area A 1104 without leaving a gap from the beginning.

  As shown in FIG. 12A, the unit data 1101 in the temporary storage area has a format in which start bits 1101a, data 1101b, and end addresses 1101c are arranged in order. The unit data 1102 in the B area and the A area has a format in which a start bit 1102a, data 1102b, an end address 1102c, and control data 1102d are sequentially arranged as shown in FIG. The control data 1102d includes a code indicating the data length of the unit length data, a trigger code indicating that the trigger signal TRG is input from the outside, the arrival order of the unit length data, and the like. Relying on these codes, data reading or reproduction control is performed.

  FIG. 13 shows a general flowchart of sample hold processing executed by the CPU. In the figure, when the process is started by turning on the power (Power on), a program load process (Step 1301) and an initialization process (Step 1302) are executed in sequence, thereby reading the control program from the setting information memory 1003. In addition, development processing on the working memory 1002, initialization processing of the DRAM 2 and the FLASH memory 3, and the like are performed.

  Subsequently, referring to the internal trigger (step 1304), on condition that this is not in the ON state (step 1305 NO), the B area process (step 1303) is repeatedly executed. If it is confirmed that the internal trigger is turned on during this period (step 1305 YES), the area A process (step 1306) is executed for a predetermined time. When the A area process (step 1306) is completed, the storage process (step 1307) is subsequently executed, and the sample hold process is completed.

  Details of the B area process (step 1303) are shown in the flowchart of FIG. In this figure, when processing is started, the input data to be sampled is awaited (steps 1401, 1402 YES), and the type of the data (MPEG4, TCP / IP, CDMA, etc.) is determined (step). 1403) Further, automatic setting processing (step 1404) for the apparatus configuration corresponding to the determined data type is executed.

  Subsequently, while monitoring incoming input data (step 1405), if the start point has arrived (YES in step 1406), input data capture processing (step 1407), temporary storage area (see FIG. 11A) The data length measurement (count) process (step 1409) is performed while repeatedly executing the storage process (step 1408). In the meantime, if arrival of the endpoint is confirmed (step 1410 YES), control data (including the measured data length) is generated (step 1411), and this is stored in the temporary storage area. Is added (step 1412), and is written into area B by FIFO processing (step 1403). The above processing (steps 1401 to 1413) is repeatedly executed until the internal trigger is turned on (YES in step 1305).

  A detailed flowchart of the interrupt processing by the external trigger is shown in FIG. For example, when the external trigger signal TRG is turned on during execution of the above-described B area processing, monitoring of input data is continued by the interrupt processing (step 1501), and if there is no input data (step 1502 NO), the internal trigger is immediately performed. Is turned on (step 1508), but when input data exists, that is, when an external trigger is turned on in the middle of one frame data (YES in step 1502), input data capture processing (step 1503), the process of saving to the temporary storage area (step 1504), and the data length counting (measurement) process (step 1505) are resumed. Thereafter, these processes (steps 1503 to 1505) are performed until the end point arrives. It is repeatedly executed during the period (NO in step 1506). If arrival of the endpoint is confirmed during that time (step 1506 YES), control data generation processing (step 1507) and control data addition processing (step 1508) are performed in the same manner as the B area processing (FIG. 14) described above. , FIFO processing to the B area (step 1509) is executed in sequence, and all the data that arrives is written into the B area until the frame is completed, and then the internal trigger flag is turned on and the processing ends. . That is, when the external trigger is turned on during the writing of the frame data to the B area, the data writing to the B area is continued until the end of the frame without immediately shifting to the A area. .

  On the other hand, when the internal trigger flag is turned on in this way, the process returns to FIG. 13, which is detected by the determination process (step 1305), and thereafter, the area A process (step 1306) is executed. Become.

  A detailed flowchart of the A area processing is shown in FIG. In the figure, when the processing is started, first, a timer for monitoring the execution time of the area A processing is started (step 1601), then the arrival of input data is monitored (step 1602), and the arrival of the start point is detected. Waiting for confirmation (YES in step 1603), input data fetching processing (step 1604), saving processing in a temporary storage area (step 1605), and data length counting (measurement) processing (step 1606) are repeatedly executed. Meanwhile, when the arrival of the endpoint is confirmed (step 1607), the control data generation process (step 1608), the control data addition process (step 1609), and the writing process to the area A (step 1610) are sequentially performed. Execute. The above processes (steps 1602 to 1610) are repeatedly executed until the timer expires. When the time expires (YES in step 1611), all the processes are completed.

  According to the second embodiment, even if sample target data is indefinite length data (for example, MPEG4 data coming from a video camera), the data length of each data is measured and the measured value is controlled. Since the data is attached to each data and stored in the memory, the memory capacity can be effectively utilized without causing any trouble in reading or reproducing the data string even if the data string is densely packed in the memory. In addition, even if the external trigger signal is turned on during the writing of one frame, the writing of the data of the frame being written at that time is continued until the end of the frame. Both the last data in the BEFORE area and the first data in the AFTER area are stored in a complete state, and the data in the BEFORE area and the data in the AFTER area can be made completely separate files. When used for investigating the cause of the accident, it is possible to guarantee the reliability of data analysis before and after the accident.

  Finally, some specific application examples of the sample hold IC according to the present invention will be described. FIG. 8 shows a configuration diagram of a data recorder to which the sample hold IC according to the present invention is applied. In the figure, for example, 801 is a probe that detects a feature quantity to be measured such as voltage, temperature, pressure, and flow rate, 802 is an input circuit that generates an electrical signal corresponding to the feature quantity based on a signal obtained from the probe, and 803 An AD / I2S conversion circuit that performs the function of digitizing an analog signal obtained from the input circuit and sending the digitized signal to the I2S bus, 804 is a sample hold IC according to the present invention, and 805 is a primary storage medium A functioning DRAM, 806 is a flash memory that also functions as a secondary storage medium, 807 is an I2S / USB conversion circuit that receives sample hold data sent from the sample hold IC 804 onto the I2S bus and sends it to the USB bus, 808 Is a personal computer that receives and processes sample and hold data 809 various status signals (e.g., detection target peripheral temperature, pressure, volume, vibration signal indicating the like) S1-Sk are trigger generation circuit which generates a trigger signal TRG at the time that satisfies the predetermined condition.

  According to this application example, the feature amount data detected by the probe 802 is always stored in the first storage area of the DRAM 805 while cyclically increasing the address. When the state signals S1 to Sk satisfy a predetermined condition, a trigger signal TRG is generated from the trigger generation circuit 809 and supplied to the sample hold IC. Then, the incoming series of feature data is written not in the first storage area but in the second storage area. After that, the data strings stored in the first and second storage areas are transferred to the flash memory 806, which is a secondary storage medium. Thereafter, the data string stored in the flash memory 806 (data string within a predetermined period before and after the arrival timing of the trigger signal) is read out and taken into the personal computer 808. Such a data recorder is mounted on the vehicle and an appropriate probe is used to constantly record the vehicle speed, accelerator opening, engine state, brake state, etc. If the trigger signal is generated by a signal highly correlated with the vehicle accident, valuable data at the time of the accident can be stored.

  Next, FIG. 9 shows a configuration diagram of a monitoring apparatus to which the sample hold IC according to the present invention is applied. In the figure, reference numeral 901 denotes a camera including a photographing lens and an image sensor, reference numeral 902 denotes a signal processing circuit for processing a video signal from the camera, reference numeral 903 denotes a compression circuit (codec) for compressing data obtained from the signal processing circuit, and reference numeral 904. Is a DATA / I2S conversion circuit for sending data obtained from the compression circuit onto the I2S bus, 905 is a sample hold IC according to the present invention, 906 is a DRAM functioning as a primary storage medium, and 907 is also functioning as a secondary storage medium A flash memory 908, an I2S / USB conversion circuit that receives sample hold data sent from the sample hold IC onto the I2S bus and sends it to the USB bus, 909 a personal computer that receives and processes the sample hold data, and 910 Various status signals (for example, detection Object near the temperature, pressure, volume, vibration signal indicating the like) S1-Sk are trigger generation circuit which generates a trigger signal TRG at the time that satisfies the predetermined condition. In this example, the status signal includes a focus error signal acquired from the camera 901, a signal from a switch 911 that is placed in the monitoring target area and operated by an intruder, and a movement of the camera itself built in the camera. A signal from an acceleration sensor (not shown) that detects the sound, a signal from a microphone (not shown) that collects sound in the monitoring target area, a video signal itself from the camera, and the like.

  According to this application example, the image data acquired by the camera 901 is normally stored in the first storage area of the DRAM 906 while the address is cyclically incremented. When the state signals S1 to Sk satisfy a predetermined condition due to the appearance of an intruder in the monitoring target area, a trigger signal TRG is generated from the trigger generation circuit 910 and supplied to the sample hold IC 905. Then, a series of incoming image data is written not in the first storage area but in the second storage area. Thereafter, the image data strings stored in the first and second storage areas are transferred to the flash memory 907 which is a secondary storage medium. Thereafter, the image data sequence stored in the flash memory 907 (the image data sequence within a predetermined period before and after the arrival timing of the trigger signal) is read out and taken into the personal computer 9098. If such a monitoring device is applied to, for example, an entrance crime prevention surveillance system, when an intruder appears in front of the entrance, a series of images including the behavior of the intruder so far can be stored.

  As described above, according to the present invention, for example, when a security camera is attached to the entrance to monitor a visitor, the arrival of the visitor is detected based on a separately provided sensor or a change in the image itself, Not only video data for a certain period after detection, but also video data for a certain period before detection can be saved, and by reproducing the video based on both of these saved video data, The situation can be observed in more detail.

  Further, according to the present invention, while monitoring the state of the object based on measurement data from a plurality of measuring instruments, the feature values indicated by the measurement data coincide with the feature values at the time of occurrence of an event assumed in advance. As a trigger, you can save not only the measurement data for a certain period after the trigger occurs, but also the measurement data for a certain period before the trigger occurs. Effective use for verification and prediction of event occurrence.

  Furthermore, according to the present invention, while monitoring the state of the vehicle based on measurement data from a plurality of measuring instruments, it is confirmed that the feature values indicated by the measurement data match the feature values at the time of an accident that are assumed in advance. As a trigger, not only the measurement data for a certain period after the trigger occurs, but also the measurement data for a certain period before the trigger occurs can be saved, and both saved measurement data can be used effectively for investigation of the cause of the accident. it can.

It is a block diagram of the sample hold device concerning the present invention. It is a general flowchart which shows operation | movement of CPU for control. It is a detailed flowchart of various setting processes. It is explanatory drawing which shows the memory map and storage data format of a primary storage medium. It is a general flowchart which shows operation | movement of a memory control part. It is a detailed flowchart of a sample hold process. It is operation | movement explanatory drawing of this invention. 1 is a configuration diagram of a tape recorder to which a sample hold IC according to the present invention is applied. FIG. It is a block diagram of the monitoring apparatus to which the sample hold IC which concerns on this invention was applied. It is a block diagram (2nd Embodiment) of the sample hold apparatus which concerns on this invention. It is explanatory drawing of the data arrangement | sequence of a primary memory. It is explanatory drawing of a unit data format. It is a general flowchart of a sample hold process. It is a detailed flowchart of a B (BEFORE) area process. It is a detailed flowchart of the interruption process by an external trigger. It is a detailed flowchart of A (AFTER) area processing.

Explanation of symbols

1,1a Semiconductor integrated circuit 2 DRAM
3 Flash memory (FLASH)
4 clock oscillator 5 super capacitor 101-105 interface 110 memory control unit 110a DAM controller (DAMC)
110b Flash memory (FLASH)
120 CPU for control
120a Flash memory (FLASH)
DESCRIPTION OF SYMBOLS 130 Header addition control part 140 Data bit control part 150 Serial / parallel conversion part 160 Serial / parallel switching control part 170 OR gate 180 Power supply control part 401 1st storage area 402 2nd storage area 403 Data part 404 Header part CLK0 Operation Clock CLK1 to n Control clock H-DATA (OUT) Sample hold data P11, P12, P2 to P7 Port PW1 Power supply for main unit PW2 Power supply for DRAM PW3 Power supply for flash memory (FLASH) PW4 Power supply for oscillator P-DATA (IN) Parallel input data S-DATA (IN) Serial input data T1 Power supply VDD external terminal T2, T3 Supercapacitor external terminal TRG Trigger signal 801 Probe 802 Input circuit 803 AD / I2S Circuit 804 sample-and-hold IC
805 DRAM
806 Flash memory 807 I2S / USB conversion circuit 808 Personal computer 809 Trigger generation circuit S1 to Sk Status signal 901 Camera (including lens and image sensor)
902 signal processing circuit 903 codec
904 DATA / I2S conversion circuit 905 Sample hold IC
906 DRAM
907 Flash memory 908 I2S / USB conversion circuit 909 Personal computer 910 Trigger generation circuit 1001 CPU
1002 Working memory 1003 Setting information memory 1004 Communication control unit 1005 Serial data input interface 1006 Parallel data input interface 1007 Data output interface 1008 Trigger input interface 1009 Primary memory interface 1010 Secondary memory interface 1101, 1102 Unit data 1101a, 1102a Start bit 1101b , 1102b Data 1101c, 1102c End address 1102d Control data 1103 BEFORE area 1104 AFTER area

Claims (33)

A method for sample-holding only a series of data existing in a predetermined section before and after the arrival timing of a predetermined trigger signal among a series of data that continuously arrives,
A first storage medium is provided in which a first storage area corresponding to a front section of the trigger signal arrival timing and a second storage area corresponding to a rear section of the trigger signal arrival timing are defined. Steps,
A second step of continuing an operation of writing a series of incoming data in the first storage area while cyclically incrementing addresses until the trigger signal arrives;
Instead of waiting for the trigger signal to arrive and stopping writing data to the first storage area, a third series of data written after the arrival of the trigger signal is written to the second storage area. And the steps
A method for sample-holding a data string, comprising: Waiting for the completion of the third step, further comprising a fourth step of transferring the data written in the first and second storage areas of the primary storage medium to the secondary storage medium. The data string sample and hold method according to claim 1. 2. The data string sample and hold method according to claim 1, wherein the primary storage medium is a non-volatile storage medium suitable for high-speed storage such as an opto-memory, or a volatile storage medium such as a power-backed DRAM. The data according to claim 2, wherein the primary storage medium is a volatile storage medium suitable for high-speed storage such as a DRAM, and the secondary storage medium is a nonvolatile storage medium such as a flash memory or a hard disk. Sample hold method for the column. 5. The data string sample and hold method according to claim 1, wherein the storage capacity of the first storage area is an integral multiple of the storage capacity of the second storage area. 6. The data string sample and hold method according to claim 5, wherein the storage capacity of the first storage area is twice the storage capacity of the second storage area. Each of a series of data that arrives continuously is indefinite length data, and the first and second steps include:
Measuring the data length of individual indefinite-length data that arrives one after the other,
The sample hold method according to claim 1, further comprising: adding control data including the measured data length to each of the indefinite length data to be written in the storage area. Each of a series of data that arrives continuously is data divided in units of frames, and in the first step, the operation of writing the series of data that arrives in the first storage area while cyclically incrementing the address is , Which continues until the frame being written ends when the trigger signal arrives,
In the second step, the operation of writing a series of data that has arrived after the arrival of the trigger signal to the second storage area is started after the frame being written ends when the trigger signal arrives. The sample and hold method according to claim 1, wherein: An apparatus for sample-holding only a series of data existing in a predetermined section before and after the arrival timing of a predetermined trigger signal among a series of data that continuously arrives,
A primary storage medium;
Area definition data for defining, in the primary storage medium, a first storage area corresponding to a front section of the trigger signal arrival timing and a second storage area corresponding to a rear section of the trigger signal arrival timing. Area definition data storage means for storing
First write control means for continuing an operation of writing a series of incoming data into the first storage area defined by the area definition data while cyclically incrementing an address until the trigger signal arrives;
Instead of waiting for the trigger signal to arrive and stopping writing data to the first storage area, a series of data that has arrived after the arrival of the trigger signal is defined by the area definition data. Second write control means for writing to two storage areas;
A sample-and-hold apparatus for a data string, comprising: A secondary storage medium;
10. The data string sample according to claim 9, further comprising data transfer control means for transferring data written in the first and second storage areas of the primary storage medium to the secondary storage medium. Hold device. 10. The data string sample and hold device according to claim 9, wherein the primary storage medium is a non-volatile storage medium suitable for high-speed storage such as an opto-memory, or a volatile storage medium such as DRAM backed up by a power source. The data according to claim 10, wherein the primary storage medium is a volatile storage medium suitable for high-speed storage such as a DRAM, and the secondary storage medium is a nonvolatile storage medium such as a flash memory or a hard disk. Row sample hold device. 13. The data string sample and hold device according to claim 9, further comprising region definition data generating means for generating region definition data internally based on external input data. The input data from the outside includes both data indicating the capacity of the first storage area and data indicating the capacity of the second storage area, and the area definition data generation means includes the two data. 14. The data string sample and hold device according to claim 13, wherein region definition data is generated based on the data. The input data from the outside includes data indicating the capacity of the first storage area, but does not include data indicating the capacity of the second storage area. 14. The data string sample and hold device according to claim 13, wherein region definition data is generated based only on data indicating the capacity of one region. 16. The data string sample-and-hold apparatus according to claim 9, wherein the storage capacity of the first storage area is an integral multiple of the storage capacity of the second storage area. 17. The data string sample and hold device according to claim 16, wherein the storage capacity of the first storage area is twice the storage capacity of the second storage area. Each of a series of data that arrives continuously is indefinite length data, and the first and second write control means include:
Means for measuring the data length of individual indefinite length data that arrives one after the other,
10. The sample hold device according to claim 9, further comprising means for adding control data including the measured data length to each of the indefinite length data to be written in the storage area. Each of a series of data that arrives continuously is data divided in units of frames, and in the first write control means, a series of data that arrives is written into the first storage area while cyclically increasing the address. The operation continues until the frame being written ends when the trigger signal arrives.
In the second write control means, the operation of writing a series of data that has arrived after the arrival of the trigger signal into the second storage area is started after the frame being written is completed when the trigger signal arrives. The sample hold device according to claim 9, wherein A first port into which a series of data to be sampled is input;
A second port to which a predetermined trigger signal is input;
A third port connected to a predetermined storage medium;
A fourth port for outputting a series of sampled and held data;
Area definition data storage means for storing area definition data defining the first storage area and the second storage area in a storage medium connected to the third port;
A trigger signal is input from the second port to write a series of data input from the first port to the first storage area of the storage medium connected to the third port while cyclically moving the address. First writing control means that continues until
Instead of waiting for the trigger signal to be input from the second port and stopping the data writing to the first storage area of the storage medium, a series of data that has arrived since the arrival of the trigger signal is stored. Second write control means for writing to two storage areas;
Data read control means for controlling the data stored in the first storage area and the second storage area of the primary storage medium connected to the third port to the fourth port;
A semiconductor integrated circuit comprising: 21. The semiconductor integrated circuit according to claim 20, wherein the storage medium is a non-volatile storage medium suitable for high-speed storage such as an opto-memory, or a volatile storage medium such as a power-backed DRAM. In addition to the inside of the semiconductor integrated circuit, a storage medium connected externally and a power supply controller that supplies power to an externally connected oscillator that supplies an operation clock to the semiconductor integrated circuit The semiconductor integrated circuit according to claim 20. 23. The semiconductor integrated circuit according to claim 22, further comprising an external terminal for connecting a super capacitor for holding the power supplied from the power control unit for a predetermined time during a power failure. A fifth port to which control data is input;
24. The semiconductor integrated circuit according to claim 20, further comprising region definition data generation means for internally generating the region definition data based on control data input from the fifth port. . A first port into which a series of data to be sampled is input;
A second port to which a predetermined trigger signal is input;
A third port connected to a predetermined primary storage medium;
A fourth port connected to a predetermined secondary storage medium;
A fifth port for reading sampled and held data;
Area definition data storage means for storing area definition data defining the first storage area and the second storage area in a primary storage medium connected to the third port;
A trigger signal is input from the second port to write a series of data input from the first port to the first storage area of the primary storage medium connected to the third port while cyclically moving the address. First write control means that continues until
Instead of waiting for a trigger signal to be input from the second port and stopping writing data to the first storage area of the primary storage medium, a series of data that has arrived after the arrival of the trigger signal is stored in the primary storage medium. Second write control means for writing to the second storage area of
Data transfer control means for transferring data written in the first and second storage areas of the primary storage medium connected to the third port to the secondary storage medium connected to the fourth port;
Data read control means for controlling the data stored in the secondary storage medium connected to the fourth port to the fifth port;
A semiconductor integrated circuit comprising: 26. The semiconductor integrated circuit according to claim 25, wherein the primary storage medium is a volatile storage medium suitable for high-speed storage such as DRAM, and the secondary storage medium is a nonvolatile storage medium such as flash memory or hard disk. . Power supply control for supplying power not only to the inside of the semiconductor integrated circuit but also to externally connected primary and secondary storage media and an externally connected oscillator that supplies an operation clock to the semiconductor integrated circuit 26. The semiconductor integrated circuit according to claim 25, further comprising a portion. 28. The semiconductor integrated circuit according to claim 27, further comprising an external terminal for connecting a super capacitor for holding the power supplied from the power control unit for a predetermined time during a power failure. 29. The semiconductor integrated circuit according to claim 24, wherein the storage capacity of the first storage area is an integral multiple of the storage capacity of the second storage area. 30. The semiconductor integrated circuit according to claim 29, wherein the storage capacity of the first storage area is twice the storage capacity of the second storage area. A sixth port to which control data is input;
31. The semiconductor integrated circuit according to claim 24, further comprising region definition data generation means for internally generating the region definition data based on control data input from the sixth port. . Each of a series of data that arrives continuously is indefinite length data, and the first and second write control means include:
Means for measuring the data length of individual indefinite length data that arrives one after the other,
The semiconductor integrated circuit according to claim 1, further comprising means for adding control data including the measured data length to each of the indefinite length data to be written in the storage area. Each of a series of data that arrives continuously is data divided in units of frames, and in the first write control means, a series of data that arrives is written into the first storage area while cyclically increasing the address. The operation continues until the frame being written ends when the trigger signal arrives.
In the second write control means, the operation of writing a series of data that has arrived after the arrival of the trigger signal into the second storage area is started after the frame being written is completed when the trigger signal arrives. The semiconductor integrated circuit according to claim 20 or 25, wherein:

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