JPS647447U - - Google Patents
Info
- Publication number
- JPS647447U JPS647447U JP10253187U JP10253187U JPS647447U JP S647447 U JPS647447 U JP S647447U JP 10253187 U JP10253187 U JP 10253187U JP 10253187 U JP10253187 U JP 10253187U JP S647447 U JPS647447 U JP S647447U
- Authority
- JP
- Japan
- Prior art keywords
- calling number
- paging receiver
- erasing
- information
- received
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 1
Description
第1図は本考案の第1の実施例の外観図、第1
図aは正面図、同図bは上面図、同図cは側面図
、第2図は第1の実施例の全体の回路構成図、第
3図(A〜F)はPOCSAG方式のデータ構成
図、第4図は通信制御回路の詳細な回路構成図、
第5図はCPUの詳細な回路構成図、第6図は通
信制御回路の動作フローチヤート及びタイミング
チヤート、第7図はRAMの構成の一部を示す図
、第8図はCPUの受信割込み処理のフローチヤ
ート、第9図は全体の処理を示すフローチヤート
、第10図は本考案の第1の実施例の時計割込み
処理のフローチヤート、第11図は本考案の第2
の実施例の時計割込み処理のフローチヤートであ
る。
10……無線受信回路、11……通信制御回路
、12……CPU、46……RAM。
Figure 1 is an external view of the first embodiment of the present invention.
Figure a is a front view, Figure b is a top view, Figure c is a side view, Figure 2 is an overall circuit configuration diagram of the first embodiment, and Figures 3 (A to F) are data configurations of the POCSAG method. Figure 4 is a detailed circuit diagram of the communication control circuit,
Fig. 5 is a detailed circuit configuration diagram of the CPU, Fig. 6 is an operation flow chart and timing chart of the communication control circuit, Fig. 7 is a diagram showing a part of the configuration of the RAM, and Fig. 8 is a reception interrupt processing of the CPU. FIG. 9 is a flowchart showing the overall processing, FIG. 10 is a flowchart of clock interrupt processing according to the first embodiment of the present invention, and FIG. 11 is a flowchart showing the second embodiment of the present invention.
3 is a flowchart of clock interrupt processing in the embodiment. 10...Radio reception circuit, 11...Communication control circuit, 12...CPU, 46...RAM.
Claims (1)
自己の呼出し番号とを比較し一致したとき前記呼
出し番号の後に続く報知情報を取り込むページン
グ受信機において、 時刻を計時する計時手段と、自己の呼出し番号
を受信したとき前記報知情報と前記計時手段によ
り計時した受信時刻とを記憶する記憶手段と、前
記報知情報に基づき該情報の受信時刻と前記計時
手段により計時される現在時刻とを比較し該情報
を消去する消去手段とを有することを特徴とする
ページング受信機。 (2) 前記消去手段は前記計時手段からの所定時
間単位の割込みで動作することを特徴とする実用
新案登録請求の範囲第1項記載のページング受信
機。[Claims for Utility Model Registration] (1) A paging receiver that compares the received calling number with its own preset calling number and, when they match, measures the time in a paging receiver that captures notification information following the calling number. a storage means for storing the notification information and a reception time measured by the clocking means when the own calling number is received; A paging receiver comprising erasing means for comparing the information with the current time and erasing the information. (2) The paging receiver according to claim 1, wherein the erasing means is operated by an interrupt from the clocking means in predetermined time units.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987102531U JPH0533084Y2 (en) | 1987-07-03 | 1987-07-03 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987102531U JPH0533084Y2 (en) | 1987-07-03 | 1987-07-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS647447U true JPS647447U (en) | 1989-01-17 |
JPH0533084Y2 JPH0533084Y2 (en) | 1993-08-24 |
Family
ID=31332523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987102531U Expired - Lifetime JPH0533084Y2 (en) | 1987-07-03 | 1987-07-03 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0533084Y2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05244064A (en) * | 1990-11-30 | 1993-09-21 | Nec Corp | Radio selective call receiver with display |
JPH0750864A (en) * | 1994-06-02 | 1995-02-21 | Casio Comput Co Ltd | Paging receiver |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58131831A (en) * | 1982-02-01 | 1983-08-05 | Nec Corp | Radio selection and calling receiver |
JPS60106237A (en) * | 1983-11-15 | 1985-06-11 | Nec Corp | Display pager device |
-
1987
- 1987-07-03 JP JP1987102531U patent/JPH0533084Y2/ja not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58131831A (en) * | 1982-02-01 | 1983-08-05 | Nec Corp | Radio selection and calling receiver |
JPS60106237A (en) * | 1983-11-15 | 1985-06-11 | Nec Corp | Display pager device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05244064A (en) * | 1990-11-30 | 1993-09-21 | Nec Corp | Radio selective call receiver with display |
JPH0750864A (en) * | 1994-06-02 | 1995-02-21 | Casio Comput Co Ltd | Paging receiver |
Also Published As
Publication number | Publication date |
---|---|
JPH0533084Y2 (en) | 1993-08-24 |
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