JPS6467646A - Logical simulation system - Google Patents
Logical simulation systemInfo
- Publication number
- JPS6467646A JPS6467646A JP62226025A JP22602587A JPS6467646A JP S6467646 A JPS6467646 A JP S6467646A JP 62226025 A JP62226025 A JP 62226025A JP 22602587 A JP22602587 A JP 22602587A JP S6467646 A JPS6467646 A JP S6467646A
- Authority
- JP
- Japan
- Prior art keywords
- interpreter
- simulator
- test program
- processing
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stored Programmes (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To ensure the design evaluation with high efficiency by using an instruction interpreter of a high simulation speed to carry out the preprocessing and the post-processing of a test program and carrying out only a test object instruction via a logical simulator. CONSTITUTION:An instruction interpreter 40 works with a general-purpose computer 1. A transfer means 33 performs the control so that the interpreter 40 carries out only the pre-processing and the post-processing of a test program and a logical simulator 2 carries out a test subject instruction group of the test program respectively. Then the transfer means 70, 6 and 26 transfer the latest software visible information on a transfer origin to a transfer destination when the execution of the test program is transferred to the simulator 2 from the interpreter 40 and vice versa. That is, the pre-processing and the post- processing of the test program are carried out by the interpreter 40 of a high simulation speed. The transfer information is transferred between the interpreter 40 and the simulator 2 via a magnetic disk device 6. Then only the test object instruction is carried out by the simulator 2. Thus it is possible to ensure the design evaluation with high efficiency without developing a test program optimum to the simulator 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62226025A JPS6467646A (en) | 1987-09-08 | 1987-09-08 | Logical simulation system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62226025A JPS6467646A (en) | 1987-09-08 | 1987-09-08 | Logical simulation system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6467646A true JPS6467646A (en) | 1989-03-14 |
Family
ID=16838605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62226025A Pending JPS6467646A (en) | 1987-09-08 | 1987-09-08 | Logical simulation system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6467646A (en) |
-
1987
- 1987-09-08 JP JP62226025A patent/JPS6467646A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0340453A3 (en) | Instruction handling sequence control system | |
EP0840213A3 (en) | A branch executing system and method | |
EP0782071A3 (en) | Data processor | |
DE69321255T2 (en) | DEVICE FOR EXECUTING SEVERAL PROGRAM PARTS WITH DIFFERENT OBJECT CODE TYPES IN A SINGLE PROGRAM OR IN A PROCESSOR ENVIRONMENT | |
ATE161980T1 (en) | SYSTEM FOR OPERATING APPLICATION SOFTWARE IN A SAFETY-CRITICAL ENVIRONMENT | |
EP0335515A3 (en) | Method and apparatus for executing instructions for a vector processing system | |
EP1248211A3 (en) | Data processing system and design system | |
JPS6467646A (en) | Logical simulation system | |
EP0700539A1 (en) | Input/output emulation system | |
JPS6467645A (en) | Logical simulation system | |
JPS6467647A (en) | Logical simulation system | |
EP0221741A3 (en) | Computer microsequencers | |
JPS57168350A (en) | Information processor | |
JPS61245239A (en) | Logical circuit system | |
Rose et al. | N. mPc: a retrospective | |
JPS5710874A (en) | Instruction control device | |
JPS5750046A (en) | Data transmission system | |
JPS6465644A (en) | On-line debugging system in cross compiler development | |
MILLS | System modeling and simulation: Application of a research methodology and test[Ph. D.] | |
TODOROV | Directions of effective development of computer software(multiprogramming in Bulgaria) | |
JPS5727362A (en) | Vector data processor | |
BLELLOCH | AFL-1: A programming language for massively concurrent computers(M. S. Thesis) | |
JPS6462729A (en) | Model setting system for computer | |
JOHNSON et al. | Hierarchical control system emulation: Applications guide[Final Report, Nov. 1981- Oct. 1982] | |
JPH03168836A (en) | Emulation processor |