JPS6467645A - Logical simulation system - Google Patents

Logical simulation system

Info

Publication number
JPS6467645A
JPS6467645A JP62226024A JP22602487A JPS6467645A JP S6467645 A JPS6467645 A JP S6467645A JP 62226024 A JP62226024 A JP 62226024A JP 22602487 A JP22602487 A JP 22602487A JP S6467645 A JPS6467645 A JP S6467645A
Authority
JP
Japan
Prior art keywords
interpreter
processing
simulator
test program
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62226024A
Other languages
Japanese (ja)
Inventor
Hiroshi Nishioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62226024A priority Critical patent/JPS6467645A/en
Publication of JPS6467645A publication Critical patent/JPS6467645A/en
Pending legal-status Critical Current

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  • Stored Programmes (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To ensure the design evaluation with high efficiency by using an instruction interpreter of a high simulation speed to carry out the pre-processing and the post-processing of a test program and carrying out only a test object instruction via a logical simulator. CONSTITUTION:An instruction interpreter 40 works with a general-purpose computer 1. A transfer means 33 performs the control so that the interpreter 40 carries out only the pre-processing and the post-processing of a test program and a logical simulator 2 carries out a test subject instruction group of the test program. Then the transfer means 70, 6 and 26 transfer the latest software visible information on a transfer origin to a transfer destination when the execution of the test program is transferred to the simulator 2 from the interpreter 40 and vice versa. That is, both the pre-processing and the post-processing of the test program are carried out by the interpreter 40 of a high simulation speed and the transfer information is transferred between the interpreter 40 and the simulator 2 via a circuit system 6. Then only the test object instruction is carried out by the simulator 2. Thus the design evaluation is ensured with high efficiency without developing a test program optimum to the simulator 2.
JP62226024A 1987-09-08 1987-09-08 Logical simulation system Pending JPS6467645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62226024A JPS6467645A (en) 1987-09-08 1987-09-08 Logical simulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62226024A JPS6467645A (en) 1987-09-08 1987-09-08 Logical simulation system

Publications (1)

Publication Number Publication Date
JPS6467645A true JPS6467645A (en) 1989-03-14

Family

ID=16838589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62226024A Pending JPS6467645A (en) 1987-09-08 1987-09-08 Logical simulation system

Country Status (1)

Country Link
JP (1) JPS6467645A (en)

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