JPS6454955A - High speed polling communication system - Google Patents

High speed polling communication system

Info

Publication number
JPS6454955A
JPS6454955A JP21171487A JP21171487A JPS6454955A JP S6454955 A JPS6454955 A JP S6454955A JP 21171487 A JP21171487 A JP 21171487A JP 21171487 A JP21171487 A JP 21171487A JP S6454955 A JPS6454955 A JP S6454955A
Authority
JP
Japan
Prior art keywords
data
terminal equipment
enq
sequence
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21171487A
Other languages
Japanese (ja)
Inventor
Toyoki Ashihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21171487A priority Critical patent/JPS6454955A/en
Publication of JPS6454955A publication Critical patent/JPS6454955A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain quick data collection, by sending a polling signal addressed to the succeeding terminal equipment from a terminal equipment not awaiting the transmission in applying polling to said terminal so as to allow a control station to eliminate the need for the polling signal addressed to the succeeding terminal equipment. CONSTITUTION:A host CPU 10 awaits a data after an ENQ sequence transmission and discriminates whether or not the data is the ENQ data or the transmission data in receiving any data. Assuming that a terminal equipment 141 does not send a data but sends the ENQ sequence, the CPU 10 discriminates the absence of data in the terminal equipment 141, a terminal equipment designation value SA in the received ENQ sequence is revised into N+1 and the data reception from a terminal equipment 142 corresponding to SA=02 is awaited. When the terminal equipment 142 receiving the ENQ sequence sends a data to a line 13, the CPU 10 discriminates the data reception and recognizes/processes the received data as the transmission data of the terminal equipment 142 corresponding to SA=02. Then the polling signal addressed to the next terminal equipment is not transmitted.
JP21171487A 1987-08-26 1987-08-26 High speed polling communication system Pending JPS6454955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21171487A JPS6454955A (en) 1987-08-26 1987-08-26 High speed polling communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21171487A JPS6454955A (en) 1987-08-26 1987-08-26 High speed polling communication system

Publications (1)

Publication Number Publication Date
JPS6454955A true JPS6454955A (en) 1989-03-02

Family

ID=16610383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21171487A Pending JPS6454955A (en) 1987-08-26 1987-08-26 High speed polling communication system

Country Status (1)

Country Link
JP (1) JPS6454955A (en)

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