JPS57141741A - Input and output control system - Google Patents

Input and output control system

Info

Publication number
JPS57141741A
JPS57141741A JP56026531A JP2653181A JPS57141741A JP S57141741 A JPS57141741 A JP S57141741A JP 56026531 A JP56026531 A JP 56026531A JP 2653181 A JP2653181 A JP 2653181A JP S57141741 A JPS57141741 A JP S57141741A
Authority
JP
Japan
Prior art keywords
input
circuit
transfer speed
device number
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56026531A
Other languages
Japanese (ja)
Other versions
JPH069036B2 (en
Inventor
Tetsuhiko Seki
Hiroshi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56026531A priority Critical patent/JPH069036B2/en
Publication of JPS57141741A publication Critical patent/JPS57141741A/en
Publication of JPH069036B2 publication Critical patent/JPH069036B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To achieve block transfer without being troubled with individual transfer speed of input and output devices, by providing a circuit recognizing the device number of the input and output devices with different transfer speed to an adaptor and controlling the circuit with a transfer speed suitable for the input and output devices. CONSTITUTION:An input and output device number discriminating circuit 10 of an adaptor A selects the device number of an opposing input and output device from data transmitted from an input and output processor CHP and outputs a device number signal. A decoder circuit 11 receiving the device number signal interpretes the device number and determines the device number input and output device and inputs a determined transfer speed signal to a transfer speed control circuit 14. The circuit 14 makes data transmission/reception with the CHP with the selected speed from this signal. On the other hand, a buffer memory control circuit 13 stores data in a buffer memory 12 with the determined transfer speed from the CHP. This data is outputted through a selection circuit 15 with the block transfer signal. As a result, the data transfer speed between the CHP and the device A is made suitable to a respective input and output device.
JP56026531A 1981-02-25 1981-02-25 I / O controller Expired - Lifetime JPH069036B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56026531A JPH069036B2 (en) 1981-02-25 1981-02-25 I / O controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56026531A JPH069036B2 (en) 1981-02-25 1981-02-25 I / O controller

Publications (2)

Publication Number Publication Date
JPS57141741A true JPS57141741A (en) 1982-09-02
JPH069036B2 JPH069036B2 (en) 1994-02-02

Family

ID=12196061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56026531A Expired - Lifetime JPH069036B2 (en) 1981-02-25 1981-02-25 I / O controller

Country Status (1)

Country Link
JP (1) JPH069036B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197918A (en) * 1983-04-23 1984-11-09 Japan Radio Co Ltd Serial buffer device
JPS6362066A (en) * 1986-09-03 1988-03-18 Nec Corp Microcomputer
JPH01136204A (en) * 1987-11-24 1989-05-29 Mitsubishi Electric Corp Programmable controller
JPH07225638A (en) * 1991-11-29 1995-08-22 Haru Kenkyusho:Kk Signal switching device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197918A (en) * 1983-04-23 1984-11-09 Japan Radio Co Ltd Serial buffer device
JPS6362066A (en) * 1986-09-03 1988-03-18 Nec Corp Microcomputer
JPH01136204A (en) * 1987-11-24 1989-05-29 Mitsubishi Electric Corp Programmable controller
JPH07225638A (en) * 1991-11-29 1995-08-22 Haru Kenkyusho:Kk Signal switching device

Also Published As

Publication number Publication date
JPH069036B2 (en) 1994-02-02

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