JPS644904A - Peak shift compensation device - Google Patents

Peak shift compensation device

Info

Publication number
JPS644904A
JPS644904A JP16002287A JP16002287A JPS644904A JP S644904 A JPS644904 A JP S644904A JP 16002287 A JP16002287 A JP 16002287A JP 16002287 A JP16002287 A JP 16002287A JP S644904 A JPS644904 A JP S644904A
Authority
JP
Japan
Prior art keywords
digital data
peak shift
pattern
delay quantity
identification means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16002287A
Other languages
Japanese (ja)
Inventor
Hiroaki Muraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16002287A priority Critical patent/JPS644904A/en
Publication of JPS644904A publication Critical patent/JPS644904A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress peak shift and to prevent an error from being generated, by providing a means to identify the pattern of digital data read out from a medium and a means which applies several kinds of delay on the digital data, and selecting a delay quantity by the above identification means. CONSTITUTION:A circuit system is classified roughly to a pattern identification means 31 which identifies the pattern of the digital data 32 read out from the medium and inputted to the circuit system, and a delay quantity control means 30 which controls the delay quantity of the digital data. Furthermore, to the pattern identification means 31, a window signal 33 generated phase-locking with the input digital data 32 by a certain kind of PLL circuit so-called as a VFO circuit is also inputted. Then, the peak shift is reduced by correcting the pulse interval of the digital data by an output signal from the pattern identification means 31 by using the delay quantity control means 30. In such a way, it is possible to correct the peak shift due to waveform interference.
JP16002287A 1987-06-26 1987-06-26 Peak shift compensation device Pending JPS644904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16002287A JPS644904A (en) 1987-06-26 1987-06-26 Peak shift compensation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16002287A JPS644904A (en) 1987-06-26 1987-06-26 Peak shift compensation device

Publications (1)

Publication Number Publication Date
JPS644904A true JPS644904A (en) 1989-01-10

Family

ID=15706278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16002287A Pending JPS644904A (en) 1987-06-26 1987-06-26 Peak shift compensation device

Country Status (1)

Country Link
JP (1) JPS644904A (en)

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