JPS57107689A - Sampling pulse correcting system - Google Patents
Sampling pulse correcting systemInfo
- Publication number
- JPS57107689A JPS57107689A JP18421680A JP18421680A JPS57107689A JP S57107689 A JPS57107689 A JP S57107689A JP 18421680 A JP18421680 A JP 18421680A JP 18421680 A JP18421680 A JP 18421680A JP S57107689 A JPS57107689 A JP S57107689A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- output
- data
- sampling pulse
- sampling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
Abstract
PURPOSE:To enable to adjust the phase and slice level of a sampling clock pulse automatically, by providing a table setting output information in response to the phase difference of data for the sampling pulse. CONSTITUTION:An input from a video detection stage is inputted to a digital phase detection means 10D via a slice circuit 10G. An original clock pulse from a terminal 50 is inputted to a delay means 10A, the output is selected and given to a 1/2 frequency divider 54 based on the output of a delay amount control means 10B and outputted from a terminal 51 as the data sampling pulse. A table for output information representing the sampling pulse and data for the phase relation is set to a converter 10E, the information is selected in response to an output of the phase detection means 10D and applied to a delay amount control means 10B and a slice level control means 10C as the control information. Thus, the phase of sampling clock and the slice level of data can be adjusted automatically.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18421680A JPS57107689A (en) | 1980-12-25 | 1980-12-25 | Sampling pulse correcting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18421680A JPS57107689A (en) | 1980-12-25 | 1980-12-25 | Sampling pulse correcting system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57107689A true JPS57107689A (en) | 1982-07-05 |
| JPH029750B2 JPH029750B2 (en) | 1990-03-05 |
Family
ID=16149392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18421680A Granted JPS57107689A (en) | 1980-12-25 | 1980-12-25 | Sampling pulse correcting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57107689A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2597811Y2 (en) * | 1996-04-26 | 1999-07-19 | 株式会社ガスター | Water heater abnormality display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54104236A (en) * | 1978-02-02 | 1979-08-16 | Nippon Hoso Kyokai <Nhk> | Synchronizing-signal-phase coupled circuit |
| JPS5571368A (en) * | 1978-11-24 | 1980-05-29 | Nec Home Electronics Ltd | Data sampling system |
-
1980
- 1980-12-25 JP JP18421680A patent/JPS57107689A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54104236A (en) * | 1978-02-02 | 1979-08-16 | Nippon Hoso Kyokai <Nhk> | Synchronizing-signal-phase coupled circuit |
| JPS5571368A (en) * | 1978-11-24 | 1980-05-29 | Nec Home Electronics Ltd | Data sampling system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH029750B2 (en) | 1990-03-05 |
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