JPS644123Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a device that displays a sense of speed using a sleeper pattern.

FIG. 1 shows a block diagram of a speed sensing display device conventionally used in submarines and the like. The sleeper pattern shown in FIG. 2b is displayed on the monitor section 9 in FIG. This sleeper pattern becomes narrower toward the tip, creating a triangular shape at the tip, giving a sense of perspective. The displayed sleeper pattern moved toward the viewer at a speed corresponding to speed data 10, giving the viewer an intuitive sense of speed. In FIG. 1, the figure generating circuit 3 generates a triangular figure signal 65 and a sleeper signal 23 for displaying this sleeper pattern. By making the waveform of the sleeper signal 23 respond to the magnitude of the speed data 10, the sleeper pattern is moved forward at a speed proportional to the magnitude of the speed data 10. A trigger generation circuit 1 generates horizontal and vertical clock pulses necessary as synchronization signals. Shift register circuit 2
generates a trigger signal for operating the Y-axis sawtooth wave circuit 6 that generates a reference sawtooth wave in the vertical axis direction, the X-axis sawtooth wave circuit 7 that generates a reference sawtooth wave in the horizontal axis direction, and the figure generation circuit 3. , generates a signal for controlling the display position of the figure generated by the figure generation circuit 3. The figure generating circuit 3 consists of a triangular figure generating circuit 4 and a sleeper pattern generating circuit 5. The triangular figure signal 65 generated by the triangular figure generating circuit 4 is transformed in the output amplifier 8 by the sleeper signal 23 generated by the sleeper pattern generating circuit 5, and is sent to the monitor section 9 as a sleeper pattern video signal 66. When the triangular figure signal 65 is sent to the monitor section 9 without being transformed by the sleeper signal 23, two triangles shown in FIG. 2a are displayed. The output amplifier 8 receives a vertical synchronization signal 67 and a horizontal synchronization signal 68 necessary for the monitor section 9.
and a sleeper pattern video signal 66 is generated.

FIG. 3 is a block diagram of the sleeper pattern generating circuit 5. A triangular figure signal 65 is output from the triangular figure generating circuit 4.
A road start signal 12, which is a rectangular wave synchronized with the road start signal 12, is sent. Control circuit 13 generates set and reset signals for operating each integrating circuit. The integration circuit 16 starts operating in response to the road start signal 12. The output of the integrating circuit 16 is compared with the reference voltage 22 in the comparator circuit 15 and
The output of 5 passes through the control circuit 13 and becomes a signal for operating the integrating circuit 17. The integration circuit 14 operates based on the speed data 10, and the integration time changes depending on the magnitude of the speed data 10. The output of the integrating circuit 14 has a sufficiently longer integration time than the output of the integrating circuit 17. A comparison circuit 15 compares the output of the integration circuit 14 and the output of the integration circuit 17 to generate a sleeper start pulse 46. Since the timing of generation of the sleeper start pulse 46 changes depending on the output of the integrating circuit 14, the timing of shift generation changes depending on the magnitude of the speed data 10.

Integrating circuits 18 and 19 generate signals for determining the number of sleeper patterns, and integrating circuits 20 and 21 generate signals for determining the width of the sleeper patterns. Comparison circuit 15 compares each signal and outputs the result. Sleeper signal 23 generated in this way
becomes a video signal through the output amplifier 8 and the monitor section 9
The image is sent to and displayed.

As shown in Fig. 3, the conventional sleeper pattern generation circuit is composed of analog circuits such as an integrating circuit, a comparator circuit, and a control circuit, and these are composed of resistors, capacitors,
Since it is made from individual parts such as operational amplifiers, the number of parts and therefore the number of boards increases, and circuit adjustment is troublesome. Furthermore, since the circuit is made up of many boards, it is susceptible to noise generated between lines.
There was a drawback that the sleeper pattern displayed on the monitor section 9 was difficult to see.

The purpose of the present invention is to digitize the sleeper pattern generation circuit, so that the sleeper pattern generation circuit can be constructed with fewer parts and boards, is less susceptible to noise between lines, and does not require any adjustment points.
To provide a speed sense display device which is small, lightweight, and inexpensive and can stably display a sleeper pattern.

The device of the present invention consists of a pair of left and right triangular figures formed with a common vertex at an arbitrary position above the vertical center line of the image plane and a pair of left and right bases set at a target position in the horizontal direction below the image plane. are combined with sleeper signals to form a sleeper pattern by contrasting them with intermittent dark areas shaped like sleepers, and the sleeper signals are shifted in accordance with the magnitude of the speed data to be expressed on the video screen while In a speed sense display device that displays a sense of speed with a pattern visually flowing from the common apex toward the base, the speed data is received while receiving a road start signal synchronized with the timing of the generation of the speed data and the triangular figure. The counter operates according to the sleeper start signal and the speed data, which provides the timing of the start of the sleeper pattern obtained by shifting the cumulative addition value of the counter operated by the road start signal and the road start signal. sleeper start pulse generating means for setting the timing of generation of the sleeper pattern by shifting it in accordance with the magnitude of the speed data while comparing the cumulative addition value of a counter that performs a sufficiently fast counting process; and the road start signal. The cumulative addition value of the counter operated by the sleeper start pulse is compared with the cumulative addition value of the counter operated by the sleeper start pulse, and the cumulative addition value of the counter operated by the sleeper start pulse is determined by the road start signal. The sleeper signal is generated with the time width of the output of the comparator circuit obtained when the value is greater than the cumulative addition value of the counter that operates, and the sleeper pattern is applied to the triangular figure, and the speed of the sleeper start pulse generating means is The apparatus includes a timing for setting a cumulative addition value of a counter operated by data in accordance with the sleeper signal, and sleeper signal generating means for clearing the accumulated value.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 4 shows a block diagram of a sleeper pattern generating circuit used in the present invention. The sleeper pattern generation circuit 59 having the configuration shown in this figure is used to display the sleeper pattern shown in FIG. 5 on the display screen of the monitor section 9 to express the sense of speed. Figure 5 a~
As shown in d, the sleeper pattern changes sequentially over time, allowing the observer to intuit the speed according to the speed data 11. 6 and 7 are timing diagrams of signals in various parts of the circuit of FIG. 4. In both figures, counter output 4
1, 42, 43, 44 and 47 are drawn instead of analog signals corresponding to digital values.

The sleeper pattern generation circuit shown in FIG. 4 includes a delay circuit 25, counters 26, 27, comparison circuits 31, 32, and a register 37, which constitute sleeper start pulse generation means, and counters 28 to 30, which constitute sleeper signal generation means. 33, comparison circuits 34 to 36, and a flip-flop 38.

The delay circuit 25 gives the road start signal 12 a delay of the time necessary to display the triangle at the tip of the sleeper pattern, and outputs it as the sleeper start signal 24. In order to make the position of the sleeper pattern change depending on the speed, a comparator circuit 32 compares the output 42 of the counter 27 which starts its operation with the sleeper start signal 24 and the output 41 of the counter 26 which starts its operation with the speed data 11. Then, a sleeper start pulse 46 is generated according to the speed data 11, and the generation position of the sleeper start pulse 46 is shifted to the right of the time axis 54 (the vertical axis indicates the count number 53). The output 41 of the counter 26 has a sufficiently long cycle compared to the output 42 of the counter 27. By comparing the output 43 of the counter 28 which starts its operation with the road start signal 12 and the output 47 of the counter 33 which starts its operation with the input of the sleeper start pulse 46, the counter output 47 having the sawtooth wave characteristic shown in FIG. obtain. As stated above, road start signal 12 operates counter 28 and counter 29. Next, the counter 33 is operated by the sleeper start pulse 46, and the comparator circuit 34 and the comparator circuit 35 output the output 43 of the counter 28 and the output 4 of the counter 29.
4 and the output 47 of the counter 33 are compared. When the condition of output 43 of counter 28<output 47 of counter 33 is satisfied, the counter 33 is cleared by the output 48 of the comparison circuit 34. Moreover, the output 44 of the counter 29<the output 47 of the counter 33
At this time, the signal of the output 49 of the comparator circuit 35 is synchronized with the vertical clock signal 40 and output from the flip-flop 38 as the sleeper signal 23.

In order to make the sleeper pattern appear to flow on the screen, the timing at which the sleeper start pulse 46 is generated is changed. For this purpose, the output 41 of the counter 26 and the output 42 of the counter 27 cumulatively add the speed data 11 at the timing of the vertical clock signal 40.
are compared by the comparison circuit 32. A sleeper start pulse 46 is generated when the conditions of the output 41 of the counter 26 and the output 42 of the counter 27 are satisfied. The output 41 of the counter 26 has different weights added per clock signal depending on the value of the speed data 11, and changes more quickly as the speed data 11 is larger (faster).

In addition, in order to make the sleeper pattern flow smoothly, the counter 26 outputs so that when the first sleeper comes to the position of the second sleeper in the first sleeper pattern that is generated, the sleeper pattern returns to the first sleeper pattern. Clear the contents of 41. In order to carry out such an operation, a comparison circuit 36 compares the output 43 of the counter 28 and the output 45 of the counter 30, which starts its operation in response to the sleeper start pulse 46. and counter 28
When the output 43 of the counter 30 is smaller than the output 45 of the counter 30, a register control signal 50 is generated, and the output 4 of the counter 27 is
2 is stored in register 37. That resist 3
The value 51 of 7 and the output 41 of the counter 26 are compared by the comparison circuit 31. As a result, counter 2
When the output 41 of 6<the register value 51, a clear signal 52 is output to clear the contents of the counter 26. Note that the horizontal clock signal 39 is a synchronization signal in the horizontal direction of the display screen.

As described above, the present invention mainly consists of a comparison circuit consisting of a counter and a digital comparator.
Since these are digital circuits, they can be configured with a small number of parts and without adjustment points for each circuit.

An embodiment of a speed sensing display device using the circuit shown in FIG. 4 is shown in FIG. The embodiment shown in FIG. 8 includes an input conversion circuit 56, a control circuit 57, a basic clock generation circuit 58, a sleeper signal generation circuit 59, a triangular figure generation circuit 60, a video synthesis circuit 61, and a monitor 9. Comparing this with the configuration of the conventional example shown in FIG. The present invention basically corresponds to the wave circuit 7, the triangular figure generating circuit 60 to the triangular figure generating circuit 4, the video synthesis circuit 61 to the output amplifier 8, and the sleeper signal generating circuit 59 corresponding to the sleeper signal generating circuit 5. This is the part that is directly targeted.
An analog speed signal 55 to be displayed is input,
The input conversion circuit 56 converts the data into digital data that can be internally processed. This data is sent to a basic clock generation circuit 58 and a sleeper pattern generation circuit 59. The sleeper pattern generating circuit 59 operates in response to signals from the basic clock generating circuit 58 and the triangular figure generating circuit 60 and generates the sleeper signal 23. The output signals from the sleeper pattern generation circuit 59 and the triangular figure generation circuit 60 are processed into video signals by the video synthesis circuit 61 and sent to the monitor section 9.
and displayed as a sleeper pattern.

According to the present invention, the sleeper pattern generation circuit can be configured with a small number of parts and circuit boards, is less susceptible to noise within the device, and does not require any adjustments, so the sleeper pattern display is stable and compact. , it is possible to obtain a lightweight and inexpensive speed sensing display device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional speed sense display device, FIG. 5 is a block diagram showing one embodiment of the sleeper pattern generation circuit used in the present invention, FIG. 5 is a display diagram of the sleeper pattern displayed by the present invention, FIG. FIG. 7 is a timing diagram showing the principle of generating the sleeper signal 23, and FIG. 8 shows an embodiment of the present invention. 1...Trigger generation circuit, 2...Shift register circuit, 3...Graphic generation circuit, 4...Triangular figure generation circuit, 5...Sleeper pattern generation circuit, 6...Y-axis sawtooth wave circuit, 7...X Axial sawtooth wave circuit, 8...
Output amplifier, 9... Monitor unit, 10, 11... Speed data, 12... Road start signal, 13...
Control circuit, 14... Integrating circuit, 15... Comparing circuit, 16-21... Integrating circuit, 22... Reference voltage, 23... Sleeper signal, 24... Sleeper start signal, 25... Delay circuit, 26- 30...Counter, 31, 32...Comparison circuit, 33...Counter, 34-36...Comparison circuit, 37...Register, 38...Flip-flop, 39...Horizontal clock signal, 40...Vertical clock signal, 46...
...Sleeper start pulse, 54...Time axis, 55...
...Speed signal, 56...Input conversion circuit, 57...Control circuit, 58...Basic clock generation circuit, 59...
. . . sleeper pattern generation circuit, 60 . . . triangle figure generation circuit, 61 . . . video synthesis circuit, 65 .

Claims (1)

[Claims for Utility Model Registration] A pair of left and right bases formed with a common vertex at an arbitrary position above the vertical center line of the image plane and a pair of left and right bases set at targeted positions in the horizontal direction below the image plane. Each of the triangular figures is combined with a sleeper signal to provide a sleeper-like intermittent dark area in contrast to form a sleeper pattern, and the sleeper signal is shifted in accordance with the size of the speed data to be represented on the video screen. In a speed sense display device that displays a sense of speed in such a manner that the sleeper pattern visually flows from the common apex toward the base, the speed sense display device comprises: receiving the speed data and a road start signal synchronized with the timing of generation of the triangular figure; a counter that operates based on a sleeper start signal that provides the timing of the sleeper pattern start obtained by shifting the cumulative addition value of the counter that operates based on the speed data and the road start signal; and a counter that operates based on the speed data; sleeper start pulse generating means for setting the timing of generation of the sleeper pattern while shifting it in accordance with the magnitude of the speed data while comparing the cumulative addition value of a counter that performs a sufficiently faster counting process than the road; The cumulative addition value of the counter operated by the start signal is compared with the cumulative addition value of the counter operated by the sleeper start pulse, and the cumulative addition value of the counter operated by the sleeper start pulse is determined as the road start signal. The sleeper start pulse generating means generates the sleeper signal with the time width of the output of the comparator circuit obtained when the cumulative addition value of the counter operated by A speed sense display device for generating the sleeper pattern, comprising timing for setting and clearing the cumulative addition value of a counter operated according to the speed data in accordance with the sleeper signal. .