JPS6437654A - Inter-processor communication memory - Google Patents

Inter-processor communication memory

Info

Publication number
JPS6437654A
JPS6437654A JP62192578A JP19257887A JPS6437654A JP S6437654 A JPS6437654 A JP S6437654A JP 62192578 A JP62192578 A JP 62192578A JP 19257887 A JP19257887 A JP 19257887A JP S6437654 A JPS6437654 A JP S6437654A
Authority
JP
Japan
Prior art keywords
control part
trigger signal
systems
segment
segments
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62192578A
Other languages
Japanese (ja)
Inventor
Masakazu Mise
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62192578A priority Critical patent/JPS6437654A/en
Publication of JPS6437654A publication Critical patent/JPS6437654A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To minimize influence due to the competition of access requests outputted from both systems and to remove the loss of a waiting time by optionally dividing each of both the systems into segments and controlling respective segments and transferring only renewal segments to the memories of both systems. CONSTITUTION:When a trigger signal A from a port A to a port B is generated, a status control part is started by receiving the trigger signal A. On the other hand, semaphores A for inhibiting the generation of a trigger signal after receiving the initial trigger signal are generated on both the ports A, B. Since the status control part controls and stores the existence of the updating of the memories in each segment, the status control part transfers only an updated segment at the time of its starting. At the time of completing the transfer of one segment, a transfer completion signal TC is informed to a transfer control part.
JP62192578A 1987-08-03 1987-08-03 Inter-processor communication memory Pending JPS6437654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62192578A JPS6437654A (en) 1987-08-03 1987-08-03 Inter-processor communication memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62192578A JPS6437654A (en) 1987-08-03 1987-08-03 Inter-processor communication memory

Publications (1)

Publication Number Publication Date
JPS6437654A true JPS6437654A (en) 1989-02-08

Family

ID=16293612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62192578A Pending JPS6437654A (en) 1987-08-03 1987-08-03 Inter-processor communication memory

Country Status (1)

Country Link
JP (1) JPS6437654A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06301652A (en) * 1993-04-14 1994-10-28 Nec Corp Semaphore acquiring device in multiprocessor system
WO2022004837A1 (en) * 2020-07-03 2022-01-06 日本電気株式会社 Information processing device, information processing method, and recording medium for information processing program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06301652A (en) * 1993-04-14 1994-10-28 Nec Corp Semaphore acquiring device in multiprocessor system
WO2022004837A1 (en) * 2020-07-03 2022-01-06 日本電気株式会社 Information processing device, information processing method, and recording medium for information processing program

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