JPS6424682A - Channel selection display circuit for television receiver - Google Patents

Channel selection display circuit for television receiver

Info

Publication number
JPS6424682A
JPS6424682A JP62181338A JP18133887A JPS6424682A JP S6424682 A JPS6424682 A JP S6424682A JP 62181338 A JP62181338 A JP 62181338A JP 18133887 A JP18133887 A JP 18133887A JP S6424682 A JPS6424682 A JP S6424682A
Authority
JP
Japan
Prior art keywords
channel selection
signal
counter
generated
selection display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62181338A
Other languages
Japanese (ja)
Other versions
JP2811067B2 (en
Inventor
Takahiro Sagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62181338A priority Critical patent/JP2811067B2/en
Publication of JPS6424682A publication Critical patent/JPS6424682A/en
Application granted granted Critical
Publication of JP2811067B2 publication Critical patent/JP2811067B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To attain cost-down by changing a channel selection display area even when number of horizontal picture elements of a picture display is changed so as to generate one channel selection display bar picture at all times to the picture display of an optional picture element number and eliminate the need for changing the frequency division ratio of a clock signal. CONSTITUTION:A clock signal 17 being N times of a synchronizing signal frequency is generated from a timing generation circuit 6 and a reset signal 18 retarded by a prescribed time from the synchronizing signal 15 is generated to activate the counter 8. When the output of the counter 8 reaches a maximum value by countup, it restores to the minimum value again, reset when the reset signal 18 is generated by count-up and starts counting the minimum value again. A channel selection control circuit 10 counts up an up-down counter 11 when an up channel selection instruction is generated, uses a D/A converter 12 to convert the signal into a DC voltage to increase the tuning voltage 13. A coincidence detection circuit 9 gives a pulse signal 16 to the gate 21 when the output of the counter 8 is coincident with the output of the counter 11. Only a 1st shot of the pulse signal 16 passes through the gate 21 and it is given to a channel selection display superimposing circuit 3 as a channel selection display signal 19.
JP62181338A 1987-07-21 1987-07-21 Tuning display circuit Expired - Lifetime JP2811067B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181338A JP2811067B2 (en) 1987-07-21 1987-07-21 Tuning display circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181338A JP2811067B2 (en) 1987-07-21 1987-07-21 Tuning display circuit

Publications (2)

Publication Number Publication Date
JPS6424682A true JPS6424682A (en) 1989-01-26
JP2811067B2 JP2811067B2 (en) 1998-10-15

Family

ID=16098950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181338A Expired - Lifetime JP2811067B2 (en) 1987-07-21 1987-07-21 Tuning display circuit

Country Status (1)

Country Link
JP (1) JP2811067B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6268373A (en) * 1985-09-20 1987-03-28 Seiko Epson Corp Channel selection display device for television

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6268373A (en) * 1985-09-20 1987-03-28 Seiko Epson Corp Channel selection display device for television

Also Published As

Publication number Publication date
JP2811067B2 (en) 1998-10-15

Similar Documents

Publication Publication Date Title
JPS57154983A (en) Multiplying circuit of horizontal scan frequency
CA1040300A (en) Digital synchronizing system
ES431139A1 (en) Digital synchronization system
GB1429621A (en) Display systems
ES8700821A1 (en) Sychronizing the operation of a computing means with a reference frequency signal.
ES8103898A1 (en) Television receiver synchronizing arrangement
JPS6424682A (en) Channel selection display circuit for television receiver
JPS5752280A (en) Line selector of television set
JPS55115775A (en) Synchronizing signal generator
JPS6430376A (en) Channel selection display circuit for television
JPS57106277A (en) Counter device
JPS5617583A (en) Television picture receiver
JPS53135513A (en) Signal decision circuit of automatic channel selection device
SU1515396A1 (en) Device for shaping video signal of inclined lines
JPS5577279A (en) Forming circuit for control signal
KR840002746Y1 (en) Television receiver
JPS5696526A (en) Timing signal generating system
SU1626452A1 (en) Device for automatic tv receiver tuning
JPS57129071A (en) Field discriminating circuit
SU1149434A1 (en) Signal-synchronizing of device video tape recorder
JPS54159122A (en) Detection circuit for selection control signal for television audio multiplex broadcast transceiver
JPS5320724A (en) Timing control device for television picture receiver, etc.
JPS5545236A (en) Multiplex broadcast receiving unit
JPS55136771A (en) Gen-lock control circuit for television synchronizing signal generator
JPS5588472A (en) Reset pulse forming circuit

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term