JPS6417511A - Digital muting circuit - Google Patents

Digital muting circuit

Info

Publication number
JPS6417511A
JPS6417511A JP17418387A JP17418387A JPS6417511A JP S6417511 A JPS6417511 A JP S6417511A JP 17418387 A JP17418387 A JP 17418387A JP 17418387 A JP17418387 A JP 17418387A JP S6417511 A JPS6417511 A JP S6417511A
Authority
JP
Japan
Prior art keywords
muting
data
level
sound data
input terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17418387A
Other languages
Japanese (ja)
Inventor
Kazuya Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP17418387A priority Critical patent/JPS6417511A/en
Publication of JPS6417511A publication Critical patent/JPS6417511A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain on-muting and off-muting of PCM sound data by controlling the level of digital sound data consisting of N bits by a level control means consisting of N multiplexers. CONSTITUTION:Reproduced PCM sound data (i) consisting of N bits are sent to an input terminal 12 in each word synchronously with a sampling clock (f) and supplied to the input terminals I1 of the multiplexers 111-11N. Each multiplexer selects a signal to be outputted from its output terminal Y out of signals inputted to its input terminals I1-I4 in accordance with data input signals supplied to its input terminals A, B. At the time of on-muting, output PCM sound data (k) are not immediately muted to the minimum level but are gradually attenuated every sampling clock and reached to the minimum level. At the time of off-muting, the data (k) is gradually restored from the minimum level to the level of the data (i).
JP17418387A 1987-07-13 1987-07-13 Digital muting circuit Pending JPS6417511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17418387A JPS6417511A (en) 1987-07-13 1987-07-13 Digital muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17418387A JPS6417511A (en) 1987-07-13 1987-07-13 Digital muting circuit

Publications (1)

Publication Number Publication Date
JPS6417511A true JPS6417511A (en) 1989-01-20

Family

ID=15974167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17418387A Pending JPS6417511A (en) 1987-07-13 1987-07-13 Digital muting circuit

Country Status (1)

Country Link
JP (1) JPS6417511A (en)

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