JPS6395551A - Serial data processor - Google Patents

Abstract

PURPOSE:To form a serial interface with small hardware without deteriorating the executing efficiency of an executing part, by applying the macroservice processing to perform transmission/reception of the serial data. CONSTITUTION:This serial data processor contains the memory parts 102 and 103 which store programs and various data, an executing part 101 which interprets the contents of programs and executes them, a status register 200 which stores the status information showing the executing state, and a serial interface part 400 which transmits and receives the serial data. The part 101 interrupts execution of a program while holding the status information showing the program executing state into the register 200 and transmits and receives the serial data by a serial data processing request signal received from the part 400. Then the part 101 restarts the program execution. The part 400 produces repetitively the processing request signals by the prescribed timing until the transmission and reception of data are through. Thus the serial data are intermittently processed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a serial data processing device having a serial interface function and a computer function, and in particular, to a serial data processing device having an execution unit that executes other processing in parallel during serial data transmission/reception processing. The present invention relates to a possible serial data processing device.

[Conventional technology]

With the development of integrated circuit manufacturing technology, timers, counters,
Various peripheral hardware such as A/D converters can now be integrated on a single chip. Among these, serial interfaces have become indispensable for distributed processing and communication between various terminals as microcomputers become more sophisticated.

Conventionally, as a method for realizing this serial interface function t'', UART (Only a
I Async-ronous I (Ieceiv
In some cases, most of the serial data processing is performed by hardware, as is known as an er/transmitter, and in other cases, most of the processing is performed by software according to a user's program.

A case in which most of the serial data processing is performed by hardware will be described below with reference to FIG. 6.

FIG. 6 is a block diagram of a conventional serial data processing device incorporating a serial interface. First, the constituent elements will be explained. The serial data processing device 100 is
Execution unit 101. Program memory 102. Data memory 103. and a serial interface 104, each of which is interconnected via an internal bus 105.

The execution unit 101 has a program counter 101-1, a program status word 101-2, and a program status word 101-2. It has a general-purpose register set 101-3, reads and executes instruction codes from the program memory 102, and stores processing data in the data memory 1.
Stored in 03. In the data memory 103, transmission data storage areas 103-1. A received data storage area 103-2 is provided. Serial interface 104 C) Transmission control unit 104-2 for controlling transmission during transmission, transmission line 104-1) Transmission shift register 104-3 for transmitting serial data C) The shift register 1
Transmission data buffer 104-4.04-3 is used for writing the transmission booter. A reception control unit 104-9 that performs reception control during reception. Reception shift register 104-10 which receives and receives received data from reception line 104-8. a receive data buffer 104-11 that stores received data;
Said transmission/reception shift register 104-3゜104-'1
First, the transmission operation will be explained. The execution unit 101 has a program memory 102
When all the instructions for serial transmission are executed, the transmission request signal line 104-6e is
It is activated and sends a transmission request signal to the transmission control section 104-2. When the transmission control unit 104-2 receives the request signal, it activates the transmission permission fi 104-7i, and transfers the transmission data previously stored in the transmission data buffer 104-4 to the transmission shift register 104-3. The transmission shift register 104-3 uses a shift clock 104 output from the baud rate generator 104-15.
-16, sequentially sends all data one bit at a time to the transmission line 104
Send from -1.

On the other hand, the transmission data buffer 10 that sent the transmission data
4-4 activates the transmission completion signal line 104-5' and informs the execution unit 10 that the transmission data buffer is empty.
Notify 1. The execution unit 101 that receives the transmission completion notification temporarily suspends the processing up to that point and sets the program counter 101-1.1 to hold the processing contents. Program status word 101-2. The contents of the general-purpose register set 101-3 are temporarily saved to the stack area in the data memory 103. The execution unit 101 then executes the interrupt program and sequentially performs the following operations.

■Transmission data storage area 10 where data to be transmitted is stored
Read the contents of 3-1 and connect it to serial interface 1.
The data is transferred to the transmission data buffer 104-4 in 04.

The data to be transmitted at the 0th time is stored in the transmission data storage area 103-1.
Store in.

After executing the above interrupt program, the execution unit 101 executes the general register set 101-3 saved in the stack. Program status word 101-2. The contents of the program counter 101-1 are returned to their original locations and the interrupted processing is continued.

By repeating the above transmission sequence a predetermined number of times, a continuous transmission operation is performed.

Next, the reception operation will be explained. First, the execution unit 101 is a reception control unit 104-9 in the serial interface 104.
Then, a reception permission signal is sent as reception permission signal 104-13. Upon receiving the permission signal, the reception control section 104-9 operates an internal start bit detection circuit to detect the start bit input through the reception line 104-8.

When the start bit is detected, the reception start line 104-
144 - Activates to permit data input from receive twin 104-8 to receive shift register 104-10. Thereafter, the reception shift register 104-10 shifts and stores the data input from the reception line 104-8 according to the shift clock 104-16 output from the baud rate generator 104-15, and stores only the data due to predetermined bits. Immediately after the storage is completed, the data' is transmitted to the reception data buffer 104-11. When the reception data buffer 104-11 stores the reception data, it activates the reception completion signal and notifies the execution unit 101 of the reception completion via the reception completion signal 104-12. When the execution unit 101 receives the reception completion signal, it temporarily suspends the processing up to that point and sets the program counter 101-1.1 to hold the processing contents. Program status word 101
-2゜Temporary data memo of the contents of general-purpose register set 101-3! Save to the stack area in J103.

Then, the interrupt program reads the contents of the received data buffer 1o4-i1, writes it to the received data storage area 1θ3-2 in the data memory 103, and writes the contents of the general-purpose register set 101-3 saved in the stack area.
Program status word 101-2. The program counter 101-1 is read again and the original processing continues.

The above describes conventional examples of serial data transmission and reception in which most of the serial data processing is performed by hardware.

In the conventional method where most of the serial data transmission and reception processing is performed by hardware, the transmission processing is automatically performed simply by loading the data t1f into the transmission data buffer, and in the case of reception, the hardware of the serial interface also performs the reception processing. Therefore, it is only necessary to retrieve the data stored in the reception data buffer, and serial data transmission and reception can be performed easily.Furthermore, since the execution unit 101 can perform other processing during serial data transmission and reception processing, the execution Although it has the advantage that the processing efficiency of the section 101 does not decrease, the amount of hardware for the serial interface itself is large. If the area on the chip is large,
The serial data processing device becomes expensive.

There are also cases where serial data is sent and received by software processing using a general bidirectional port without using the above hardware, but in this case, the execution unit This has the disadvantage that the processing efficiency of the execution section decreases because the computer cannot perform other processing, and because it is software processing, the transmission and reception processing cannot keep up with the faster transfer speed.

[Problem that the invention seeks to solve]

The conventional serial data processing device described above requires a large amount of hardware for serial transmission and reception processing, such as shift registers and buffer registers, which occupies a large circuit area on the chip, making the serial data processing device expensive. There are drawbacks.

[Means for solving problems]

The serial data processing device according to the present invention includes a memory unit that stores the program and each rJ data, an execution unit that fully interprets and executes the contents of the program, a status register that stores status information indicating the execution state, and a memory unit that stores the program and each rJ data, and a status register that stores status information indicating the execution state. The execution unit includes a serial interface unit for executing the program, and the execution unit executes the program while retaining status information indicating the execution state of the program in the status register according to the serial data processing request signal output from the serialization interface unit. interrupted,
After executing the serial data transmission/reception process, the program execution process is restarted, and the serial interface section repeatedly generates the processing request signal at a predetermined timing until the serial data transmission/reception process is completed, thereby intermittently performing the process. It was designed to be carried out in

〔Example〕

Next, examples of the present invention are shown in FIGS. 1, 2, 3, and 4.
This will be explained using FIG.

FIG. 1 is a block diagram of an embodiment of the serial data processing apparatus of the present invention, and FIG. 2 is a detailed diagram of the serial interface block 400 in FIG. 1. The constituent elements will be explained below.

The serial interface block 400 in the serial data processing device 100 has one external input/output line 400-2.
4- It is used to send and receive serial data,
1-bit read/write latch 400-3. Start bit detection circuit 400-4. Baud rate timer 400-
5. It has a serial mode flag 400-6. When transmitting data, first, the transmission/reception switching flag 400-61't@1' is set to the transmission mode. Then, set the transmission trigger bit 400-62k to "1", activate the transmission activation line 400-9, and send a transmission activation request signal to the serial interface control unit 300 through the transmission/reception request line 4.
Output via 00-11.

At the same time, the baud rate timer 400-
Start 5. When receiving data, the transmission/reception switching flag 400-61'k is set to "O" to set the reception mode, and the start bit detection line 400-8 is activated to start the operation of the start bit detection circuit 400-4.

When the start bit detection circuit 400-4 detects the start bit bit, it activates the reception activation line 400-10 and starts the baud rate timer 400-5. The baud rate timer 400-5 is connected to the transmission activation line 400-9. Alternatively, when the reception activation line 400-10 receives or receives a transmission activation request signal or a reception activation request signal, the signals start after being reset and are sequentially incremented at a predetermined clock.

When an overflow occurs, the timer overflow line 400-1 is activated and a transmission/reception request signal is output to the serial interface control section 300 via the transmission/reception request line 400-11. The baud rate timer 400-5 is set to transmit serial data bit by bit at a fixed timing, and when changing the baud rate, the pit length is changed. Read/write data latch 40
0-3 is a latch that stores 1 bit of transmitted/received data, and when transmitting, the data stored by the processing of the execution unit 101 is output to the external input/output line 400-2 by the timer overflow signal 400-1, and when receiving, The external input/output &! is triggered by the timer overflow signal 400-1. 400-
Latch the input data to 2. The serial interface control section 300 is a serial interface block 40
When a transmission request signal or a reception request signal from 0 is received via the transmission/reception request line 400-11, one bit of data to be transmitted is transferred to the read/write latch 400-3. The operation of transferring the 1-bit received data captured in -3 to the data memory was performed automatically without any program intervention (hereinafter this operation sound is referred to as "macro service").
, which is in charge of general interrupt processing operations, and the I10 request control unit 300-1. I10 request processing execution line 300-3. I10 request processing processing type specification line 30
0-4. and an I10 request receiving section 300-2 that controls the operation of the execution section 101.

The execution unit 101 uses a program counter (hereinafter referred to as "PC") 101-1. A program status word (P8W) 101-2 that indicates the operating status of the entire execution unit; a general-purpose register set 101-3 that holds data being processed; Arithmetic logic unit (hereinafter referred to as "ALU") 101- having an arithmetic logic operation function
4. Temporary register 101-8 for storing 1-bit transmitted/received data. Instruction register 101-5 that holds the G instruction to be executed next. an instruction decoder 101- that decodes the contents of the instruction register 101-5 and generates each first control signal;
6. It has an execution control section 101-7 that controls the operation of the entire execution section based on the output of the instruction decoder 101-6.

Furthermore, the data memory 103 includes a macro service register group 200 used in the macro service.

Within the macro service register group 200, there is a transmission/reception data storage area (2 bytes) 20 for storing data to be transmitted/received.
0-1. The macro service counter (hereinafter referred to as “M
200-2 (referred to as "2O") is set. All of the above-mentioned parts are interconnected by an internal bus 105.

Below are block diagrams in Figures 1 and 2, serial data transmission/reception macro service processing sequence diagram in Figure 3, and Figure 4.
Transmission and reception operations will be explained with reference to the transmission and reception sequence diagram in FIG.

First, the transmission operation will be explained. First, one start bit (“0”) is placed in the transmission/reception data storage area 200-1.
8 bits of transmission data, 1 bit of parity bit, 1 bit of stop bit (11").

Data @1'', a total of 12 bits, are stored as shown in Figure 4 (■). Then, a value of 13 is set in the MSC 200-2. Next, set the transmission/reception switching flag 400-61 to l" to set the transmission mode. Then, the transmission trigger bit 400-6
2e is set to "1" and a transmission activation request is given. Upon receiving the transmission activation request signal via the transmission activation line 400-9'e, the baud rate master 400-5 starts counting up.

At the same time, the transmission activation request signal is sent to the transmission/reception request line 400.
-11' via serial interface control unit 300
is input. The I10 request control section 300-1 in the serial interface control section 300 recognizes this transmission activation request signal as a macro service request, activates the I10 request processing execution line 300-3, and activates the I10 request processing processing mode specification line 300-. 4, all macro service request signals are output. The I10 request reception unit 300-2 receives these signals and forcibly sets a code for macro service processing in the instruction register 101-5.

The execution control unit 101-7 prohibits updating of the address of PCIOI-1 based on the macro service processing code number, and further updates pclot-t, P8W101-2. The following macro service processing is performed while holding the value of the general-purpose register set 101-3.

■Transmission/reception switching) Check the value of 2G 400-61,
°1" and recognizes it as a transmission operation.

(2) Concatenate the 2-byte data in the transmitted/received data storage area 200-1 to create 16-bit data and shift it to the right by 1 bit. This operation t↓ is performed in ALU10t-4. However, at this time, f and SB of the lower byte of the transmission/reception data storage area 200-1 are transferred to the MOB of the upper byte, and L of the upper byte is
8B are each transferred to the temporary register 101-8 by 7 feet (see FIG. 3).

■By the above shift, the temporary register 101
-8 is output to a predetermined bit of the internal bus, and the data sent to the read/2
The data is stored in the i-latch 400-3.

0 MSC200-2 is decremented, and if it is not 609, macro service processing is performed and I) return to the previously executed processing. If it is "0", the baud rate timer 400-5'e is stopped and an interrupt processing request signal is generated.

With the above macro service processing, 1 bit (M8C=13
In the case of processing, the data of the start bit) is stored in the read/write latch 400-3. The time required for the above macro service processing is determined by the baud rate timer 400-
Note that the time required for 5 to overflow is extremely short compared to the time required for overflow.

Now, by setting the transmit l/rega bit 400-62 to 111, the start bit is set to the read/write latch 40.
The baud rate timer 400-5 also starts counting up at the timing when the trigger bit turns ON. When the baud rate timer 400-5 again exceeds 70-, the timer overflow signal 40-5
The data (stop bit) stored in the read/write latch 400-3 is output to the external input/output line 40.
0-2 and baud rate timer 400-5e.
A transmission request signal is then output to the I10 request control section 300-1 in the serial interface control section 300 via the full transmission/reception request signal line 400-11, and the baud rate timer 400-5 is reset. and start it. The I10 request control unit 300-1 recognizes the transmission request signal as a macro service request, performs the same macro service as described above, and then sends the transmission data No. 0.
All bits (To) are transferred to read/write latch 400-3. and the next timer overflow signal 400-1
As a result, the transmission data 0th (To) is output to the external input/output line.

Thereafter, as described above, macro service processing is repeatedly performed intermittently using the overflow signal of the baud rate timer 400-5 until the MSC 200-2 becomes O, thereby realizing the transmission operation shown in FIG.

Then, in the macro service processing (2), the MSC20
0-2 becomes "0"9, the interrupt processing request signal is sent to the request control unit 300-10 via the transmission/reception request line 400-11.
1, the request control unit 300-1 recognizes the signal as a serial data transmission completion interrupt,
Activate the I10 request processing execution line 300-3 and
All interrupt request signals are output to the 10 request processing processing mode designation line 300-4. The I10 request reception unit 300-2 receives and receives the above signal, and causes the execution unit 101 to perform interrupt processing.

In the interrupt processing, the application program executes processing for continuous data transmission, such as storing the value "13" in the M3C 200-2 and storing the next transmission data in the transmission/reception data storage area 200-1. The above is one embodiment of the transmission operation of the present invention.

Next, the reception operation will be explained. First, MSC200-2
is preset to "10". The transmit/receive switching 7 lag 400-61 is set to "0" to set the reception mode, and the start bit detection line 400-8 is activated.

Start bit detection circuit 400-4 connects external input/output line 4
When the falling edge of the input level of 00-2 is detected,
After a certain period of time (half of one cycle specified by the baud rate), the level of the external input/output line 400-2 is checked again. If the level is low, it is assumed that a start bit has been detected, and the reception activation line 40-
1 (through l, the reception start signal is sent to the baud rate timer 400.
-5KIfl force.

When the baud rate timer 400-5 receives the reception activation signal, it is reset and then starts counting up. Then, the baud rate timer 400-5 overflows after a certain period of time (cycle specified by the baud rate),
At this time, the timer overflow line 400-1 is activated, the transmission/reception request signal 400-11'1I10 is output to the request control section 300-1, and the process starts again after being reset. Further, in response to the timer overflow signal, one bit of received data from the external input/output line 400-2 is launched into the read/write dual circuit 400-3.

The I10 request control unit 300-1 sends the transmission/reception request signal to
It is recognized as a macro service request to start sending and receiving data,
The machine 10 request processing execution line 300-3 is activated and a macro service request signal is output to the machine 10 request processing execution mode specification 1ia3004. I10 request reception unit 300-2
receives the above signal and forcibly sets the macro service processing code in the instruction register 101-5. The execution control unit 101-7 controls the PC based on the macro service processing code.
Prohibiting address update of IOI-1 and further PCIO
I-1, P8W101-2. General purpose register Sera) 101
While holding the value -3, the following macro service processing for reception is performed in the same manner as in the above-mentioned transmission.

■Check the value of the transmission/reception switching flag 400-61,
0'' and recognizes that it is a receiving operation.

■Read/write by timer over 70-signal 400-1.
The 1-bit received data stored in the write latch 400-3 is transferred to a predetermined bit of the internal bus 105 via the data input/output line 400-7. All 1-bit received data on this internal bus is stored in the temporary register 101-8.

(2) Concatenate the 2-byte data in the transmitted/received data storage area 200-1 to create 16 bit data, and shift it 1 pit to the right. This operation is performed in ALIJIOI-4. However, at this time, the 1-bit received data in the temporary register 101-8 is shifted to the MSB of the lower byte of the transmission/reception data storage area 200-1, and the LSB of the lower byte is shifted to the MSB of the upper byte. ■Reference).

0 MSC200-2, and if it is not "O", the process returns to the process that was being executed before the macro service process. Also, if the angle is 10°, baud rate timer 4
00-5i is stopped and an interrupt processing request signal is generated.

One bit of received data is stored in the transmitted/received data storage area 200-1 through one reception macro service process described above. Then, as in the case of transmission, the overflow signal of the baud rate timer 400-5 causes the MSC 200-
The macro service process is repeated 9 times intermittently until the number of bits reaches 2 to 10", and as shown in Figure 5, reception of 10 bit data (8 bits of received data, 1 bit of parity bit, 1 bit of stop bit) is realized. .

Furthermore, as in the case of transmission, IL, (SC200-2
When the interrupt request processing signal output in the macro service processing (2) is input to the I10 request control unit 300-1 via the transmission/reception request line 400-1 when the I10 is "O",
10 request control unit 300-1 determines it as a general interrupt signal. The I10 request reception unit then executes the execution unit 1.
01 to execute reception completion interrupt processing. In the reception completion interrupt processing, only the data bits are extracted from the received data stored in the transmitted/received data storage area 200-1, arranged into 8-bit data, stored in another area in the data memory 103, and parity bits, stop bits, etc. MSC to check bits and receive next data.
Processing such as setting 200-2 to 10'' is performed.

An example of serial transmission and reception using macro service processing has been described above, but compared to the conventional example, the serial interface block 400 in this embodiment eliminates the need for shift registers, buffer registers, etc. Since it uses bit boat e,
The amount of hardware is extremely small and the area occupied on the chip is also small.

Since the transmission and reception of serial data is performed by the macro service processing, software processing by the user's program is unnecessary, and the execution efficiency of the execution unit 101 does not deteriorate.

In the above embodiment, the case where the transmission data is 11 bits and the reception data is 10 bits has been described, but other data lengths can also be easily realized. Furthermore, in this embodiment, transmission and reception.

It is also possible to create separate flowcharts for each macro service process.

〔Effect of the invention〕

As explained above, the serial data processing device according to the present invention performs serial data transmission and reception processing using macro service processing, thereby eliminating shift registers, buffer registers, etc., without reducing the execution efficiency of the execution section. Since the serial interface can be configured with extremely small hardware, the area occupied by the serial interface on the chip of the serial data processing device can be reduced, and the serial data processing device can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the serial data processing device of the present invention, FIG. 2 is a detailed block diagram of the serial interface in FIG. 1, FIG. 3 is a flowchart of the macro service of the present invention, and FIG. 5 is a sequence diagram of a receiving operation in the present invention, and FIG. 6 is a block diagram of a conventional serial data processing device. 100... Serial data processing device, 100-
1...External terminal, 101...Execution unit,
101-1...Program counter (PC),
101-2...Program status word register (P8W). 101-3...General-purpose register set, 101-
4... Arithmetic logic unit (ALU), 10
1-5...Instruction register (Il(,), 101
-6...Instruction decoder (DEC), 101-7
...Execution control unit (EXU), 101-8...
...Temporary register, 102...Program memory, 1o3...Data memo 1c 10
3-1... Transmission data storage area, 103-2.
...Received data storage area, 1o4 ... Serial interface, 104-1 ... Transmission line, 104-2 ... Transmission control section (TC), 1
04-3...Transmission shift register (TS),
104-4...Transmission data buffer (Tf) D
), 104-5... Transmission completion signal line, 104
-6 Old... Transmission request signal line, 104-7...
Transmission permission line, 104-8...Reception line, 10
4-9...Reception control section (RC)% 104-
10...Reception shift register (R8), 10
4-11... Reception data buffer (几DB)
, 104-12... Reception completion signal line, 104-
13... Reception permission line, 104-14...
- Reception start line, 104-15...Baud rate generator (BR, G), 104-16...Shift clock line, 105...Internal bus, 106
...Boat block, 106-1 Old read/write latch, 106-2 External input/output line, 106-3 Data input/output line, 106
-5-°-=Reception request M, 200...Macro service register group, 200-1...Transmission/reception data storage area, 200-2...Macro service counter (MSC) ), 300...°Zorial Louis/Li7 process control unit, 300-1...I10 request control unit, 300-2...I10 request reception unit, 30
0-3...I10 request processing execution line, 300-4
...I10 request processing processing mode specification line, 400.
... Serial ink 7 ace block, 400-
1... Timer overflow line, 400-2.
...External input/output line, 400-3 ... Read/write latch, 400-4 ... Start bit detection circuit, 400-5 ... Baud rate timer, 400-6... Serial mode register,
400-61...Transmission/reception switching hook, 400
-62...Transmission trigger beep), 400-7...
...Padata input/output line, 400-8...Start bit detection start line, 400-9...Transmission activation line, 400-10...-Reception activation line, 400- 1
1...Transmission/reception request line agent Patent attorney Susumu Uchihara//Yuhaku 2 diagrams 1 vote conversion HδC-/2 F=vote PMδC= // ``Yotoyo 廂C:〆IP:Horizontal C=9 F=horizontal MSC=δ F==yo gain; 7 F koyoden y, 5c=t F yo=yo MδC bow E yoyoyo MδC ko 4 F==73 N5C=3 ~L loss

Claims (1)

[Claims] Serial data processing that includes a memory section that stores programs and various data, an execution section that interprets and executes program contents, a status register that stores status information indicating the execution status, and a serial interface section that sends and receives serial data. In the apparatus, the execution unit interrupts execution of the program while retaining the status information indicating the execution status of the program in the status register without moving it from the status register, in response to the serial data processing request signal from the serial interface unit, and After executing data transmission/reception processing, restarting the program execution processing, and causing the serial interface unit to repeatedly generate the processing request signal at a predetermined timing until the serial data transmission/reception is completed, and perform the processing intermittently. A serial data processing device characterized by: