JPS638983A - Enlarging/reducing system for input image - Google Patents

Abstract

PURPOSE:To improve the image input performance of an image scanner by changing an enlarging ratio and a reducing ratio optionally and continuously. CONSTITUTION:A flip-flop 11 has a function to sample binarization image data from a CCD with a clock CLK. At the output of the flip-flop 11, reduced and expanded variable power data appear by the length of the period of the clock CLK. The period of binary data supplied from the CCD to the flip-flop 11 is tO, the period of the clock CLK supplied from a variable clock generating device 12 to the flip-flop 11 is tS, and then, an expanding image is obtained at the time of setting to tS<tO, a full size is obtained at the time of tS=tO and at the time of setting to tS>tO, the reducing image is obtained. A clock period tS is changed by a knob 18 of a variable resistance 17 in the variable clock generating device 12.

Description

[Detailed Description of the Invention] [Summary] Image information read by an image scanner is sampled with a sampling signal whose synchronization is continuously variable, so that the enlargement/reduction ratio of the input image can be continuously changed.

[Industrial application field]

The present invention relates to an image input method using an image scanner, and particularly to a method for arbitrarily enlarging or reducing an image read by an image scanner.

[Conventional technology]

In general, in image information processing, it is often necessary to fit images input by an image scanner into a fixed or specified arbitrary size for reasons such as jJig collection or storage/transfer.

In such a case, processing to enlarge or reduce the two images is performed, but conventionally this has been done by appropriately sampling the binary image data output from the image scanner.

FIG. 6 shows an example of a conventional enlarging/reducing circuit, and FIG. 7 is a waveform diagram showing an example of the operation of the circuit of FIG.

In FIG. 6, 1 is an image, 2 is a CCD, 3 is an A/D converter, 4 is a binarization circuit, 5 is an enlargement/reduction circuit, 6 is a flip-flop, and 7 is a clock selection circuit.

The analog image signal resulting from the scanning and reading of the image 1 by the CCD 2 is converted into a multi-level digital signal by the A/D converter 3, and then converted into a multi-level digital signal by the binarization circuit 4 using an appropriate threshold value. Converted to digitized image data.

This binarized image data is input to the flip-flop 6 of the enlargement/reduction circuit 5. This binary image data is written into the flip-flop 6 in synchronization with the clock CLK, that is, sampled, and transferred as variable-magnification data.

The clock applied to flip-flop 6 is:

It is supplied from the clock selection circuit 7, and the ratio between the period of the binarized image data and the period of the clock provides the values of the enlargement rate and the reduction rate.

The clock selection circuit 7 selects clocks C with three different periods.
LKI, CLK2. One of CLK3 is selected by two pin selection signals 5ELL and 5EL2. As shown in Figure 7, CLK
I is the same period as the binarized image data, CLK2 is CLK
The period is 5/4 times l, and CLK3 is 3/4 times the period of CLKI.
It has a period of 4.

Next, the operation of the enlargement/reduction circuit 5 will be explained using the waveform diagram shown in FIG.

In FIG.

2 is the binary image data input to the flip-flop 6, and A, B, C, D, E, and F are the binary image data input to the flip-flop 6.

Each represents a sequential period of binarized image data.

The data for each cycle corresponds to 9 pixel values.

3 represents CLKI and scaled data sampled by CLKI. This scaling data is CL'K
Since I is synchronized with the input binary image data, the enlargement ratio (reduction ratio) is 1.

2 represents CLK2 and variable scale data sampled by CLK2. This scaling data is the input 2
This is because the digitized image data is sampled at CLK2, which is 574 times the cycle.

The binary image data is reduced to 415 pixels.

3 represents CLK3 and variable scale data sampled by CLK3. This scaling data is the input 2
This is because the digitized image data is sampled at CLK3, which is 374 times the cycle.

This is binary image data enlarged 473 times.

[Problem that the invention seeks to solve]

In this way, in the conventional enlargement/reduction method, the enlargement rate and reduction rate are determined by several types of clocks prepared in advance.
Generally, several types of crystal oscillators are used as a clock source, so the step of the enlargement/reduction ratio becomes coarse, and there is a problem in that fine-grained enlargement/reduction cannot be performed.

[Means for solving problems]

The present invention provides an image scanner for enlarging and enlarging an input image.
The clock source used for reduction consists of a variable period oscillator. Magnification, in an easy way! This allows the IM ratio to be changed continuously.

FIG. 1 shows the basic structure of the present invention in an exemplary manner.

In FIG. 1, 10 is an enlargement/reduction circuit, 11 is a flip-flop, and 12 is a variable clock generator.

13 and 14 are monostable circuits, 15.16 is a time constant circuit, 17 is a variable resistor, 1st is the knob of variable resistor 17, 19
is a sub-scanning signal generation circuit.

The flip-flop 11 has a function of sampling the binary image data from the COD using the clock CLK.

At the output of the flip-flop 11, variable magnification data that is 1 wJ smaller or larger appears depending on the length of the cycle of the clock CLK.

Clock CLK is supplied from variable clock generator 12.

The variable clock generator 12 consists of two monostable circuits 13.1
This is a self-excited oscillator constructed by connecting 4 in a loop, and the clock period can be arbitrarily changed by adjusting the variable resistor 17 included in the time constant circuit 5 of the monostable circuit 13 with the knob 18. be able to. Further, the pulse width of the clock is determined by the time constant circuit 16 of the monostable circuit 14.

The sub-scanning signal generation circuit 19 generates, for example, a rask sampling signal in the sub-scanning direction in correspondence with the period of the clock CLK, which is a sampling signal in the main-scanning direction, and outputs it simultaneously with the scaled data from the flip-flop 11.

[Effect]

The effect of the configuration of the present invention shown in FIG.

Use the waveform diagram in Figure 2 to determine customs.

In Figure 2, ■ is a flip-flop 1 from C and CD.
This is binarized image data supplied to 1.

Its period is indicated by to. Also, ■ is a clock CLK supplied from the variable clock generator 12 to the flip-flop 11, and its period is expressed as 1 s.

Here 1. <1. If you set t, like this, you can get an enlarged image, and when 1,=10, you get the original size.

If 1s is set such that 1s>10, a reduced image can be obtained.

Knob 18 of variable resistor 17 in variable clock generator 12
By providing on the operation panel, the clock period t,
can be easily changed from the outside.

〔Example〕

FIG. 3 shows one embodiment of the present invention.

Figure 3 shows an implementation in which the feeding speed in the sub-scanning direction is adjusted in response to enlarging/reducing (variable magnification) in the main scanning direction for binary image data, and enlargement/reduction in the sub-scanning direction is performed. This is an example.

In FIG. 3, 10 is an enlargement/reduction circuit, 11 is a sampling flip-flop, 12 is a variable clock generator, and 18 is a knob for the variable resistor 17.

19 is a sub-scanning signal generation circuit, 20 is an input port 21 is M
PU, 22 is a motor drive circuit, and 23 is a sub-scanning direction feed motor.

Knob 18 of variable resistor 17 in variable clock generator 12
By turning , a clock CLK is generated which gives the desired enlargement or reduction ratio.

It is supplied to flip-flop 11.

As a result, the input binarized image data.

Sampled in flip-flop 11.

The data is output as variable magnification data enlarged or reduced in the main scanning direction.

At this time, the clock CLK is also supplied to the sub-scanning signal generation circuit 19, and passes through the manual port 20 therein to the MPU 21.
given to.

The MPU 21 checks the cycle of the clock CLK.

Then, in the sub-scanning direction, the rotation speed of the sub-scanning direction feed motor 23 necessary to produce the same enlargement or reduction ratio is calculated, and the sub-scanning direction feed motor 23 is controlled via the motor drive circuit 22. drive

FIG. 4 shows another embodiment of the present invention, in which a rask sampling signal in the sub-scanning direction is generated from the clock CLK.

In FIG. 4, 10, 11, 12, 18, and 19 are the same elements as in FIG. 3, and 24 is a memory for storing binarized pixel data.

Clock CLK output from variable clock generator δ12
is applied to the flip-flop 11 and the sub-scanning signal generation circuit 19. The magnification data in the main scanning direction output from the flip-flop 11 is as follows.

The information is sequentially written into the memory 24.

The sub-scanning signal generation circuit 19 measures the period of the clock CLK, creates a rask sampling signal in the sub-scanning direction, and applies it to the memory 24 as a write control signal.

As a result, in the memory 24, the flip-flop 1
The variable magnification data in the main scanning direction output from 1 is further sampled by the rask sampling signal Gmi, and is output as variable magnification data that is also enlarged/reduced in the sub-scanning direction.

FIG. 5 shows still another embodiment of the present invention. This embodiment is a modification of the embodiment shown in FIG. 4, but unlike the embodiment shown in FIG. It is possible to generate a rask sampling signal in the sub-scanning direction.

The knob 25 provided in the illustrated sub-scanning signal generation circuit 19 is for adjusting the variable resistance included in the time constant circuit in the sub-scanning signal generation circuit 19, and by turning this knob, .

The period of the rask sampling signal can be changed arbitrarily.

〔Effect of the invention〕

As described above, in the conventional method, only several types of enlargement or reduction ratios could be used, but with the present invention, it is now possible to change them arbitrarily and continuously, improving the image input performance of the image scanner. Significantly improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is an operational waveform diagram explaining the present invention in detail, and FIGS. 6 is a block diagram of a conventional enlarging/reducing circuit, and FIG. 7 is an operating waveform diagram of the conventional circuit shown in FIG. In Figure 1. 10: Expansion/reduction circuit. 11: Flip-flop. 12: Variable clock generator,' 17: Variable resistor. 18: Snack. 19: Sub-scanning signal generation circuit. Patent Applicant: Usatsuk Electronic Industry Co., Ltd. Agent: Patent Attorney: Fumihiro Hase (2 others)
−−−−−−−−−−−−−−−−−−−11−−−−
-'' J Mi 4th August's Nona Burial ll I Re month 1 to $ 1 Ward i, <9 Matsuto o,・o. Shoulder back, 〉9 Reduced size ≧i5 Light 〢・Tsuru movement γν shape 2 Mouth 3 Figure L--1----1 ------1 -1--'' 4 Evening light nose Absolute horizontal A' (n2) $ 4 Figure -----,, -+--++++--J 11
F1 up and the bell overturned” (Mu3) $5I21 Figure 6

Claims (1)

[Claims] An image scanner is equipped with a flip-flop that samples binarized image data generated based on an input image, and a variable clock generator that can continuously manually change the clock cycle, and output from the variable clock generator. By applying a clock to the flip-flop as a sampling signal and appropriately setting the length of the clock cycle with respect to the cycle of the binarized image data, an arbitrary enlargement or reduction ratio can be obtained. Enlargement/reduction method of input image.