JPS60123888A - Display character bordering generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a display character border generation circuit for sharpening characters displayed on a cathode ray tube.

Prior Art and Problems The resolution of cathode ray tubes in general home television receivers is low, but when viewing moving images of people or landscapes, vision is deceived and even though the outlines are blurred, the overall image on the screen appears to be accurate. However, when displaying characters, if the resolution is low, the blurring of the outline of the characters will clearly appear, and if the characters are small, it will be difficult to judge what kind of characters they are <tt4. Furthermore, when characters are displayed in white, there is a problem in that the characters become invisible if the image surrounding the characters is also white. Therefore, a black border is used around the letters.

FIGS. 1 and 2 are explanatory diagrams of this, the former showing characters without borders, and the latter showing characters with borders. In this example, the character is the number "2", and the small squares correspond to memory cells on the memory and dots on the display screen. Character part "1"
”, if the peripheral part of the character is '0'', the CG1 dot line output in the A-A section of Figure 1 is 1.100000011
This is shown in waveform W1. The one-dot line character signal on the line B--B in FIG. 2 is the same as that on the line A--A, and is indicated by W2. W3 is a border signal, character signal W2
1 bit is added to both sides of the literature section, and the polarity is reversed (1 is changed to 0). “0” is black, ul”
When W2 and W3 are ORed and displayed, white characters with a black border as shown in the figure appear.

Framing signals are generated using large computers in television broadcasts and the like. There is also an analog method for edging the characters by recessing (lowering the level) both ends of the character portion of the signal that controls the brightness of the scanning line, but there is no suitable method for easily edging the characters digitally.

OBJECTS OF THE INVENTION The present invention provides a relatively simple digital circuit that outputs a signal that creates a black border around a character and makes the ring of the character stand out.

Structure of the Invention The present invention provides a display character edging generation circuit for making characters displayed on a cathode ray tube clearer, including a circuit for edging the left and right sides of the character, a circuit number for edging the top and bottom of the character, and a circuit number for edging the left and right sides of the character. The circuit includes a first circuit that receives serial signals for each line of the character generator sequentially and provides a delay of two clock periods, and a first circuit that provides a delay of one clock period to the logical sum of the input signal and output signal of the circuit. and a second circuit that generates a border signal for the output character signal of the fourth circuit, which will now be described with reference to embodiments.

Embodiment of the Invention FIG. 3 shows an embodiment of the invention, which is a circuit for adding black dots to the left and right of a character section. lO is a character generator (CG), 12 is a shift register, 14, 16.1
8 is a flip-flop, and 20 is an or gate. CG
The IO stores character patterns in dots such as 7x9, and outputs one dot line at a time in synchronization with television scanning. Assuming that one dot line is composed of 5 bits, the 5 bits are loaded in parallel into the 5-bit shift register 12 and output one bit at a time in response to the shift clock CLK. The output (2) of the shift register 12 is input to the flip-flop 14, the output (2) is input to the next flip-flop 16, and the -output (2) is input to the OR gate 20 together with the output (2). Since the flip-flops 14 and 16 are D type, the output is the input delayed by one clock.

Examples of the waveforms of the outputs ■, ■, ■ are shown in FIG. 4 (11 (21+31).

The output 0 of the OR gate 20 is as shown in FIG. 4 (4), and when this is input to the D-type flip-flop 18, the output
becomes like (5). The reversal of ■ and ■ is W 2 in Figure 2.
, W3, the former is used as the character signal Sc, and the latter is used as its border signal Sf. Note that the inverted output (2) of (2) can be obtained by taking the output of the flip-flop 18 from the Q terminal.

In this way, bordering the left and right sides of the text area is the third step.
It can be executed using the circuit shown in the figure. To create a border around the entire perimeter of the text,
In addition to this, it is also necessary to border the top and bottom of the text.
A circuit with such a function is shown in FIG.

In FIG. 5, the same parts as 3E are given the same reference numerals, and a flip-flop (FF) 14.16°18 outputs a character signal Sc and a border signal Sf. Two sets of CGs, IOA and JOB, are provided, and correspondingly, two sets of shift registers, 12A and 12B, are provided. Upper and lower borders are performed by checking the next scanning line and adding a border signal if it contains a character portion, so installing two sets of CCs and the like is to deal with this. Furthermore, since this circuit interpolates between dot lines to display a character pattern of 7×9 dots as 14×1B dots, the shift clock also uses CLK2, which has twice the frequency of CLK1. 22 is a display character selection circuit; 24 is a memory for storing display characters selected by the circuit 22; 28.30 is a D-type FF that provides one clock delay, 26
are shift registers 12A, 12B and D-type FFs 28, 3
In response to the output of 0, output a as shown in FIGS. 8 to 12.

Decoder producing c, g, 32, 36.3B, 40.4
2.48 is D type FF, 44.46 is Nant gate, 82
is a television receiver. The circuit 84 receives the clock CLK3 and outputs the decoder control clock CPT and the border control signal 12.
This is a control circuit that generates a D-type FF 80, a NAND gate 52, 54°60.62, 64.66, a NOR gate 68, 70°72.74, an AND gate 76.4, a bit counter 50, and an inverter.

The 4-bit counter 50 counts the clock CLK3 and outputs the first to fourth stage counter outputs PO to P3 with the waveform shown in FIG.
Output. The decoder control signal CPT is obtained as a NOR (74) of an AND ('76) of PO and Pl and a NOR (72).

FIG. 5 Tbl is a detailed diagram of the decoder 26. As shown in this figure, the decoder 26 consists of inverters 1 to I5, Nant gates Nl to N1□, an inverter I6, and a flip-flop FF, and includes shift registers 12A and 12B, outputs OI to 04 of flip-flops 28 and 30, and control signals. After receiving CPT and clock CLK 2, output a will be described later.
+'+g is produced.

The operation of the circuit shown in FIG. 5 will be explained by taking as an example the case where the number 3 in FIG. 6 is displayed with a border. Number 3 is 5 in CG
x7 dots are stored, d1 to d7 are each dot line, and b1 to b5 are each bit on the dot line. The figure shows the state after interpolation, and as can be seen by excluding the interpolated bones and edges, the d1 line is b2. b3. b4 is 1 (white), and in the d2 line, bl, b, and s are 1, and this applies hereafter. Interpolation bits are indicated by dotted lines. In a method incorporating this interpolation, one bit line is displayed in two scans. Timing T1-T5
The output states of each part in FIG. 5 are shown in FIGS. 8 to 12.

At timing T1, the state is as shown in FIG.

That is, the character code of number 3 is output from the memory 24, and this becomes the address of CGIOA and IOB.
The pattern of tontoline dO is output from CGIOB, the pattern of tontoline d1 is output from CGIOB, and the pattern of tontoline d1 is output from register 12A.
, 12B.

Incidentally, in addition to the character code, an address specifying a dot line is also added to the CG address, but since the details of this point are well known, their explanation will be omitted. The outputs a, c, and g of the decoder 26 are as shown in FIG. That is, a is the margin dQ, and g is the dot line di (more specifically, its upper half)
These signals pass through FFs 32, 36, etc. and are delayed by one period of the shift clock CLK2. C=“1
'', the Nantes gate 42 is open, and therefore the character signal Sc becomes a delayed output of a, which is 0 in this case.The border signal Sf is "l" (white), that is, without border, but this is g The inversions j and e of the delayed outputs of
is 1".The signal j2', m becomes A'=Q, m=1 only at the beginning and end, and j!=m=4 in the middle.
become.

At timing T2, the situation is as shown in FIG. That is, at this point, scanning is still on the dO line, so the output of CGIOA is dO and the output of CGIOB is dl, which is the same as timing T1. But l.

Since m both become 1, the Nantes gate 46 opens and n=k
become. n becomes the edge signal Sf after one clock delay by the FF18. This gives a 3-bit (but half the width) border around the top of the number 3.

At timing T3, the situation is as shown in FIG. That is, CGI
The output of OA is d2, and the output of CGIOB is d3. These outputs and the one-clock delayed outputs di and d2 from FFs 28 and 30 are input to the decoder 26, and outputs a and c from these are input.

g is as shown in the figure. In other words, NAND output d of a and c
becomes the character part (interpolated) on the T3 line, and g
becomes the border. g corresponds to the lower half of di. These signals d and g propagate through FFs 34, 36, etc., d becomes Sc after a 3-clock delay, and g is input to the (j)+nd gate 44 after a 3-clock delay and inversion, and the NAND of e and Sc is input. The left and right edges as explained in Fig. 3 are done.
The output becomes n. This becomes the edge signal Sf with a one clock delay.

At timing T4, the state becomes as shown in FIG. That is, C'Cl
The outputs of 0A and IOB remain unchanged, but decoder 26 produces the output of the next scan line with signal CPT, and a, c, and g become as shown. Since g is a signal indicating the character portion above or below the scanning line, it becomes as shown in the figure, but in this case it has no meaning because the characters continue. Left and right edges are made using e and SC. ' At timing T5, it becomes as shown in FIG. In this case, the input to the decoder 26 is d3. d2. , d4, and the output a
, c, and g are as shown in the figure. As is clear from the explanation so far, C is an interpolation bit added to the leading edge, a is a character bit with an interpolation bit added to the trailing edge (if there is one), and g is a character bit added to the upper and lower edges as described above. It's a bit. The interpolation bits are generated in the decoder 26 by looking at the character bits on the top and bottom scan lines of the (current) scan line.

As described in detail, the invention has the advantage that it is possible to frame characters with a relatively simple circuit, and in particular, only a left and right edge can be done with an extremely simple circuit.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of characters stored in CG, Fig. 2 is an explanatory diagram of framed characters, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is an explanatory diagram for explaining its operation. Waveform diagram, 5th
The figure is a block diagram showing the overall embodiment of the present invention, Figure 6 is an explanatory diagram of displayed characters, Figure 7 is a clock waveform diagram, and Figures 8 to 12 are waveforms explaining operations at each timing. It is a diagram. . In the drawing, CGIO is a character generator, 12 is a shift register, 14. '16 is a first circuit that provides a delay of 2 clock periods; 18 is a second circuit that provides a delay of 1 clock period; 26, 36, 38, 40. '44.46.48 is a circuit that borders the top and bottom of characters. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1

Claims (1)

[Scope of Claims] (11) It is equipped with a circuit for edging the left and right sides of the characters displayed on the screen and a circuit for edging the characters at the top and bottom, and the circuit for edging the left and right sides of the characters is for each dot line of the character generator. A first circuit that receives a serial signal sequentially and gives a delay of two clock periods; and a circuit that gives a delay of one clock period to the logical sum of the input signal and output signal of the circuit, and applies a delay of one clock period to the output character signal of the first circuit. and a second circuit that generates a border signal. (2) The circuit for bordering the upper and lower portions of characters checks the scanning line one above and below the current scanning line. The patented circuit is characterized in that, when a character part is included in the character part, a border signal having the length of the character part is generated. (3) The border signal is logically ORed with the character signal. 3. A display character border generation circuit according to claim 1, wherein the display character border generating circuit is set to a level that gives priority to the character signal when the display character signal is displayed.