JPS638488B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to CRT displays. In conventional CRT display devices, typically
The character display position on the screen and the read address of the refresh memory are fixedly corresponded to each other as shown in Table 1.

[Table] Furthermore, as a type of improved CRT display device, one has been proposed in which the read address of the refresh memory can be offset by an offset amount α from the character display position. Now, if α=40, the relationship between the character display position and the refresh memory read address is as shown in Table 2.

[Table] By doing this, it is possible to scroll the entire screen in the vertical direction by simply changing the value of the offset amount α. FIG. 1 is a block diagram showing an example of a conventional CRT display device. In the figure, 40 is an LSI
50 is a ROM (Read Only Memory) that stores the processor program, and 60 is a data memory RAM (Randon Access Memory) for the processor.
Memory) and is connected to the address bus 42 and data bus 44 of the processor 40. Reference numeral 10 denotes a host computer, and data transmission and reception between the host computer and the CRT display device is performed via an interface controller 30. That is, display data is sent from the host computer 10 to the refresh memory 70 of the display device, and data input to the display device is taken into the host computer. Reference numeral 20 denotes a keyboard, and display data entered by a key is written into a refresh memory 70. 200 is a timing control circuit, and a block diagram of its main part is shown in FIG. In FIG. 2, 210 is an oscillator which generates a dot timing clock 215. 220 is a dot counter, which defines the number of horizontal dots in one character. Output 225 of dot counter 220
is a character clock that occurs once per horizontal character time. 230 is a character counter, which defines the total number of characters per raster. 240 is a decoder which decodes the output of the character counter 230 and outputs the horizontal synchronization signal 24.
Generates 5. 250 is a raster counter,
Specifies the number of vertical dots in one character. 260 is a line counter, which defines the total number of lines per frame. Output 26 of line counter 260
6 is a frame clock that occurs once per frame. Further, 270 is a decoder, which decodes the output of the line counter 260 and generates a vertical synchronization signal 275. FIG. 3 shows a time chart of the main parts of the timing control circuit. Returning to FIG. 1 again, the operation of a conventional CRT display will be explained. Display data input from the host computer 10 or the keyboard 20 is stored in the refresh memory 70 in the form of character codes. Data in the refresh memory 70 is sequentially read character by character in synchronization with the raster scan. That is, the character counter 230
output 235 and output 26 of line counter 260
5 is supplied to the address converter 300, and its output 305 becomes the read address of the refresh memory 70. The address converter 300 is a circuit device that converts a two-dimensional address into a one-dimensional address, and those skilled in the art can realize its specific circuit in various ways, and will not be discussed here. The output 75 of the refresh memory 70 is output to the character generator 8 along with the output 255 of the raster counter 250.
0, and the dot pattern 85 corresponding to the raster address of the character code is read out and supplied to the parallel-to-serial converter 90. The parallel/serial converter 90 converts the parallel dot pattern into a serial dot pattern 95 using the dot clock 215 and converts it into a serial dot pattern 95 on the CRT display 1.
Output to 00. In addition, the CRT display 100 is supplied with a horizontal synchronization signal 245 and a vertical synchronization signal 275, and characters are displayed on the CRT display 100 by these signals. In the conventional display device described above, as shown in FIGS. 4A and 4B, the display character position on the screen (Figure A) and the address of the refresh memory (Figure B)
The correspondence has been fixed. In addition, some improved display devices are designed to have an offset in the correspondence between the two addresses in order to perform scrolling. However, these conventional displays cannot display the contents of the refresh memory at an arbitrary address on an arbitrary line of the display screen.
Therefore, the display data stored in the refresh memory can be reassembled and displayed, or any part of each page of the multiple pages of refresh memory can be selectively read out and displayed on the CRT. Extensive software support is required to display images simultaneously on the screen or to display scrolling images limited to an arbitrary portion of the display screen, which is virtually impossible. It is an object of the present invention to provide a display device in which a read address of a refresh memory corresponding to a character position on a display screen can be externally specified in correspondence with a line address. To provide an improved CRT display device capable of reassembling and displaying display data stored in a refresh memory with a small burden of software. The gist of the present invention is that the address setting of the refresh memory is forcibly given from the outside in addition to the normal address setting. For this reason, in the present invention, an address setting section that performs address setting plays an important role. The optimal external address setting according to the present invention is to be performed on a line-by-line basis. Hereinafter, the present invention will be explained in detail. The content of the present invention will be understood from the drawings and description provided below. FIG. 5 is an overall block diagram of a CRT display device according to the present invention, which is characterized by an address setting device. In the figure, the same parts as in FIG. 1 are designated by the same numbers. 400 in Figure 5
is an address setting device, which is connected to the address bus 42 and data bus 44 of the processor, and is connected to the output 265 of the line counter 260 and the character clock 22 from the timing control circuit 200.
5 and a raster clock 236 are introduced. Output 445 of address setting device 400 is a read address signal for reading display data from refresh memory 70. FIG. 6 is a block diagram showing an embodiment of the address setting device. In the figure, 420 is an address multiplexer, which switches the output of the address bus 42 of the processor 40 and the output 265 of the line counter 260 with a signal 415.
The signal is selectively output to the output 425 by switching. 410 is an address decoder which decodes the contents of the address bus 42 and outputs the switching signal 4.
Outputs 15. Reference numeral 430 denotes a start address register, which is made up of a group of registers whose number is equal to the number of display lines of the display device (for example, 16 according to the display example shown in FIG. 4). 440 is an address counter, and its output 445 is supplied to the refresh memory 70 and becomes a read address for display data. 450 is a bus driver, and the output 435 of the start address register 430 is output to the data bus 44 of the processor 40 via this bus driver. The start address register 430 is constituted by a RAM, and can be written to and read from by the processor 40. First, when writing to the start address register 430, a write address is specified by the address bus 42. If the address information at this time is the address space assigned to the start address register 430, the output 415 of the decoder 410 becomes "1", and the address of the address bus 42 becomes the address space assigned to the start address register 430.
Then, the contents of the data bus 44 are written to the register specified by the above address among the plurality of start address registers. Next, in the case of reading, the contents of the register designated by address 425 are output to data bus 44 via bus driver 450 and read into processor 40. When the output 415 of the decoder 410 is “0”, that is, the start address register 43
0 is accessed by processor 40, the output 265 of line counter 260 is passed through multiplexer 420 to start address register 4.
30, and for each row address, the contents of the start register are read out as output 435, which output is fed to the data input of address counter 440. The address counter 440 is composed of a counter capable of synchronous loading, and the carry output 236 of the character counter 230 is introduced into its load control input terminal LD.
A character clock 225 is introduced into the clock input terminal CK. Therefore, the output 435 of the start address register 430 read out for each row address is preset in the address counter 440 for each starting point of each raster in each row, and the character clock 225 is then used as the starting point of the address until the end of the raster. By counting , the refresh memory address of the data to be displayed on that line is generated.
This address generation is repeated for all lines, and all addresses necessary for displaying one screen are generated. FIG. 7 shows an address setting device 400.
It shows the operation time chart. FIG. 7 shows the address generation operation in the 0th line and 1st line when the total number of horizontal characters is 63 and the number of horizontally displayed characters is 40. However, in this case, it is assumed that "0" is preset in the start address register of the 0th row and "40" is set in the start address register of the 1st row. In the following explanation, the number of displayed characters per line is 40, and the number of displayed lines per screen is 16. FIG. 8A shows an example of the contents of the start address register 430 corresponding to a display line, and FIG. 8B shows an output status table of the address counter 440 at that time. Figure 9A shows a refresh memory with a capacity of 640 characters, and Figure 9B has a display capacity of 640 characters.
A CRT display is shown, and FIG. 9C shows the set value of the start address register 430 at this time. This figure shows a typical example in which the correspondence between the display character position on the CRT screen and the read address of the refresh memory is fixed. Figure 10A shows an example in which half of the lower address of page 0 and half of the lower address of page 1 are combined and displayed on one screen from a refresh memory having a capacity of two pages (two screens). ing. FIG. 10B shows the set value of the start address register 430 at this time. FIG. 11A shows an example in which data for 1/4 screen of each page is selectively read from a refresh memory having a capacity of 4 pages, and is combined and displayed on one screen. FIG. 11B shows the set value of the start address register 430 at this time. FIG. 12A shows an example in which only lines 8 to 15 of the display screen are scrolled and displayed, and FIG. 12B shows the setting value of the start address register 430 at this time. In the figure, the set values (marked with * in the figure) from line address 8 to line address 15 are rewritten by processor 40, and a desired scroll display is performed. FIG. 13A shows an example in which only 8th to 11th rows of one screen are scrolled, and FIG. 13B shows the set value of the start address register at this time. Only the setting values in lines 8 to 11 in the figure are processed by processor 4.
It is rewritten with 0 and the desired scrolling display is performed. As is clear from the above description, according to the address setting device according to the present invention, the read address of the refresh memory is determined on a line-by-line basis. It has started to selectively read out any part of each page from the display data of the page and display it simultaneously on one screen, and also to selectively scroll and display any part of the displayed image. The effect is extremely large because it can be achieved simply by writing the contents of the address register. Selective scroll display of any part of the display screen is performed using the start address register 43 in FIG.
This is executed by changing the set value of 0 in the processor 40 of FIG. The start address register 430 is provided corresponding to the display line address of the display screen, and selective scrolling display can be performed by changing the contents of the start address register only for the part corresponding to the line address to be scrolled. can. For selective scrolling of any part of the display screen, there are two types of scrolling: line-by-line scrolling and character-by-character scrolling. Scrolling in units of lines is to scroll in the line direction of the display screen, that is, in the upward and downward directions, and the value set in the start address register 430 is as shown in equation (1). A' = A±n・H Where, A': Start address after change A: Start address before change n: Number of scroll step lines H: Number of displayed characters per line ±: When scrolling upward + down Direction - n is the number of scroll step lines, n=1
If n=3, then one setting change will scroll one line up or down, and if n=3, one setting change will scroll three lines at a time. FIG. 14 shows the start address register 43 in line-by-line scrolling when n=1 and H=40.
An example of the correspondence between a setting value of 0 and a display screen is shown. This example shows an example in which only row addresses 13, 14, and 15 are selectively scrolled upward, and only the contents of the start address registers corresponding to row addresses 13, 14, and 15 (* in the figure) are shown.
display) settings are changed. 14 shows the set value of the start address register and the display screen in the initial state, and 2 shows the set value of the start address register and the CRT display screen when scrolling upward by one line. 3 shows the setting value of the start address register and the display screen when the screen of 2 is further scrolled upward by one line. From the above diagram, it will be understood that by changing the contents of the start address register in units of n·H (in this example, n·H=40), scrolling can be performed in units of lines. Character-by-character scrolling involves scrolling the display screen horizontally in character-by-character units, and the value set in the start address register 430 is as shown in equation (2). A'=A±n...(2) Here, A': Start address after change A: Start address before change ±: + when scrolling to the left, - when scrolling to the right - n is the number of scroll step characters Yes, N=
If it is 1, one character change will scroll one character to the left or right, and if N=3, one setting change will scroll three characters to the left or right. Figure 15 shows the start address register 430 in character-by-character scrolling when n=1.
An example of the correspondence between the setting values and the CRT display screen is shown. This example shows an example of selectively scrolling only row addresses 13, 14, and 15 to the left, and only the contents of the start address registers corresponding to row addresses 13, 14, and 15 (indicated by * in the figure). settings are changed. 15 shows the set value of the start address register and the display screen in the initial state, and 2 shows the set value of the start address register and the display screen when scrolling one character to the left. 3 shows the setting value of the start address register and the display screen when the screen 2 is further scrolled one line to the left. From the above diagram, it will be understood that by changing the contents of the start address register in units of n (in this example, n=1), scrolling can be performed in units of characters. As is clear from the explanation using the examples in FIGS. 14 and 15, according to the embodiment of the present invention, by changing the settings in the start address register according to equation (1) or equation (2), You can freely realize scrolling by units and scrolling by characters. Furthermore, if the timing control circuit shown in Fig. 2 and the address setting device shown in Fig. 6 are integrated into one chip using LSI technology, a CRT display device having many of the effects of the present invention can be easily realized with an extremely small number of parts. be able to. In each of the above embodiments, a computer (processor)
Although the setting of the start address has been described above, it may also be set from another dedicated device. Furthermore, although the start address is set as a line address, it may be set in character address units. However, in this case, the interface between the timing control circuit and the address setting device will naturally be different. That is, when changing the screen by setting in character address units, the value of the start address written in the start address register 430 may be changed to a desired value. For example, FIG. 8A shows an example of the contents of the start address register 430 corresponding to the display line of the CRT screen (40 characters x 16 lines).
The first address of the line is “0”, the second line is “40”, the third
The line is specified as "80"..., but this can be changed to "+2" such as "2", "42", "82", etc.
By specifying the address by shifting increments, you can scroll by any number of characters.
Needless to say, the same applies to the opposite case, that is, to specifying by shifting by "-2". In this way, character-by-character shifting is possible because the address setting in the present invention is on a CRT.
This is because instead of directly specifying the line addresses 0, 1, 2, . . . on the screen, the memory address of the refresh memory 70 corresponding to the line address is specified. According to the present invention described above, it has become possible to freely change the screen from the outside. When changing the screen, it is possible to scroll not only line by line but also pixel by pixel.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional CRT display device, Figure 2 is a block diagram showing the main configuration of the timing control circuit, Figure 3 is an operation time chart of the main parts of the timing control circuit, and Figure 4A is the display. FIG. 4B is a diagram showing the address arrangement of the refresh memory, FIG. 5 is a block diagram of the CRT display device according to the present invention, and FIG. 6 is an implementation of the address setting device according to the present invention. Example diagram, Figure 7 is an operation time chart of the address setting device, Figure 8A is a diagram showing the setting value of the start address register, and Figure 8B is a diagram of the address generator based on the setting value of Figure 8A. 9A is a diagram showing the refresh memory of one screen. FIG. 9B is a diagram showing the display screen. FIG. 9C is a diagram showing the setting value of the start address register. Figure 10A is a diagram showing an example of combining and displaying display data for one screen from two pages of refresh memory, Figure 10B is a diagram showing the setting value of the start address register at that time, and Figure 11 Figure A shows an example in which one screen's worth of display data is synthesized and displayed from four pages of refresh memory, Figure 11B shows the setting value of the start address register at that time, and Figure 12 A is an example of scrolling and displaying only lines 8 to 15 of the display screen, Figure 12B is a diagram showing the setting value of the start address register at that time, and Figure 13A is an example of scrolling only lines 8 to 11 of the display screen. An example of scroll display, FIG. 13B shows the setting value of the start register at that time, and FIG. 14 shows the setting value of the start address register 430 in line-by-line scrolling.
Diagram showing an example of correspondence between CRT display screens, Part 1
FIG. 5 is a diagram showing an example of the correspondence between the set value of the start address register 430 and the CRT display screen in character-by-character scrolling. 40... Processor, 70... Refresh memory, 100... CRT display, 200... Timing control circuit, 400...
...address setting device.

Claims (1)

[Claims] 1 A CRT display, a refresh memory that stores data to be displayed on the CRT display in character address units, an address of the refresh memory, read timing, and the above-mentioned CRT.
The address setting section includes a timing control circuit that outputs various timings for display on a display, and an address setting section that generates a read address for the refresh memory, and the address setting section:
a start address register for setting a display start refresh memory address corresponding to the display line of the CRT display in character address units;
The contents of the register are preset at the start point of row scanning, and the character clock generated by the timing control circuit is counted up using that value as the start address, and the reading address of the refresh memory is determined by the sequentially obtained count values. and an address counter for use in
CRT display device.