JPS5454531A - Crt display unti - Google Patents

Crt display unti

Info

Publication number
JPS5454531A
JPS5454531A JP12095177A JP12095177A JPS5454531A JP S5454531 A JPS5454531 A JP S5454531A JP 12095177 A JP12095177 A JP 12095177A JP 12095177 A JP12095177 A JP 12095177A JP S5454531 A JPS5454531 A JP S5454531A
Authority
JP
Japan
Prior art keywords
address
unit
bus
display
crt display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12095177A
Other languages
Japanese (ja)
Other versions
JPS638488B2 (en
Inventor
Masahiro Iwamura
Fumiya Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12095177A priority Critical patent/JPS5454531A/en
Publication of JPS5454531A publication Critical patent/JPS5454531A/en
Publication of JPS638488B2 publication Critical patent/JPS638488B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To display the display data of memory on the screen with reassembling and to enable to control the change of screen freely from external, by providing the address set unit to which the readout address of refresh memory is set.
CONSTITUTION: The CRT display unit is provide with the address set unit 400, which is connected to the address bus 42 and the data bus 44 of processor, the output 265 of the line counter 260, character clock 225 and raster clock 236 are introduced from the timing control circuit 200. Further, the output 445 of the unit 400 is the readout address signal to read out the display data from the refresh memory 70. When write-in is made from the processor 40 to the start address register 430 constituted with RAM, the write-in address is designated from the address bus 42 and the content of the data bus 44 is written in the designated register
COPYRIGHT: (C)1979,JPO&Japio
JP12095177A 1977-10-11 1977-10-11 Crt display unti Granted JPS5454531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12095177A JPS5454531A (en) 1977-10-11 1977-10-11 Crt display unti

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12095177A JPS5454531A (en) 1977-10-11 1977-10-11 Crt display unti

Publications (2)

Publication Number Publication Date
JPS5454531A true JPS5454531A (en) 1979-04-28
JPS638488B2 JPS638488B2 (en) 1988-02-23

Family

ID=14799005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12095177A Granted JPS5454531A (en) 1977-10-11 1977-10-11 Crt display unti

Country Status (1)

Country Link
JP (1) JPS5454531A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57112780A (en) * 1980-12-29 1982-07-13 Fujitsu Ltd Divided screen display circuit in display device
JPS58121446A (en) * 1982-01-14 1983-07-19 Yokogawa Hokushin Electric Corp Graphic display equipped with refresh memory
JPS58125091A (en) * 1982-01-20 1983-07-25 富士通株式会社 Display unit
JPS58160983A (en) * 1982-03-18 1983-09-24 横河電機株式会社 Crt display unit
JPS59208586A (en) * 1983-04-25 1984-11-26 テキサス・インスツルメンツ・インコ−ポレイテツド Video image display unit
JPS6097391A (en) * 1983-09-30 1985-05-31 イング・チイ・オリベツチ・アンド・チイ・エス・ピー・ア Display for image prescribed by a plurality of data lines
JPS615282A (en) * 1984-06-19 1986-01-11 日本電信電話株式会社 Image display system
JPS61193193A (en) * 1984-06-29 1986-08-27 テキサス　インスツルメンツ　インコ−ポレイテツド Apparatus for displaying video image on display screen by line-wise and dot-wise frame sweep
JPS61212892A (en) * 1985-03-18 1986-09-20 株式会社日立国際電気 Control of character display unit
JPS62152575U (en) * 1986-03-20 1987-09-28
JPS62222289A (en) * 1985-05-15 1987-09-30 シャラン　ジェラール　オドニール Virtual memory image controller

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015953B2 (en) * 1980-12-29 1985-04-23 富士通株式会社 Split screen display circuit in display device
JPS57112780A (en) * 1980-12-29 1982-07-13 Fujitsu Ltd Divided screen display circuit in display device
JPS6349234B2 (en) * 1982-01-14 1988-10-04 Yokokawa Denki Kk
JPS58121446A (en) * 1982-01-14 1983-07-19 Yokogawa Hokushin Electric Corp Graphic display equipped with refresh memory
JPS58125091A (en) * 1982-01-20 1983-07-25 富士通株式会社 Display unit
JPS58160983A (en) * 1982-03-18 1983-09-24 横河電機株式会社 Crt display unit
JPH0313592B2 (en) * 1982-03-18 1991-02-22 Yokogawa Electric Corp
JPS59208586A (en) * 1983-04-25 1984-11-26 テキサス・インスツルメンツ・インコ−ポレイテツド Video image display unit
JPS6097391A (en) * 1983-09-30 1985-05-31 イング・チイ・オリベツチ・アンド・チイ・エス・ピー・ア Display for image prescribed by a plurality of data lines
JPH0570832B2 (en) * 1983-09-30 1993-10-05 Olivetti & Co Spa
JPS615282A (en) * 1984-06-19 1986-01-11 日本電信電話株式会社 Image display system
JPS61193193A (en) * 1984-06-29 1986-08-27 テキサス　インスツルメンツ　インコ−ポレイテツド Apparatus for displaying video image on display screen by line-wise and dot-wise frame sweep
JPS61212892A (en) * 1985-03-18 1986-09-20 株式会社日立国際電気 Control of character display unit
JPS62222289A (en) * 1985-05-15 1987-09-30 シャラン　ジェラール　オドニール Virtual memory image controller
JPS62152575U (en) * 1986-03-20 1987-09-28

Also Published As

Publication number Publication date
JPS638488B2 (en) 1988-02-23

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