JPS6381558A - Multi-cpu controlling system - Google Patents

Abstract

PURPOSE:To attain the flexible applications by providing a mode control register and changing the connection system of two microprocessors programmably so as to effectively utilize the performance of the processors. CONSTITUTION:The mode control register 4 is constituted to be accessed from both the processors 1, 6 and when the operating system is operated on the processor of a CPU 1, a CPU 2 acts like a sub-processor, a local memory 8 is used to control a screen control section 9, and the information of the CPU1(1) and CPU2(6) is converted by a common memory 3. The mode control register 4 is accessed by the program of the CPU1 to change the mode, then a driver/ receiver 5 is made ineffective, a driver/receiver 11 is made effective, a bus 7 of the CPU2 is connected to the system 12 and the CPU2(6) accesses a main memory 13 and an input/output device 14. In this mode, the CPU1(1) is inoperative and the control of the entire system is executed by the CPU2(6).

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is a multi-CPU control method (prior art) that can effectively utilize the performance of a microprocessor. There are several ways to improve system performance by using more microprocessors. In most of them, one operates as a main processor, and the other functions as a sub-processor, for example, as a dedicated processor for screen control.

Let's take a concrete example of a graphic system.

When displaying graphic data in such a system, it is necessary to develop the dot pattern data in memory and transfer it to a terminal. Therefore, a distributed function architecture is adopted in which the main processor and the graphics processor are made independent, and a common memory that receives and transfers graphics commands mediates between the two.

(Problems to be Solved by the Invention) Despite the fact that the performance of microprocessors has improved significantly in recent years with advances in semiconductor technology, in the above function distributed system, apart from the main processor, It is difficult to say that the performance of the sub-processor is fully utilized, and it is not possible to use it flexibly.

The present invention has been made in view of the above circumstances, and is a multi-CPU control method that realizes flexible usage while effectively utilizing the performance of processors.

The purpose is to provide

[Structure of the Invention (Means for Solving Problems)] The present invention changes the connection method of two microprocessors to a programmable one, effectively utilizes the performance of the microprocessors, and facilitates the expansion of system functions. It is something that will be realized.

For this reason, conventionally, a mode control register was added to the components of this type of system, which is accessed by a microprocessor connected to the system, and its operating mode is set. By connecting the system bus via the /receiver, one of the drivers/receivers is enabled according to the contents set in the mode control register, and one of the microprocessors functions as the main. be.

(Function) Even in the above configuration, the mode control register is in the mode of one of the microprocessors in the initial state, and therefore enables the driver/receiver connected to the bus of that microprocessor, and enables the system. Main memory and input/output devices connected to the bus can be accessed. At this time, the other CPU operates as a subprocessor and uses its own local memory to perform screen control, for example. On the other hand, when the microprocessor accesses the mode control register and changes the mode, the other driver/receiver is enabled and
The microprocessor, which previously functioned as a subprocessor, is connected to the system bus and can access the main memory and turntable device connected to this bus.

Note that the mode control register can also be accessed by all microprocessors connected to the system, and both modes can be switched programmably.

According to the method of the present invention, if different microprocessors are connected to the system, a plurality of operating systems can be operated in one system.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. For reference, a conventional example is also shown in FIG. 2, and blocks with the same numbers are the same as those in FIG. 1. In the figure, 1 is the bus processor (CPU1), 2.7 is its bus,
A common memory 3 serves as a mailbox for the processor 1 and the processor (CPU 2) 6. Reference numeral 4 denotes a mode control register added according to the present invention, which is configured to be accessible from both processors 1 and 6.

5 is CPU bus 2 driver/receiver (D/R)
It is. 6 is the other processor (CPU2), 7
is its bus, and 8 is a local memory for the CPU2.

9 and 10 are a screen control unit and a display device (CRT), respectively. Reference numeral 11 denotes a driver/receiver (D/R) of the bus 7 that the CPU 2 has.

12 is the system bus, main memory 13 output device■
4 is connected.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail in comparison with the conventional example.

Conventionally, as shown in FIG. 2, the CPUI operates as a main processor and operates on the CPUI of an operating system (O8) box. In order to reduce the load on the CPU, a dedicated subprocessor CPU2 is used for screen control, etc.
(6), and the information during that time was stored in the common memory 5. In recent years, the performance of microprocessors has improved significantly due to advances in semiconductor technology, but as mentioned above, in the conventional system, the subprocessor 6 was only engaged in dedicated processing and processing such as screen control, and its performance was not fully utilized. That's right.

FIG. 1 shows an embodiment of the present invention in which the mode control register 4 is in the CPUI mode in the initial state. In this mode, the driver/receiver 5 is enabled and the CPU bus 2 is connected to the system bus 12. The CPU can access 13 main memory outputs 14.

That is, σS operates on the processor of the CPUI. At this time, the CPU 2 operates as a sub-processor and controls the screen control section 9 using the local memory 8.

The information of CPUI (1) and CPU2 (6) is converted by common memory 3. When the program on the CPUI accesses the mode control register 4 and changes the mode, the driver/receiver 5 becomes invalid. Instead, the driver/receiver 11 is enabled, the bus 7 of the CPU 2 is connected to the system bus 12, and the CPU 2
(6) The main memory 13 can now access the output device 14. In this mode, the CPU (1) is not operated and all system control is performed by the CPU (6). The mode control register 4 can also be accessed by the CPU 2 (6), and both modes can be switched programmably.

By the way, according to the method of the present invention, if the CPUI and the CPU2 are configured with different types of microprocessors, it is also possible to operate two C)S in the l system.

[Effect of the invention] According to the method of the present invention as explained above, regarding mode 1,
By setting the function distribution mode in which CPU1 operates as the main processor and CPU2 as a sub-processor, and on the other hand, in mode 2, by setting the mode in which only CPU2 operates as the main processor, if the CPUI and CPU are configured with different types of microprocessors, If
Two different σS can be operated in one system. By distributing functions in this way and switching modes while aiming to improve system performance, flexible usage such as operating two O8s becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1.6...processor (CPU), 2.7...C
PU bus, 3... Common memory, 4... Mote control register, 8... Local memory, 5, 11... Driver/receiver, 12... System bus. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] A microprocessor, each with an independent bus,
a common memory that is connected between the buses and stores communication information when converting information between the microprocessors; a mode control register that is accessed by both of the microprocessors and sets their operating modes; Each bus is connected via a driver/receiver, and consists of a system bus to which main memory and input/output devices are commonly connected, and one of the drivers/receivers is activated according to the contents set in the mode control register above. A multi-CPU control method characterized by enabling a microprocessor connected to a system bus to function.