JPH0784963A - Semiconductor integrated circuit with cpu - Google Patents

Abstract

PURPOSE:To improve the efficiency of the data arithmetic processing of multiple CPUs by performing an interruption request processing from a peripheral module at a high speed. CONSTITUTION:Peripheral modules 11, 12, and 13 are connected to an I/O system data bus 201, an interruption control circuit 17 is connected to an I/O system processor 101 and the peripheral modules, and an interruption control circuit 17 transfers interruption requests from the peripheral modules to the I/O system processor 101. The peripheral modules need to perform data transfer through an I/O system data bus 102 and selecting circuits 18 and 19 when sending or receiving data to or from outside the chip. The data transfer between the peripheral modules and the outside of the chip through the I/O system data bus 102 is performed under the control of the I/O system processor 101, so an interruption request for this data transfer is not sent to an arithmetic system processor 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a CPU (central processing unit), and more particularly to improving the processing efficiency of data arithmetic processing of a single chip microcomputer having two CPUs mounted on the same chip. for,
CPU and I on the same chip for data processing
CPU for I / O processing (peripheral module processing)
And a single-chip microcomputer provided with.

[0002]

2. Description of the Related Art As a conventional example of a single chip microcomputer, there is a Hitachi single chip microcomputer HD6475328. This HD6475328
Then, in addition to the CPU and the memory, peripheral modules such as a timer and a serial communication interface are connected to one data bus. The CPU reads an instruction from the memory, executes data input, calculation, and result storage according to the read instruction. In addition, the CPU receives an interrupt request from the peripheral module and performs an interrupt request process for the peripheral module that has generated the interrupt. On the other hand, in JP-A-62-152064, a plurality of CPUs independently have an internal address data bus and a built-in memory, and these internal address data buses are connected to an external address data bus via a common bus control device. There is disclosed a single-chip microcomputer which has an improved processing capability by being connected to the. On the other hand, as is well known, a computer system has an interrupt function as a means for realizing flexibility of operation. In particular, external interrupts are interrupts that occur independently of program execution, such as power supply abnormalities, timer interrupts, input / output interrupts,
External signals are specific factors. When such an interrupt factor is detected and an interrupt occurs, the execution of the program is interrupted, the program status word or program status vector that defines the execution status of the program is saved in a certain area, and the interrupt processing routine is executed. Control is transferred.

[0003]

In a conventional single-chip microcomputer having only one CPU, in addition to the data arithmetic processing that the CPU should originally perform, interrupt request processing from peripheral modules must be performed. The efficiency of data calculation processing was reduced. That is,
No consideration has been given to improving the efficiency of the data calculation processing of the CPU. Also in the conventional single-chip microcomputer having a plurality of CPUs disclosed in Japanese Patent Laid-Open No. 62-152064, how the plurality of CPUs execute the interrupt request processing may reduce the efficiency of the data calculation processing. It does not disclose whether it can be avoided.

Therefore, it is an object of the invention to execute an interrupt request process from a peripheral module at high speed in a single-chip microcomputer having a plurality of CPUs and to improve the efficiency of the CPU's data operation process. is there.

[0005]

In order to achieve the above object, a semiconductor integrated circuit according to a typical embodiment disclosed in the present application includes a first and a second processor (10) for outputting an address.
0, 101) and a first address bus (202) and a first data bus (200) connected to the first processor (100).
A second address bus (204) and a second data bus (201) connected to the second processor (101), the first and second address buses and the first second bus. A built-in memory (10) connected to the data bus, a selected one of the first and second address buses and a selected one of the first and second data buses are connected to an external address bus (22). )
And a selection circuit (18, 19) connected to the external data bus (21), and the second data bus (201) includes a timer (11), an A / D converter and a D / D converter. A peripheral module which is at least one of the A converter (12) and the serial input / output interface (13) is connected to the second processor.
Interrupt control circuit (17) between (101) and the above peripheral modules
Is connected, and the interrupt control circuit (17) sends an interrupt request (250) from the peripheral module to the second processor (10).
It is characterized in that it is transferred to 1) (see FIG. 1).

In the semiconductor integrated circuit according to a preferred embodiment of the present invention, the interrupt control circuit (17) is further connected to the first processor (100), and the second processor (101).
The interrupt control circuit (17) generates an interrupt request from the second processor (101) generated at the end of transfer of external data to the built-in memory (10) by the first processor.
It is characterized in that it is transferred to (100) (see FIG. 1).

A semiconductor integrated circuit according to another preferred embodiment of the present invention further comprises a designation means (53) for designating one of the first and second processors.
In the plurality of accesses from the processor (100) and the plurality of accesses from the second processor (101), the selection circuit (18, 19) is designated to the plurality of accesses from the designated one. One of them is continuously executed exclusively by connecting the other one to the external address bus (see FIGS. 21 and 23).

In a semiconductor integrated circuit according to a more preferred embodiment of the present invention, the built-in memory has a plurality of banks (115, 116, 1).
A storage means (119) for storing information for controlling access to the plurality of banks is connected to the second data bus (201) and includes the first address bus.
The access to the plurality of banks from the first processor (100) via the (202) is made to the first address bus (20
A second address decoder (113) connected to the first address bus (202) for controlling in response to the upper bits of 2) and the information of the storage means (119), and the second processor The interrupt control circuit sends an interrupt request from the second processor (101) generated each time data transfer to at least one of the plurality of banks (115, 116, 117, 118) of external data accessed by (101) is completed. (17)
Is transferred to the first processor (100) and the second processor (100) is transferred.
The second processor each time data transfer to the at least one bank of the plurality of banks (115, 116, 117, 118) of external data accessed by the processor (101) is completed.
(101) updates the information in the storage means (119) via the second data bus (201), and the first processor (100) responds to each interrupt request at the end of the data transfer. The same access address is sent to the first address bus (202) (see FIG. 15).

In a semiconductor integrated circuit according to a more specific embodiment of the present invention, the first data bus (200) has at least one of a multiplier / divider (14), a function calculator (15), and a floating point processor. It is characterized by being connected with the auxiliary calculation module (see FIG. 1).

[0010]

In the semiconductor integrated circuit of the typical embodiment disclosed in the present application (see FIG. 1), in particular, the second data bus (201)
Includes a timer (11), an A / D converter and a D / A converter (1
2), a peripheral module which is at least one of the serial input / output interface (13) is connected, and an interrupt control circuit is provided between the second processor (101) and this peripheral module.
(17) is connected, and since this interrupt control circuit (17) transfers an interrupt request from the peripheral module to the second processor (101), the following operation is possible. That is, the timer (11), the A / D converter and the D / A converter
Peripheral modules such as (12) and serial input / output interface (13) transfer data via the second data bus (102) and selection circuits (18, 19) when transmitting or receiving data to or from the outside of the chip. Need to do. Since the data transfer between the outside of the chip and the peripheral module via the second data bus (102) is performed under the control of the second processor (101), the interrupt request for this data transfer requires the first interrupt. It is not transmitted to the processor (100). Therefore, during this period, the first processor (100) is connected to the first address bus (20
Built-in memory (10) via 2) and the first data bus (200)
Can be accessed, and processing of logical operations can be performed on this access data. The specific contents are as follows. That is, the timer (11) compares the data set in the timer constant register with the data updated in synchronization with the clock, and if they match, sets a flag in the timer control / status register. Also, the timer (11)
The setting of the data in the timer constant register is performed by the second processor (101) from the outside of the chip via the selection circuit (18, 19) and the second data bus (201). Since the processor (100) does not receive the interrupt for setting the data in the timer constant register,
The processor (100) can access the internal memory (10) through the first address bus (202) and the first data bus (200), and can perform logical operation processing on the access data. . Further, the first processor (100) is based on the interrupt at the end of the counting operation by the timer (11).
In order to enable access to the data in the internal memory (10) by the
It is desirable that the interrupt from (11) at the end of the counting operation is transmitted to the first processor (100) as an internal request interrupt signal (250) via the interrupt control circuit (17). Further, the serial input / output interface (13) transmits / receives internal data and serial port data by performing parallel-serial conversion or serial-parallel conversion of data in the shift register unit, and when transmitting / receiving data from outside the chip. The serial data is converted to parallel data, and the parallel data is converted to serial data when the data is transmitted to the outside of the chip. In addition, during serial-parallel conversion during reception and parallel-serial conversion during transmission, data transfer between the digital port (DP) for connection to the outside of the chip and the second data bus (201) is the second. This is performed by the management of the processor (101), but during this time, since the interrupt for this data transfer is not transmitted to the first processor (100), the first processor (100) operates as a first address bus (202) The internal memory (10) can be accessed via the first data bus (200),
Logical processing can be performed on this access data. In addition, based on the interrupt of the completion of the serial-parallel conversion at the time of reception by the serial input / output interface (13), the second processor (101) of the conversion data stores the internal memory (1
Conversion operation from the serial I / O interface (13) to enable storage in the (0) and access of data in the internal memory (10) by the first processor (100), and further logical operation of access data It is desirable to transmit the interrupt at the end to the first processor (100) and the second processor (101) via the interrupt control circuit (17) as the internal request interrupt signal (250). Also, an A / D converter and a D
The A / A converter (12) performs analog-digital conversion (A / D conversion) or digital-analog conversion (D / A conversion) between internal data and an analog port to perform transmission / reception. When analog signals are received from the chip, analog data are converted to digital data (A / D conversion), and when analog signals are sent to the outside of the chip, digital data are converted to analog data (D / A conversion). In addition, A / D conversion and D during reception and transmission
During the A / A conversion, data transfer between the analog port (AP) for connection with the outside of the chip and the second data bus (201) is performed by the management of the second processor (101). Since the interrupt for this data transfer is not transmitted to the first processor (100),
(100) is the first address bus (202) and the first data bus (2
00) and the built-in memory (10) can be accessed, and this access data can be processed by a logical operation.
Further, the conversion data is stored in the internal memory (10) by the second processor (101) based on the interruption of the completion of the A / D conversion at the time of reception by the A / D converter and the D / A converter (12). In order to enable access to the data in the internal memory (10) by the first processor (100) and further the logical operation of the access data, the A / D converter and the D / A converter (12) It is desirable that the interrupt at the end of the conversion operation is transmitted to the first processor (100) and the second processor (101) via the interrupt control circuit (17) as the internal request interrupt signal (250).

In the semiconductor integrated circuit of the preferred embodiment of the present invention, the interrupt control circuit (17) further includes a first processor (1
00) to generate an interrupt request from the second processor (101) when the second processor (101) finishes transferring external data to the internal memory (10).
7) is to be transferred to the first processor (100), the first processor (100) of the transfer data in the internal memory (10)
It is possible to quickly start access and logical operation by.

In a semiconductor integrated circuit according to another preferred embodiment of the present invention, the designation means (53) is used for a plurality of accesses from the first processor (100) and a plurality of accesses from the second processor (101). The first and the second specified by
Multiple access from one of the processors in the selection circuit (1
(8, 19) is an exclusive and continuous execution. Therefore, the second processor (1
When 01) is specified, the second processor (1) that handles data transfer between the peripheral modules (11, 12, 13) and the outside of the chip
The exclusive continuous use right of the external address bus (22) and the external data bus (21) is given to 01). In this case, the first processor (10
The functions of peripheral modules (11, 12, 13) are more important than 0). In the opposite case, the function of the first processor (100) that mainly processes the data logic operation inside the chip is more important than the peripheral modules (11, 12, 13). In any case, an access mode suitable for the orientation of various users can be designated by the designating means (53).

In a semiconductor integrated circuit of a more preferred embodiment of the present invention (see FIG. 15), the built-in memory has a plurality of banks (11
5,116,117,118), and storage means (119) for storing information for controlling access to a plurality of banks is connected to the second data bus (201) and is connected to the first address bus (202). A first address decoder (113) controls the access from the one processor (100) to the plurality of banks in response to the upper bits of the first address bus (202) and the information of the storage means (119). One of the plurality of banks (115, 116, 117, 118) of external data, which is connected to the first address bus (202) and is accessed by the second processor (101), completes the second transfer every time data transfer to at least one bank is completed. The processor (101) updates the information in the storage means (119) via the second data bus (201), and the external data accessed by the second processor (101) is stored in a plurality of banks (115, 116, 11).
The interrupt control circuit (17) causes the first processor (100) to transfer an interrupt request from the second processor (101) generated at the end of data transfer to at least one bank (7, 118). The first processor (100) sends the same access address to the first address bus (202) in response to each interrupt request at the end of data transfer. Therefore, in response to each interrupt request from the second processor (101) generated at the end of data transfer to one bank, the first processor (100) sends the same access address to the first address. Despite sending to the bus (202)
The same access address is converted each time by the update information of the storage means (119). Since this conversion address designates a plurality of banks (115, 116, 117, 118) one after another, data of a plurality of banks (115, 116, 117, 118) can be successively accessed by the same access address from the first processor (100). Therefore, a plurality of banks in the address space of the first processor (100) (11
5,116,117,118) can be reduced in address area, and other address areas are allocated to a storage means such as a private memory and a register for the first processor (100) mainly processing the data logic operation in the chip. be able to.

In a more specific embodiment of the present invention, a semiconductor integrated circuit (see FIG. 1) has a first data bus (200) having a multiplier / divider (14), a function calculator (15), and a floating point calculator. Since the auxiliary arithmetic module, which is at least one of the processors, is connected, the arithmetic function of the first processor (100) mainly processing the data logic operation in the chip can be assisted by this auxiliary arithmetic module. Other objects and features of the present invention will be apparent from the following examples.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the embodiment of the present invention, basically, 1
2 which can execute most of the instructions in the chip
Two sets of internal buses 202, 200, each of which has one processor 100, 101 and is connected to each processor;
By including 204 and 201, the processor 100 for data arithmetic processing and the processor 1 for peripheral module processing
It can be divided into 01 and. Further, the processor 10
1 and the peripheral modules 11, 12, and 13 are connected to the interrupt control circuit 17, and the interrupt control circuit 17 transfers the interrupt request 250 from the peripheral modules 11, 12, and 13 to the processor 101 for processing the peripheral module. Since there is no interrupt request from the peripheral modules 11, 12, 13 to the processor 100 for data arithmetic processing, the efficiency of data arithmetic processing of the processor 100 can be improved. Furthermore, two sets of internal buses 20
2, 200; 204, 201 are connected to the selection circuits 18 and 19, and the external address bus 2 outside the chip is connected to the external port.
2 and the external data bus 21 can be connected, a single-chip microcomputer can be realized with a small area.

FIG. 1 shows a block configuration within one chip of a multi-CPU single-chip microcomputer. The arithmetic system internal data bus 200 and the arithmetic system address bus 202 in the chip are connected to the arithmetic system CPU 100, the multiplier / divider 14, and the functional arithmetic unit 15 such as a trigonometric function useful in voice / image processing and the like. An auxiliary arithmetic module such as a decimal point arithmetic processor can be connected. The CPU 100 only includes a logical operation unit (ALU) that performs processing such as addition, subtraction and inversion, and a barrel shifter that performs shift processing such as bit shift, and the data operation of the CPU 100 relating to multiplication / division, function operation, floating point operation, etc. The processing function is not sufficient. The auxiliary arithmetic modules 14 and 15 assist these data arithmetic processing functions. The function calculator 15 is, for example, a participation function sinX = Y.
Of inputs X ₀ , X ₁ ... X _n and its outputs Y ₀ , Y ₁
, Y _n and a look-up table that stores Y _n, and the look-up table may include a plurality of inputs X.
It is desirable that the associative memory that outputs the output data when ₀ , X ₁ ... X _n are used as the storage key and the search key and the storage key and the search key match. On the other hand, the I / O system internal data bus 201 and the I / O system address bus 204 include an I / O system CPU 101, a timer 11, an A / D and D / A converter 12, and a serial input / output interface 1.
Peripheral modules such as 3 are connected. The function and operation of this peripheral module are as described above. Although not shown, the I / O system internal data bus 20
1. The I / O system address bus 204 has a DMA built in a conventional single-chip microcomputer.
(Direct memory access) It is desirable to connect a built-in peripheral circuit such as a controller. The internal memory 10, the internal / external bus control circuit 16, and the interrupt control circuit 17 are used for the operation system buses 200 and 202 and the I / O system internal data bus 2.
01 and I / O system address bus 204. Further, the built-in memory 10 has a function as a shared memory (shared memory) accessed by the arithmetic CPU 100 and the I / O CPU 101, and the arithmetic CPU 100.
And a function as a private memory (private memory) accessed from either the I / O system CPU 101 or the I / O system CPU 101. The built-in memory 10 is a static RAM,
Mask ROM, non-volatile memory (EPROM, EEPR
OM etc.) and the like. Operation system CP
The U100 and the I / O system CPU 101 are CPUs that operate with almost the same instruction code of the instruction set of the single-chip microcomputer. Arithmetic CPU 100
Mainly performs data operation processing such as voice image processing, and I /
The O-system CPU 101 mainly performs data input / output processing between an external device and this single-chip microcomputer. A general logic LSI such as a single-chip microcomputer has a limitation on the number of external pins. Therefore, the address and data internal buses 202, 200; 20 separated into the operation system and the I / O system inside the chip
4, 204 also need to be multiplexed in the interface (external pin) portion with the outside of the chip. Therefore, the arithmetic data bus 200 and the I / O data bus 20
1 is input to the multiplexer 18 as a selection circuit, and the external data bus 2 is input via this multiplexer 18.
Connected to 1. Similarly, the arithmetic address bus 202 and the I / O address bus 204 are input to the multiplexer 19 and connected to the external address bus 22 via the multiplexer 19. Data is exchanged with a device external to the chip by using the external data bus 21, the external address bus 22, and the WAIT control signal 23 for controlling the extension of the bus cycle period. Therefore, the arithmetic CPU 100 and the I / O CPU 101 are connected to the internal bus 2
02,200; 204,204 and multiplexer 18,
An external device such as an external memory can be accessed via the 19, the external data bus 21, and the external address bus 22. The internal / external bus control circuit 16 is an arithmetic system C
According to the address information 202 and 204 output from the PU 100 or the I / O system CPU 101, the internal memory 10 in the chip and the peripheral module 1 that are address-mapped
It controls the data transfer cycle between the registers 1, 12, 13 and various registers of the auxiliary arithmetic modules 14, 15 and external devices outside the chip. When data is transferred to an external device, the control signal 20 specifies which internal bus of the operation system or the I / O system is connected to the external device. At the end of the bus cycle, the control signal 24 is sent to the arithmetic CPU 100 and the I / O C
The PU 101 is informed by the control signal 25 that the bus cycle is completed, and is instructed to make the next data transfer request. The interrupt control circuit 17 includes a timer 11,
An internal interrupt request signal 250 output from a built-in peripheral module such as the A / D and D / A converter 12 and the serial input / output interface 13, and an external interrupt request signal 249 input from outside the chip are input. Based on these interrupt requests, the interrupt to the arithmetic system CPU 100 is the interrupt request signal 245, and the I / O system CPU 101
Is an interrupt request signal 247 and activates interrupt processing. The external interrupt request signal 249 is an interrupt due to a power failure or the like, and the timer 11, A / D and D /
The internal interrupt request signal 250 output from the built-in peripheral modules such as the A converter 12 and the serial input / output interface 13 has been described in detail before the embodiment. The vector number for designating the program address to be executed after the interrupt processing is a dedicated bus between the interrupt control circuit 17 and the two CPUs 100 and 101.
A method of designating via (indicated by a broken line in FIG. 1) and a method of designating via two internal data buses 200 and 201 as shown in FIG. 1 can be adopted. As described above, in the multi-CPU single-chip microcomputer of this embodiment, the internal / external bus control circuit 16, the interrupt control circuit 17, and the built-in memory 10 are shared by the arithmetic CPU 100 and the I / O CPU 101, and two single CPUs are shared. The chip microcomputer is configured as one chip.
Therefore, if the operation of the shared portion is not considered, the respective CPUs 100 and 101 perform the same operation as that of the conventional single chip microcomputer.

As a concrete example of realizing the built-in memory 10 shown in FIG. 1, FIG. 2 shows a memory allocation configuration in a shared memory unit of a multi-CPU. FIG. 2 is a block diagram for preventing a decrease in data calculation processing efficiency of the calculation system CPU 100.
FIG. 3 is a diagram showing a configuration in which allocation of shared memory to arithmetic CPU 100 and I / O CPU 101 is variable.

FIG. 2 shows an arithmetic CPU 100, an address decoder 102, a memory allocation register 108, a selection circuit 107, a shared memory A104, a shared memory B1.
05, I / O system CPU 101, address decoder 103
It is composed of The memory allocation register 108
The value written from the I / O system CPU 101 is output to the two address decoders 102 and 103 and the selection circuit 107. The address decoders 102 and 103 select the memory according to the value of the memory allocation register 108 CS4
Signal 211, CS5 signal 212, CS6 signal 213, C
Control the S7 signal 214. The selection circuit 107 selects the shared memory A1 according to the value of the memory allocation register 108.
04 and the shared memory B105 as the arithmetic CPU 10
It controls the SL0 signal 215 and the SL1 signal 216 that determine which of 0 and the I / O system CPU 101 is logically connected. The arithmetic system internal data bus 200 is connected to the shared memory A 104 and the shared memory B 105. The operation system address bus 202 is connected to the shared memory A 104 through the operation system lower address 220. The operation system address bus 202 is connected to the shared memory B105 through the operation system lower address 221. The upper address of the arithmetic address bus 202 is
Address decoder 1 through arithmetic system upper address 203
02 is connected. I / O system internal data bus 201
Is shared memory A104 and shared memory B1
05 is connected. I / O system address bus 204
Are connected to the shared memory A 104 through the I / O system lower address 222. I / O system address bus 2
04 is connected to the shared memory B105 through the I / O system lower address 223. Further, the upper address of the I / O system address bus 204 is connected to the address decoder 103 through the I / O system upper address 205. The memory allocation register 108 is connected to the I / O system internal data bus 201 through a signal line 206.
The memory allocation register 108 includes signal lines 209 and 210.
Through address decoder 102 and selection circuit 107
It is connected to the. The memory allocation register 108 is connected to the address decoder 103 via signal lines 207 and 208. The CS4 signal 211 and the CS5 signal 212 output from the address decoder 102 are shared memory A104 and shared memory B10, respectively.
Connected to 5. The CS6 signal 213 and the CS7 signal 214 output from the address decoder 103 are the shared memory A 104 and the shared memory B, respectively.
It is connected to 105. The SL0 signal 215 and the SL1 signal 216 output from the selection circuit 107 are connected to the shared memory A104 and the shared memory B105, respectively.

A memory map of the arithmetic system CPU 100 is shown in FIG.
Shown in. From this figure 3, from H'00000000 to H '
External memory space in 7FFFFFFF, H'80000
000 to H'9FFFFFFF, internal memory space,
It can be seen that the memory allocation spaces 0 and 1 are provided in H'A00000000 to H'BFFFFFF, respectively, and no other memory is provided. I / O system C
The memory map of PU101 is shown in FIG. From FIG. 4, the external memory space is set from H'00000000 to H'7FFFFFFF, and from H'80000000 to H'9F.
FFFFFF with internal memory space, H'A000000
0 to H'BFFFFFFF memory allocation space 0, 1
From H'C0000000 to H'FFFFFFFF, it is understood that the internal memory spaces are provided.
In addition, according to the value set in the memory allocation register 108 of FIG.
Shared memory A104 in memory allocation space 0, 1
And the shared memory B105 is allocated.

The structure of the memory allocation register 108 is shown in FIG.
Shown in. As shown in FIG. 2, the memory allocation register 10
8 is a signal line 206 and an I / O system internal data bus 20.
1 can be read and written by the I / O CPU 101. The memory allocation register 108 is composed of 2 bits of MD1 and MD0. Memory allocation register 1
FIG. 6 shows a memory map of the arithmetic CPU 100 and the I / O CPU 101 when the 2-bit MD1 and MD0 values of 08 are set. From FIG. 6, in the mode 00, the arithmetic CPU
All the memory is allocated to the 100 side, the memory is allocated to each of the arithmetic CPU 100 and the I / O CPU 101 in the mode 01, and the arithmetic CPU 100 in the mode 10.
It can be seen that no memory is allocated on the side. Mode 1
1 is not defined.

A block diagram of the address decoder 102 on the arithmetic system CPU 100 side is shown in FIG. From this figure, A31, A30, A29, A of the arithmetic system upper address 203
28, MD1 and MD0 control the CS4 signal 211 and the CS5 signal 212. CS4 signal 21
1 and CS5 signal 212 are shared memory A1 respectively.
04, a signal line for selecting the shared memory B105.

The function of the address decoder 102 shown in FIG. 7 is shown in FIG.

When A31 = 0, the external space is designated, so that 0 is output to the CS4 signal 211 and the CS5 signal 212 to select no memory. (A31, A30) =
(1, 1) is from H'C0000000 to H'FFFF
Specify the FFFF space (A31, A30, A29)
When = (1, 0, 0), since the internal memory space is designated, 0 is output to the CS4 signal 211 and the CS5 signal 212. (A31, A30, A29, A28) = (1,
In the case of 0, 1, 0), the memory allocation space 0 is designated.
At this time, the CS4 signal 21 depends on the values of MD1 and MD0.
1, the value of the CS5 signal 212 is determined. (MD1, M
When D0) = (0,0) and (0,1), the shared memory A104 is allocated to the memory allocation space 0. Therefore, the CS4 signal 211 for selecting the shared memory A104 is 1,
0 is output to the CS5 signal 212 for selecting the shared memory B105. When (MD1, MD0) = (1,0), no memory is allocated to the memory allocation space 0.
The CS4 signal 211 and the CS5 signal 212 both output 0. When (MD1, MD0) = (1, 1), the mode is not defined, so CS4 signal 211, CS5 signal 2
Both 12 are don't care (*). (A3
When 1, A30, A29, A28) = (1, 0, 1, 1), the memory allocation space 1 is designated. At this time, MD
The values of CS4 signal 211 and CS5 signal 212 are determined by the values of 1 and MD0. (MD1, MD0) = (0,
0), the shared memory B1 is allocated to the memory allocation space 1.
Since 05 is allocated, 0 is output to the CS4 signal 211 that selects the shared memory A104, and 1 is output to the CS5 signal 212 that selects the shared memory B105. (MD1, M
When D0) = (0,1) and (1,0), since the memory is not allocated to the memory allocation space 1, the CS4 signal 21
Both 1 and CS5 signal 212 output 0. (MD1,
When MD0) = (1,1), the mode is not defined, so both CS4 signal 211 and CS5 signal 212 are set to *.

FIG. 9 is a block diagram of the address decoder 103 on the I / O system CPU 101 side of FIG. From this figure, A31 and A3 of the I / O system upper address 205
0, A29, A28 and MD1, MD0, CS6 signal 2
13 and the CS7 signal 214 is controlled.

The function of the address decoder 103 shown in FIG. 9 is shown in FIG. The concept of the function table of FIG. 10 is as shown in FIG.
Since the concept of the function table is basically the same, detailed description is omitted. The difference from FIG. 8 is that when the mode is specified, the method of allocating memory to the memory allocation space is the operation system CP.
Since U100 and I / O CPU 101 are the opposite, C
The output values of the S6 signal 213 and the CS7 signal 214 are CS4
It is different from the values of the signal 211 and the CS5 signal 212.

FIG. 11 shows a block diagram of the selection circuit 107. From this figure, SL1 signal 215 for MD1 and MD0,
It can be seen that the SL1 signal 216 is controlled.

The function of the selection circuit 107 is shown in FIG.
In the function table, SL signals are operation system and I / O system CS signals input to the shared memory, lower address and internal data bus selection signals, and when the signal is 1, the operation system CS signals, The lower address and the internal data bus are selected, and when the signal is 0, the I / O type is selected.
When (MD1, MD0) = (0, 0), the shared memory A104 and the shared memory B105 are set to the operation system CP.
Since it is connected to U100, both SL0 signal 215 and SL1 signal 216 output 1. (MD1, MD0) =
In the case of (0, 1), since only the shared memory A104 is connected to the arithmetic system CPU 100, 1 is output to the SL0 signal 215 and 0 is output to the SL1 signal 216. (MD1, MD
When 0) = (1,0), no memory is connected to the arithmetic CPU 100, so that the SL0 signal 215 and the SL1 signal 2
Both 16 output 0. (MD1, MD0) = (1,
In the case of 1), the mode is not supported, so both SL0 signal 215 and SL1 signal 216 are set to *.

FIG. 13 shows a block diagram of the shared memory A104 of FIG. The shared memory A104 includes a memory 109 and selection circuits 110, 111 and 112. The selection circuit 110 selects the operation system lower address 220 and the I / O system lower address bus 222 according to the value of the SL0 signal 215, and outputs it to the signal line 217. The selection circuit 111 uses the value of the SL0 signal 215 to determine the operation system internal data bus 200 and the I / O system internal data bus 201.
Is selected and output to the signal line 218. Selection circuit 11
2 depends on the value of the SL0 signal 215 and the CS4 signal 21
1 and the CS6 signal 213 are selected and output to the signal line 219. The selection circuits 110, 111 and 112 are SL
When the 0 signal is 1, the CS4 signal 211, the operation system lower address 220 and the operation system internal data bus 200 are selected,
CS6 signal 213, I / O when SL0 signal 215 is 0
System lower address 222 and I / O system internal data bus 2
This is a circuit for selecting 01. The shared memory B105 also has the same configuration as that of FIG. The operation will be described below.
Now, consider the case where mode 00 is designated and both shared memory A 104 and shared memory B 105 are connected to the arithmetic CPU 100 side. At this time, 00 is set in the memory allocation register 108. First, CPU 100
Will access the memory allocation space 0. At this time (A31, A30, A29, A28) =
It becomes (1, 0, 1, 0). Memory allocation register 10
Since 8 is (MD1, MD0) = (0, 0), 1 is output only to the CS4 signal 211 that selects the shared memory A104 from the function table of FIG. Further, since the selection circuit 107 has (MD1, MD0) = (0, 0), from the function table of FIG.
Shared memory A104 and shared memory B1 on the side
SL0 signal 215, SL1 signal 2 to connect 05
1 is output to 16. Shared memory A104 is S
Since the L0 signal 215 is 1, the arithmetic CPU 1
CS4 signal 211 from 00, operation system lower address 22
0, connected to the operation system internal data bus 200. Therefore, it becomes possible to access the shared memory A 104 from the arithmetic CPU 100. The shared memory B105 is also connected to the arithmetic system CPU 100 side, but the CS5 signal 212 is 0.
Therefore, it is not accessed from the arithmetic CPU 100.
Next, consider a case where the arithmetic CPU 100 accesses the memory allocation space 1. From the function table of FIG. 8 (A31, A
30, A29, A28) = (1, 0, 1, 1), (MD
Since 1, MD0) = (0,0), only 1 is output as the CS5 signal 212. From the selection circuit 107, the operation system CP
The SL0 signal 215, so that the shared memory A104 and the shared memory B105 are connected to the U100 side,
1 is output for both SL1 signals 216. Since the SL1 signal 216 is 1, the shared memory B105 is connected to the CS5 signal 212 from the arithmetic CPU 100, the arithmetic lower address 222, and the arithmetic internal data bus 200. Therefore, it becomes possible to access the shared memory B105 from the arithmetic CPU 100. The shared memory A104 is also connected to the arithmetic CPU 100 side, but C
Since the S4 signal 211 is 0, it is not accessed by the arithmetic CPU 100. On the other hand, consider that the I / O system CPU 101 accesses the memory allocation space 0 and the memory allocation space 1. From the function table of FIG. 10, the CS6 signal 21
No 1 is output for the 3 and CS7 signals 214. Further, the SL0 signal 215 output from the selection circuit 107,
1 is output to the SL1 signal 216 in order to connect the shared memory A104 and the shared memory B105 to the arithmetic CPU 100. Therefore, shared memory A
104 and the shared memory B105 are the arithmetic CPU 1
00 and not to the I / O CPU 101. Therefore, it cannot be accessed from the I / O system CPU 101. From the above, when the mode 00 is designated, the shared memory A104 and the shared memory B1
05 will be connected to the arithmetic system CPU 100 side, so I
It is understood that the memory allocation space 0 and the memory allocation space 1 cannot be accessed from the / O system CPU 101. Even if the mode is set to 01 and 10, the memory allocation shown in FIG. 6 is performed by the same operation as described above. According to the present embodiment, by providing the memory allocation register 108, the address decoders 102 and 103 controllable by the memory allocation register 108, and the selection circuit 107, the arithmetic CPU 100 and the I / O
It is possible to make the memory allocated to the O-system CPU 101 variable. Further, since the I / O system CPU 101 performs all reading and writing from and to the memory allocation register 108, it is possible to prevent a decrease in the efficiency of the data computing process of the computing CPU 100. Further, since the I / O system CPU 101 can write a value to the memory allocation register 108, it is possible to change the memory allocation during the chip operation.

Further, by externally writing data to the memory allocation register 108 at the start of the chip operation, it is possible to programmatically allocate memory for each user. An example of the configuration is shown in FIG. FIG. 14 shows the pad 12
9, a pad 130, a pass transistor 131, a pass transistor 132 and a memory allocation register 108. The connection relationship is shown below. Pad 129
Are connected to the pass transistor 131 through the signal line 260. The write signal line 259 is connected to the pass transistor 131. Pass transistor 131
Is allocated via the signal line 261 to the memory allocation register 108.
Connected to the MD1 bit. The pad 130 is connected to the pass transistor 132 through the signal line 262. The write signal line 259 is connected to the pass transistor 13
Connected to 2. The pass transistor 132 is connected to MD0 of the memory allocation register 108 through the signal line 263.
Connected to a bit. The operation will be described. At the start of the chip operation, the value to be set in the memory allocation register 108 is applied to the pads 129 and 130. A signal is sent to the write signal line 259. The signal of the write signal line 259 is input to the gates of the pass transistor 131 and the pass transistor 132. Pass transistor 131
And the pass transistor 132 is connected to the write signal line 259.
When a more signal is input, it turns on. When the pass transistor 131 is turned on, the value applied to the pad 129 changes to the signal line 260, the pass transistor 131,
M of the memory allocation register 108 through the signal line 261
Input to D1 bit. Similarly, the value applied to the pad 130 is the MD of the memory allocation register 108 through the signal line 262, the pass transistor 132, and the signal line 263.
Input to 0 bit. As described above, by connecting the pad 129, the pad 130, the pass transistor 131, and the pass transistor 132 to the memory allocation register 108, the user can programmably store the memory for the arithmetic CPU 100 and the I / O CPU 101 at the start of the chip operation. Can be assigned. In the above description, the signal line 259
Is the write signal line, but the same function can be realized by inputting the reset signal line. Also, memory allocation register 1
08 is a non-volatile memory (EPROM, EEPROM)
Etc.) or a fuse. Although the present embodiment has been described using two shared memories, the same effect can be obtained for two or more shared memories if the number of bits of the memory allocation register is increased by the number of shared memories. Can be realized.

As another embodiment for realizing the built-in memory 10 shown in FIG. 1, FIG. 15 shows a bank switching configuration in a shared memory section of a multi-CPU. FIG. 15 is a diagram showing a configuration that makes it possible to allocate two arbitrary shared memories among the four shared memories to the internal memory space existing on the memory map of the arithmetic CPU 100. With this configuration, the arithmetic CPU 100 does not perform the bank switching operation and the I / O CPU 10
It becomes possible to take in the data written in a plurality of shared memories one after another. That is, as described in detail before the embodiments, the arithmetic CPU 100 responds to the same access in response to each interrupt request from the I / O CPU 101 generated at the end of data transfer to one bank. Even though the address is sent to the address bus 202, the same access address is converted each time by the update information of the register 119, and this converted address specifies a plurality of banks 115, 116, 117, 118 one after another. , A plurality of banks 115, 11 by the same access address from the arithmetic CPU 100.
6,117,118 data can be accessed one after another. FIG. 15 shows an arithmetic CPU 100, an I / O CPU 101, an address decoder 113, an address decoder 114, a shared memory C115, a shared memory D116, a shared memory E117, and a shared memory F.
The point that it is composed of 118, a bank switching register 119, and an interrupt control circuit 17 is basically the same as the embodiment of FIG. 1, and a bank switching register 119 is added. That is, the bank switching register 119 is connected to the I / O system internal data bus 201 through the signal line 240, and the address decoder 1 through the SA1 signal 241, the SA0 signal 242, the SB1 signal 243, and the SB0 signal 244.
It is connected to 13. CS0 signal 224, CS1 signal 225, CS2 output from the address decoder 113
The signal 226 and the CS3 signal 227 are connected to the shared memory C115, the shared memory D116, the shared memory E117, and the shared memory F118, respectively. The CS8 signal 228, the CS9 signal 229, the CS10 signal 230, and the CS11 signal 231 output from the address decoder 114 are connected to the shared memory C115, the shared memory D116, the shared memory E117, and the shared memory F118, respectively. FIG. 16 shows a memory map of the arithmetic CPU 100. From this Figure 16, H'8000000
It can be seen that the internal memory spaces A and B are provided from 0 to H'AFFFFFFF. By setting the value in the bank switching register 119 by the I / O CPU 101,
Any two of the shared memory C115, the shared memory D116, the shared memory E117, and the shared memory F118 are allocated to the internal memory spaces A and B. Therefore, the arithmetic CPU 100 cannot simultaneously recognize the four shared memories.

A memory map of the I / O system CPU 101 is shown in FIG. FIG. 17 shows that the I / O CPU 101 can simultaneously recognize four shared memories. Therefore, the I / O system CPU 101
The shared memory C115, shared memory D116, shared memory E117 and shared memory F118 can be accessed.

The configuration of the bank switching register 119 is shown in FIG.
8 shows. As shown in FIG. 15, the bank switching register 119 includes a signal line 240 and an I / O system internal data bus 2.
Through 01, the I / O system CPU 101 can read and write. The bank switching register 119 has SA1, SA
It is composed of 4 bits of 0, SB1, and SB0. S
The shared memory to be allocated to the internal memory space A on the memory map of the arithmetic CPU 100 is set by 2 bits of A1 and SA0. The shared memory to be allocated to the internal memory space B on the memory map of the arithmetic CPU 100 is set by 2 bits of SB1 and SB0.

FIG. 19 shows a block diagram of the address decoder 113 on the arithmetic system CPU 100 side. From this Figure 19,
A31, A28 and SA of the arithmetic system upper address 203
1 signal 241, SA0 signal 242, SB1 signal 243,
SB0 signal 244, CS0 signal 224, CS1 signal 2
25, the CS2 signal 226 and the CS3 signal 227 are controlled. The CS0 signal 224, CS1 signal 225, CS2 signal 226 and CS3 signal 227 are
Shared memory C115 and shared memory D1 respectively
16, shared memory E117, shared memory F11
8 is a signal line for selecting 8.

The function of the address decoder 113 is shown in FIG.
Shown in. When A31 = 0, the external space is designated, and therefore 0 is output to the CS0 signal 224, the CS1 signal 225, the CS2 signal 226, and the CS3 signal 227 because no memory is selected. (A31, A28) = (1,0)
Specifies the memory space A. In this case, the values of the SA1 signal 241 and the SA0 signal 242 designated by the space A are valid. When (SA1, SA0) = (0, 0), only 1 is output as the CS0 signal 224 designating the shared memory C115. When (SA1, SA0) = (0, 1), the CS1 signal 22 that specifies the shared memory D116
Only 5 is output as 1. (SA1, SA0) = (1,
When it is 0), CS that specifies the shared memory E117
Only the 2 signal 226 is output as 1. (SA1, SA0)
When = (1,1), 1 is output only for the CS3 signal 227 designating the shared memory F118. (A31,
A28) = (1,1) specifies the memory space B. In this case, the values of the SB1 signal 243 and the SB0 signal 244 that specify the space B are valid. (SB1, SB0) = (0,
When 0), CS that specifies the shared memory C115
Only the 0 signal 224 is output as 1. (SB1, SB0)
When = (0,1), only 1 is output as the CS1 signal 225 designating the shared memory D116. (SB1,
When SB0) = (1,0), the shared memory E11
Only the CS2 signal 226 designating 7 is output as 1.
When (SB1, SB0) = (1, 1), only 1 is output as the CS3 signal 227 designating the shared memory F118. The operation will be described below. I / O CPU 101
The operation of passing the data written in the shared memory C115 and shared memory D116 to the arithmetic CPU 100 will be described. The I / O CPU 101 is H'C00.
The space of H'CFFFFFFF is accessed from 00000 and the data is written in the shared memory C115. After writing the data to the shared memory C115, the I / O system CPU 101 next accesses the space from H'D0000000 to H'DFFFFFFF and writes the data to the shared memory D116. Shared memory C11
5 and the data is written in the shared memory D116, the I / O system CPU 101 sets a value in the bank switching register 119. Shared memory C115,
The values representing the shared memory D116, shared memory E117, and shared memory F118 are 00, 01, and
10 and 11, in order to connect the shared memory C115 and the shared memory D116 to the arithmetic CPU 100, the bank switching register 119 (SA1, SA
The values 0) = (0,0) and (SB1, SB0) = (0,1) are set. When the setting of the value in the bank switching register 119 is completed, the I / O system CPU 101 interrupts the arithmetic system CPU 100 by the interrupt means.
115, Notify completion of data set to the shared memory D116. After that, the I / O system CPU 101 operates the arithmetic system C
Data is written to the shared memory E117 and the shared memory F118 that the PU 100 does not access.
On the other hand, the arithmetic system CPU 100 that has received the interrupt interrupts the data arithmetic processing that has been executed until then, and the internal memory space A
And recognizing that the data set to the internal memory space B is completed, the access to the internal memory space A and the internal memory space B is started. When accessing the internal memory space A, (A31, A28) = (1, 0). Since (SA1, SA0) = (0, 0) is set in the SA1 signal 241 and the SA0 signal 242 of the bank switching register 119, C which selects the shared memory C115.
1 is output only to the S0 signal 224. Therefore, when the internal memory space A is accessed, the shared memory C115
Can be accessed. When accessing the internal memory space B, (A31, A28) = (1, 1). Since (SB1, SB0) = (0, 1) is set in the SB1 signal 243 and the SB0 signal 244 of the bank switching register 119, the CS for selecting the shared memory D116 is selected.
1 is output only to one signal 225. Therefore, when the internal memory space B is accessed, the shared memory D116 can be accessed. When the access to the shared memory C115 and the shared memory D116 is completed, the arithmetic system C
The PU 100 generates an interrupt to the I / O system CPU 101 to notify that the access is completed. After that, the arithmetic CPU 100 returns to the original data arithmetic processing. On the other hand, the I / O system CPU 101 sets a value in the bank switching register 119 when the data set in the shared memory E117 and the shared memory F118 is completed, and causes the arithmetic system CPU 100 to generate an interrupt again. From the above, the I / O system CPU 101 performs the value setting to the memory and the bank switching operation.
Banks can be switched while preventing a decrease in the U data calculation processing efficiency. The shared memories C115 and E117 in the internal memory space A of the arithmetic CPU 100 have the same access address H'8000 of the arithmetic CPU 100.
Operation system CPU that can be accessed from 0000
Shared memory D11 in the internal memory space B of 100
6, F118 can be accessed from the same access address H'90000000 of the arithmetic CPU 100.

FIG. 21 shows details of the internal / external bus control circuit 16 of FIG. Internal / external bus control circuit 16
In the inside of, the three sequential circuits of an external bus control circuit 50, an arithmetic system internal bus control circuit 51, an I / O system internal bus control circuit 52, an access right setting register 53, and two O
It is composed of R logic gates 54 and 55. The external bus control circuit 50 includes an operation system address bus 202 and I / O.
The system address bus 204, the access right setting register 53, and the data of the WAIT control signal 23 for controlling the extension of the bus cycle input from the outside of the chip are input. Based on these input data, the external bus control circuit 5
0 changes the internal state of the sequential circuit, and controls signals of the multiplexer 18 of the arithmetic system data bus 200 and the I / O system internal data bus 201 and the multiplexer 19 of the arithmetic system address bus 202 and the I / O system address bus 204. 20, an external access end signal 56 for the arithmetic CPU 100 and an external access end signal 58 for the I / O CPU 101 are output. The access right setting register 53 is
I / O system CPU connected to O system internal data bus 201
The configuration is such that 101 can read and write data. The arithmetic system internal bus control circuit 51 includes an arithmetic system address bus 2
The data on 02 is input. Based on this data, the internal state of the sequential circuit is transited, and at the same time, the arithmetic CPU
The internal access end signal 57 of 100 is output. I / O
The system internal bus control circuit 52 includes the I / O system address bus 2
The data on 04 is input. Based on this data, the internal state of the sequential circuit is transitioned, and at the same time, the I / O system CP
The internal access end signal 59 of U101 is output. The external access end signal 56 and the internal access end signal 57 of the arithmetic CPU 100 are ORed by the OR logic gate 54 and output as the control signal 24 instructing the completion of the bus cycle. Similarly, I / O CPU 101
External access end signal 58 and internal access end signal 5
9 is ORed by the OR logic gate 55 and output as the control signal 25 instructing the completion of the bus cycle. Arithmetic CPU 100 and I / O CPU 10
The address output by 1 for data access is
As shown in FIGS. 3, 4, 16 and 17, the address map is determined as the chip specification. Therefore, since the external access and the internal access can be distinguished by the address map, the three bus control circuits 50, 51, 52 composed of sequential circuits can recognize the bus cycle to be controlled. For example, arithmetic system C
Since the arithmetic system internal bus control circuit 51 is not performing internal data access control while the PU 100 is performing external access, the internal access end signal 57 is “1”.
Output 0'level. The data of the access right setting register 53 input to the external bus control circuit 50 is the operation system C
It specifies which of the PU 100 and the I / O system CPU 101 has the priority of external access. Fast page
When reading a large amount of data stored in a space where addresses on a dynamic memory (DRAM) that can be accessed are continuous, data access within the same page is speeded up, so continuous reading is actually preferable. The total amount of memory access time required for this is reduced. Burst access may be required in some cases when accessing a device for which a data transfer cycle is specified. Therefore, it is necessary to have a mode in which either the CPU of the operation system or the I / O system is dedicated to external access. I / O CPU 101 makes this designation
This is performed by writing mode information to the access right setting register 53 via the O-system internal data bus 201.

FIG. 21 shows the access right setting register 53.
FIG. 7 shows a timing chart in the case where the external access priorities of the two CPUs of the operation system and the I / O system are set equal. During the period of T1, the I / O CPU 101 and the arithmetic C
The internal access 1 and the internal access A are simultaneously performed with the PU 100. During the period of T2, I / O system CPU1
01 executes external access 2 and, at the same time, arithmetic CPU 1
00 performs internal access B and C. During the period T3, the external access 2 of the I / O system CPU 101 is continuing, so the external access D of the arithmetic system CPU 100 is in a waiting state. During the period T4, the external access D of the CPU 100 in the waiting state is executed, and I
External access 3 of the / O system CPU 101 is in a waiting state. The external access 3 in the waiting state is T5.
Will be executed from the period. Thus, in this mode,
The external access ratios of the two arithmetic CPUs 100 and 101 are set to be equal.

FIG. 23 shows the access right setting register 53.
2 shows a timing chart when the mode (exclusive continuous use right to the I / O system CPU 101) for monopolizing the I / O system CPU 101 for external access is set. During the period of T1, the I / O CPU 101 and the arithmetic CPU 100 are simultaneously performing the internal access 1 and the internal access A. During the period of T2, the I / O system CPU 101 executes the external access 2, and at the same time, the arithmetic system CPU 100 executes the internal access B and C. The external access D of the arithmetic CPU 100 which is about to be performed during the period of T8 is
It is not executed until the access right setting register 53 releases the designation of the external access exclusive mode of the I / O system CPU 101. Therefore, in this mode, I / O system CPU1
01 will have exclusive access to the outside. Contrary to this example, the access right setting register 53 arithmetic system CPU 100
It goes without saying that it is possible to create a mode that allows external access to be exclusively used.

Next, as an embodiment of the interrupt control circuit 17 shown in FIG. 1, FIG. 24 shows a block diagram of an interrupt system of a multi-CPU. FIG. 24 shows an arithmetic CPU 100, an I / O CPU 101, an interrupt control circuit 120, an interrupt flag register 121, an interrupt control circuit 122, an interrupt flag register 123, an A / D and D / A converter 124, a timer TMR 125, and a serial input. Output interface SC
I126 and interrupt vector registers 127 and 128. With this configuration, the I / O system CPU 101
From the CPU to the arithmetic CPU 100, and the arithmetic CP
It is possible to interrupt the U100 to the I / O CPU 101. That is, the arithmetic system internal data bus 200 includes the interrupt flag register 123 and the interrupt vector register 1
28 is connected. Interrupt vector register 128
Are further connected to the I / O system internal data bus 201. The interrupt flag 123 is connected to the interrupt control circuit 122 through a signal line 248. An external interrupt request signal 249 and an internal interrupt request signal 250 are connected to the interrupt control circuit 122. Interrupt control circuit 1
22 is connected to the interrupt flag 123 through the interrupt flag clear signal 257. Interrupt control circuit 122
Are connected to the interrupt vector register 127 through the interrupt vector read signal 256. The interrupt control circuit 122 is connected to the I / O system CPU 101 through an interrupt request signal 247 and an interrupt vector signal 258. The I / O system internal data bus 201 is connected to the interrupt flag register 121 and the interrupt vector register 127. The I / O system internal data bus 201 is connected to the A / D and D / A converter 124 through a signal line 251, and is connected to the TMR 125 through a signal line 252.
It is connected to the SCI 126 through a signal line 253.
The interrupt vector register 127 is connected to the arithmetic system internal data bus 200. The interrupt flag 121 is connected to the interrupt control circuit 120 via a signal line 246. The interrupt control circuit 120 is connected to the arithmetic system CPU 100 through an interrupt request signal 245. The interrupt control circuit 120 is connected to the interrupt flag 121 through an interrupt flag clear signal 254. The interrupt control circuit 120 is connected to the interrupt vector register 127 through the interrupt vector read signal 255. The operation will be described below. The arithmetic system CPU 100 sets a vector address in the interrupt vector 128 through the arithmetic system internal data bus 200, and further, the arithmetic system internal data bus 2
A value is set in the interrupt flag 123 through 00. The interrupt flag 123 is transmitted to the interrupt control circuit 122 through the signal line 248. When the interrupt control circuit 122 receives a signal from the signal line 248, it outputs a signal to the interrupt request signal 247. Interrupt vector read signal 25 at the same time
The signal is output to 6. The interrupt vector register 128 is
When receiving a signal from the interrupt vector read signal 256,
The vector address is output to the I / O system internal data bus 201. When the I / O CPU 100 receives the signal from the interrupt request signal 247, it recognizes that it is an interrupt from the arithmetic CPU 100, reads the vector address output to the I / O internal data bus 201, and according to this value. Start interrupt request processing. At this time, the interrupt control circuit 122 causes the I / O CPU 100 to interrupt the interrupt request signal 24
When it recognizes that the signal No. 7 has been received, the signal line 257
To reset the value set in the interrupt flag 123. When an interrupt occurs from the external interrupt request signal 249 or the internal interrupt request signal 250, the interrupt control circuit 122 outputs a signal to the interrupt request signal 247 and at the same time outputs a vector address to the interrupt vector signal 258. Further, the interrupt control circuit 12 is configured so that the vector address is not output from the interrupt vector register 128.
2 does not output a signal to the interrupt vector read signal 256. When the I / O system CPU 100 receives the signal from the interrupt request signal 247, it recognizes that it is an external interrupt or an internal interrupt, reads the vector address output to the interrupt vector signal 258, and executes interrupt processing according to this value. To do. I / O CPU 100 to operation CP
The interrupt control circuit 120, the interrupt flag register 123, and the interrupt vector register 127 can be used to generate an interrupt to the U100 in the same manner as described above.

Voice processing will be considered as an application of the single-chip Mycoro computer shown in FIGS.
FIG. 25 shows a processing procedure of input data to be processed by the arithmetic CPU 100 in the form of an arithmetic memory map. In FIG. 25, shared memory C115 and shared memory D1
16, the data is processed in the order of the shared memory E117. The state of FIG. 24 (1) shows the present operation CPU 100.
Represents the shared memory handled by. in this case,
A shared memory C115 is connected to the internal memory space A, and a shared memory D116 is connected to the internal memory space B. Shared memory C115 and shared memory D
When the data calculation processing of 116 is completed in sequence, FIG.
The shared memory must be connected as in (2). Looking at FIG. 24B, the internal memory space A of FIG.
The shared memory C115 that was there was no longer connected,
Instead, it can be seen that the shared memory D116, which was connected to the internal memory space B, is connected to the internal memory space A, and the shared memory E117 is newly connected to the internal memory space B. In voice processing, when data is divided into certain sizes and processed, in order not to deteriorate the quality of the data calculation processing at the divided boundaries,
It is necessary to leave the data processed immediately before and restart the processing from that part. Therefore, after the processing of FIG. 25 (1) is completed, the data in the shared memory D116, which is the immediately preceding data, can be processed first in the state of FIG. 25 (2), and then new data is stored. The shared memory E117 is connected. In order to realize the above operation, the operation of the single-chip Mycoro computer shown in FIG. 15 will be described below. Operation system CP
In order not to write data to the shared memory already connected to U100, the I / O system CPU 101 reads the bank switching register 119 before inputting the data to be processed to the shared memory, and the current operation system CPU
Find out which shared memory is connected to 100. Now, it is assumed that no shared memory is connected to the arithmetic CPU 100 at the stage of transferring the first audio processing data. The I / O system CPU 101 sets a value in the access right register 53 in the internal / external bus control circuit 16 of FIG. 21 to set the mode in which the I / O system CPU 101 exclusively uses external access. As a result, the access right register 53 transfers the set value to the external bus control circuit 5
Output to 0. When receiving the value set in the access right register 53, the external bus control circuit 50 in FIG. 21 outputs a signal to the control signal 20. The signals of the control signal 20 are input / output through the external data bus 21 and the external address bus 22, respectively.
O system internal data bus 201 and I / O system address bus 20
Control multiplexers 18 and 19 to be connected to 4. The I / O system CPU 101 transfers the address of the external space to the I / O system address bus 2 in order to perform external access.
Output to 04. The address output from the I / O system CPU 101 to the I / O system address bus 204 is output to the external address bus 22 through the multiplexer 19.
The data of the external memory accessed by the output address is input to the I / O system internal data bus 201 through the external data bus 21 and the multiplexer 18. I
The I / O system CPU 101 is an I / O system internal data bus 201.
Transfer the data input to the shared memory. Since the current state is the initial stage of voice processing and there is no shared memory connected to the arithmetic CPU 100, the data fetched from the outside is transferred in the order of the shared memory C115 and the shared memory D116. When data transfer to the two shared memories is completed, I / O system CPU1
A value 01 is set in the bank switching register 119 of FIG. 15 in order to represent the shared memory for which the data transfer is completed. In this case, since the data is stored in the shared memory C115 and the shared memory D116 in this order, the bank switching register 119 receives (SA1, SA0, SB).
1, SB0) = (0, 0, 0, 1) is set. Next, the I / O system CPU 101 fetches the data transferred to the shared memory, and sets a vector address in the interrupt vector register 127 of FIG. Finally I / O system CP
The U 101 sets a value in the interrupt flag 121. After that, the I / O system CPU 101 replaces the current operation system CPU 100.
The external data is transferred in the order of the shared memory E117 and the shared memory F118 which are not connected to each other. on the other hand,
When a value is set in the interrupt flag register 121 of FIG. 24, the interrupt flag register 121 outputs a signal to the signal line 246. When the interrupt control circuit 120 receives a signal from the signal line 246, it outputs an interrupt request signal to the interrupt request signal 245. At the same time, the interrupt control circuit 120 outputs "1" to the vector address read signal 255 in order to output the vector address stored in the interrupt vector register 127 to the arithmetic system internal data bus 200.
When the interrupt vector register 127 receives the signal from the vector address read signal 255, it outputs the vector address to the arithmetic system internal data bus 200. Arithmetic CPU 1
00 receives the interrupt request signal from the interrupt request signal 245, interrupts the data operation processing up to that point, and the I / O system C
Recognizing that it is an interrupt from the PU 101, the vector address output to the arithmetic system internal data bus 200 is fetched. The interrupt control circuit 120 is the arithmetic CPU 10.
0 receives an interrupt, interrupt flag 121
"1" is output to the interrupt flag clear signal 254 in order to clear the value set in. When receiving the signal from the interrupt flag clear signal 254, the interrupt flag register 121 clears the interrupt flag. Arithmetic CPU
100 reads a program for processing the data stored in the shared memory from the fetched vector address and executes the program. In this case, the arithmetic CPU 1
00 accesses the internal memory space A and the internal memory space B. When accessing the internal memory space A, the arithmetic address buses A31 and A28 are (A31, A2).
8) = (1,0). At this time (SA1, SA0)
= (0,0), the shared memory C11
"1" is output only to the CS0 signal 224 designating "5". Therefore, the arithmetic CPU 100 is the I / O CPU 10
The data transferred by the 1 to the shared memory C115 can be fetched. Further, when the arithmetic CPU 100 accesses the internal memory space B, the arithmetic address buses A31 and A28 are (A31, A28) = (1, 1). At this time, since (SA1, SA0) = (0, 1), “1” is output only to the CS1 signal 225 designating the shared memory D116. Therefore, the calculation system CP
In U100, I / O CPU 101 is shared memory D
The data transferred to 116 can be captured. From the above, the I / O system CPU 101 has the shared memory C
The data transferred to the shared memory D116 and the shared memory D116 can be transferred to the arithmetic system CPU 100.
The state of (1) can be realized. Arithmetic CPU 1
In 00, the original data arithmetic processing can be executed until the I / O system CPU 101 fetches the external data, stores it in the memory, and generates the interrupt request signal, so that it is possible to prevent the deterioration of the data arithmetic processing efficiency. Arithmetic CPU 10
0 is a shared memory C115 and a shared memory D
When the data of 116 has been taken in, the vector address is set in the interrupt vector register 128 through the internal data bus 200 of the operation system. Next, the arithmetic CPU 100
Sets a value in the interrupt flag register 123 through the arithmetic system internal data bus 200, and then the arithmetic system CPU 10
0 continues the original data calculation processing. When the signal is set, the interrupt flag register 123 outputs the signal set on the signal line 248. Interrupt control circuit 122
When receiving a signal from the signal line 248, the arithmetic CPU 10
Recognizes that it is an interrupt from 0, and interrupt request signal 2
An interrupt request signal is output to 47. At the same time, the interrupt control circuit 122 outputs a signal to the interrupt vector read signal 256. The interrupt vector register 128 receiving the signal from the interrupt vector read signal 256 outputs a value to the I / O system internal data bus 201. At this time, the interrupt control circuit 122 does not output the vector address to the interrupt vector signal 258. When the I / O CPU 101 receives the interrupt request signal from the interrupt request signal 247, the arithmetic CPU
The interrupt from 100 is recognized, and the vector address output to the I / O system internal data bus 201 is fetched. The interrupt control circuit 122 is the I / O system CPU 10
When 1 receives an interrupt, it outputs a signal to the interrupt flag clear signal 257, and the interrupt flag register 1
Clear 23. The I / O CPU 101 executes the processing program after the arithmetic CPU 100 has fetched the data in the shared memory from the fetched vector address. I / O CPU 101 is shared memory E1
If the data transfer to 17 is not yet completed, the data transfer is continued. On the other hand, shared memory E117
When the data transfer to the terminal has been completed, FIG. 25 (2)
The following operations are performed to bring the state into. The I / O system CPU 101 newly sets a value in the bank switching register 119. In this case, (SA1, SA0, SB
1, SB0) = (0, 1, 1, 0) is set, and the shared memory D is allocated to the internal memory space A and the shared memory E is allocated to the internal memory space B. In voice processing, if the sample data is divided into appropriate lengths and processed, the previously processed data is processed again before the next data is processed, and then the new shared memory data is processed. There must be. This is because the quality of the audio processing at the boundary portion that divides the data is not deteriorated. Therefore, the shared memory D is moved to the internal memory space A. When the setting of the value in the bank switching register 119 is completed, the I / O system CPU 101 issues an interrupt request to the arithmetic system CPU 100 in the same procedure as described above. Arithmetic system C
When receiving an interrupt request signal from the I / O system CPU 101, the PU 100 takes in a vector address from the arithmetic system internal data bus 200. From the fetched vector address, enter the program that fetches the shared memory data and execute the program. In this case, the shared memory D116 is stored in the internal memory space A and the shared memory D116 is stored in the internal memory space B.
A shared memory E117 is connected to. Here, the point different from the above is that the processing of the data in the shared memory D116 has already been completed. Therefore, if the processing is performed from the beginning of the shared memory D116, the same processing is performed twice. Therefore, in this case, in the program fetched by the interrupt request, the actual processing is started from an arbitrary address which is considered necessary by the programmer after H'80000000, for example. When the processing is started from here and the value of the shared memory is read in, the arithmetic CPU 100
Issues an interrupt request to the I / O system CPU 101. I / O
Upon receiving an interrupt request from the arithmetic CPU 100, the CPU 101 newly sets data in the shared memory and transfers it to the arithmetic CPU 100. By repeating the above operation, the voice processing can be executed without reducing the data calculation processing efficiency of the CPU. Thus, in this application example, the bank switching register, the shared memory,
By using a multi-CPU single-chip microcomputer provided with a CPU readable / writable interrupt flag and an interrupt vector register, it is possible to execute the voice processing without lowering its efficiency. Further, by realizing the configuration of the present invention on one chip, it becomes possible to operate at a higher speed than in the case where it is realized by a plurality of chips. Furthermore, the number of pins of one chip can be reduced as compared with the case of realizing with a plurality of chips. Further, it can be supplied at a low cost as compared with the case where it is realized by a plurality of chips. In the present invention, 4
The explanation was made using two shared memories. If the number of bits of the bank switching register is set to represent the number of shared memories, four or more shared memories can be supported. Also, by increasing the number of address signals input to the address decoder, it is possible to increase the number of internal memory spaces to which the memory is allocated. It is also possible to reduce the size of one memory space at this time.

[0040]

According to the present invention, in a single-chip microcomputer having a plurality of CPUs, interrupt request processing from peripheral modules can be executed at high speed, and the efficiency of data arithmetic processing of the CPUs can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a multi-CPU according to an embodiment of the present invention.

FIG. 2 is a diagram showing a shared memory unit of the multi-CPU of FIG.

FIG. 3 is a diagram showing a memory map of the arithmetic CPU of FIG.

4 is a diagram showing a memory map of the I / O system CPU of FIG. 1. FIG.

5 is a diagram showing the memory allocation register of FIG. 2;

FIG. 6 is a diagram showing a relationship between a mode designation and a memory map of the multi CPU shown in FIG.

FIG. 7 is a block diagram of an address decoder on the arithmetic system CPU side.

FIG. 8 is a diagram showing the function of an address decoder on the arithmetic system CPU side.

FIG. 9 is a block diagram of an address decoder of an I / O system CPU.

FIG. 10 is a diagram showing a function of an address decoder of an I / O system CPU.

FIG. 11 is a block diagram of a selection circuit.

FIG. 12 is a diagram showing a function of a selection circuit.

FIG. 13 is a diagram showing a configuration of a shared memory.

FIG. 14 is a diagram showing a configuration of another memory allocation register.

FIG. 15 is a diagram showing an embodiment of a multi-CPU that realizes bank switching in the shared memory unit.

FIG. 16 is a diagram showing a memory map of an arithmetic CPU.

FIG. 17 is a diagram showing a memory map of an I / O system CPU.

FIG. 18 is a diagram showing a configuration of a bank switching register.

FIG. 19 is a block diagram of an address decoder on the arithmetic system CPU side.

FIG. 20 is a diagram showing the function of an address decoder on the arithmetic system CPU side.

FIG. 21 is a diagram showing a configuration of an internal / external bus control circuit.

FIG. 22 is a diagram showing a timing chart when the external access of two CPUs is equally set in the access right setting register.

FIG. 23 is a diagram showing a timing chart when the I / O system CPU sets a mode dedicated to external access in the access right setting register.

FIG. 24 is a diagram showing the configuration of an interrupt control circuit in more detail.

FIG. 25 is a diagram showing a change in an arithmetic CPU memory map during execution of voice processing.

[Explanation of symbols]

10 ... Built-in memory, 11 ... Timer, 12 ... A / D and D / A converter, 13 ... Serial input / output interface,
14 ... Multiplier / divider, 15 ... Function calculator, 16 ... Internal / external bus control circuit, 17 ... Interrupt control circuit, 18 ... Multiplexer, 19 ... Multiplexer, 20 ... Control signal, 21
... External data bus, 22 ... External address bus, 23 ... W
AIT control signal, 24 ... control signal, 25 ... control signal, 5
0 ... External bus control circuit, 51 ... Arithmetic system internal bus control circuit, 52 ... I / O system internal bus control circuit, 53 ... Access right setting register, 54 ... OR circuit, 55 ... OR circuit, 5
6 ... External access end signal, 57 ... Internal access end signal, 58 ... External access end signal, 59 ... Internal access end signal, 100 ... Arithmetic CPU, 101 ... I / O system C
PU, 102 ... Address decoder, 103 ... Address decoder, 104 ... Shared memory A, 105 ... Shared memory B, 107 ... Selection circuit, 108 ... Memory allocation register, 109 ... Memory, 110 ... Selection circuit, 111 ...
Selection circuit, 112 ... Selection circuit, 113 ... Address decoder, 114 ... Address decoder, 115 ... Shared memory C, 116 ... Shared memory D, 117 ... Shared memory E, 118 ... Shared memory F, 119 ... Bank switching register, 120 ... Interrupt control circuit, 121 ... Interrupt flag, 122 ... Interrupt control circuit, 123 ... Interrupt flag, 124 ... A / D, 125 ... TMR, 126 ... SC
I, 127 ... Interrupt vector register, 128 ... Interrupt vector register, 129 ... Pad, 130 ... Pad, 13
1 ... pass transistor, 132 ... pass transistor, 2
00 ... Operation system internal data bus, 201 ... I / O system internal data bus, 202 ... Operation system address bus, 203 ... Operation system upper address, 204 ... I / O system address bus, 20
5 ... I / O system upper address, 206 ... Signal line, 207 ...
Signal line, 208 ... Signal line, 209 ... Signal line, 210 ... Signal line, 211 ... CS4 signal, 212 ... CS5 signal, 21
3 ... CS6 signal, 214 ... CS7 signal, 215 ... SL0
Signal, 216 ... SL1 signal, 217 ... Signal line, 218 ...
Signal line, 219 ... Signal line, 220 ... Operation system lower address, 221 ... Operation system lower address, 222 ... I / O system lower address, 223 ... I / O system lower address, 224 ...
CS0 signal, 225 ... CS1 signal, 226 ... CS2 signal, 227 ... CS3 signal, 228 ... CS8 signal, 229
... CS9 signal, 230 ... CS10 signal, 231 ... CS1
1 signal, 232 ... Operation system lower address, 233 ... Operation system lower address, 234 ... Operation system lower address, 235 ...
Operation system lower address, 236 ... I / O system lower address,
237 ... I / O system lower address, 238 ... I / O system lower address, 239 ... I / O system lower address, 240 ... Signal line, 241 ... SA1 signal, 242 ... SA0 signal, 24
3 ... SB1 signal, 244 ... SB0 signal, 245 ... Interrupt request signal, 246 ... Signal line, 247 ... Interrupt request signal,
248 ... Signal line, 249 ... External interrupt request signal, 250
... internal interrupt request signal, 251 ... signal line, 252 ... signal line, 253 ... signal line, 254 ... interrupt flag clear signal, 255 ... interrupt vector read signal, 256 ... interrupt vector read signal, 257 ... interrupt flag clear signal, 258 ... interrupt vector read signal, 259 ... write signal line, 260 ... signal line, 261, ... signal line, 262 ...
Signal line, 263 ... Signal line.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Yoshihito Yoshihito 1-280, Higashi Koikeku, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Ikeda 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Akio Amano 1-280 Higashi Koikekubo, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Haruo Uemaki 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Center ( 72) Inventor Yoshiaki Asakawa 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory

Claims (5)

[Claims] 1. A first and second processor for outputting an address, a first address bus and a first data bus connected to the first processor, and a first processor connected to the second processor. A second address bus and a second data bus; a built-in memory connected to the first and second address buses and the first second data bus; and a first and a second address bus. A selection circuit for connecting the selected one and the selected one of the first and second data buses to an external address bus (22) and an external data bus (21); A peripheral module, which is at least one of a timer, an A / D converter and a D / A converter, and a serial input / output interface, is connected to the data bus of, and an interrupt control is provided to the second processor and the peripheral module. Circuit is connected, the interrupt control circuit semiconductor integrated circuit, characterized in that forwarding the interrupt request from the peripheral module to said second processor. 2. The interrupt control circuit is further connected to the first processor, and receives an interrupt request from the second processor generated at the end of transfer of external data by the second processor to the internal memory. 2. The semiconductor integrated circuit according to claim 1, wherein the interrupt control circuit transfers the interrupt control circuit to the first processor. 3. A designation means for designating one of the first processor and the second processor, further comprising a plurality of accesses from the first processor and the second processor.
The plurality of accesses from the processor, the selection circuit executes the plurality of accesses from the designated one exclusively and continuously by connecting the designated one to the external address bus. The semiconductor integrated circuit according to claim 1. 4. The built-in memory is composed of a plurality of banks, and storage means for storing information controlling access to the plurality of banks is connected to the second data bus, and the first address bus is connected to the first data bus. A first address decoder for controlling access to the plurality of banks from the first processor via the first address bus in response to upper bits of the first address bus and information in the storage means. A second bus via the second data bus each time data transfer to the at least one of the plurality of banks of external data accessed by the second processor is completed. And updating the information in the storage means to transfer the external data accessed by the second processor to at least one of the plurality of banks. The interrupt control circuit transfers an interrupt request from the second processor generated at the end of each transmission to the first processor, and the first processor causes each interrupt request at the end of the data transfer. 2. The semiconductor integrated circuit according to claim 1, wherein the same access address is sent to the first address bus in response to the response. 5. An auxiliary arithmetic module, which is at least one of a multiplier / divider, a function arithmetic unit, and a floating point arithmetic processor, is connected to the first data bus. The semiconductor integrated circuit described in any one of the above.