JPS6381431U - - Google Patents
Info
- Publication number
- JPS6381431U JPS6381431U JP17431286U JP17431286U JPS6381431U JP S6381431 U JPS6381431 U JP S6381431U JP 17431286 U JP17431286 U JP 17431286U JP 17431286 U JP17431286 U JP 17431286U JP S6381431 U JPS6381431 U JP S6381431U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- synchronization
- circuit
- output
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims 2
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第1図は本考案による位相同期型受信機の構成
図、第2図は、従来の位相同期型受信機の構成図
である。
図において、1は受信信号入力端子、2は同期
信号出力端子、3は位相検波器、4はループフイ
ルタ、5は演算増幅器、6は帰還回路、7は電圧
制御発振器、8は同期検出回路、9は同期信号保
持回路、10はOR回路である。なお、図中同一
あるいは相当部分には同一符号を付してある。
FIG. 1 is a block diagram of a phase-locked receiver according to the present invention, and FIG. 2 is a block diagram of a conventional phase-locked receiver. In the figure, 1 is a received signal input terminal, 2 is a synchronization signal output terminal, 3 is a phase detector, 4 is a loop filter, 5 is an operational amplifier, 6 is a feedback circuit, 7 is a voltage controlled oscillator, 8 is a synchronization detection circuit, 9 is a synchronization signal holding circuit, and 10 is an OR circuit. In addition, the same reference numerals are given to the same or corresponding parts in the figures.
Claims (1)
圧制御発振器と、上記受信信号入力端子から入力
される入力信号と、上記電圧制御発振器の出力信
号とを位相比較する位相検波器と、上記位相検波
器の出力信号を平滑するループフイルタと、帰還
回路と、上記ループフイルタの出力信号を増幅し
、かつ上記帰還回路と組合せて、発振器を構成す
る演算増幅器と、上記受信信号入力端子から入力
される受信信号と上記電圧制御発振器の出力信号
の位相が同期した時同期信号を出力する同期検出
回路と、上記同期検出回路の出力信号がOFFと
なつても一定時間同期保持がONとなるよう、同
期信号を保持する同期信号保持回路と、上記同期
検出回路と上記同期信号保持回路の出力信号のい
ずれかがONの時、上記帰還回路と上記演算増幅
器で構成する発振器の発振を停止する信号を出力
するON回路を備えたことを特徴とする位相同期
型受信機。 a received signal input terminal, a synchronization signal output terminal, a voltage controlled oscillator, a phase detector that compares the phase of the input signal input from the received signal input terminal and the output signal of the voltage controlled oscillator, and the phase detector. a loop filter that smoothes the output signal of the device, a feedback circuit, an operational amplifier that amplifies the output signal of the loop filter and configures an oscillator in combination with the feedback circuit; A synchronization detection circuit outputs a synchronization signal when the phases of the received signal and the output signal of the voltage controlled oscillator are synchronized, and a synchronization detection circuit is configured to maintain synchronization for a certain period of time even if the output signal of the synchronization detection circuit is OFF. A synchronization signal holding circuit that holds the signal, and when any of the output signals of the synchronization detection circuit and the synchronization signal holding circuit are ON, outputs a signal that stops the oscillation of the oscillator constituted by the feedback circuit and the operational amplifier. A phase synchronized receiver characterized by being equipped with an ON circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17431286U JPS6381431U (en) | 1986-11-13 | 1986-11-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17431286U JPS6381431U (en) | 1986-11-13 | 1986-11-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6381431U true JPS6381431U (en) | 1988-05-28 |
Family
ID=31112578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17431286U Pending JPS6381431U (en) | 1986-11-13 | 1986-11-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6381431U (en) |
-
1986
- 1986-11-13 JP JP17431286U patent/JPS6381431U/ja active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6381431U (en) | ||
JPS6381430U (en) | ||
JPS633644U (en) | ||
JPH0328606Y2 (en) | ||
JPS6425251U (en) | ||
JPS6347638U (en) | ||
JPS62191227U (en) | ||
JPS6030645U (en) | phase synchronized receiver | |
JPS5910817Y2 (en) | receiver tuning circuit | |
JPH02134781U (en) | ||
JPS62186533U (en) | ||
JPS6188333U (en) | ||
JPS6165366U (en) | ||
JPH03117946U (en) | ||
JPH0282133U (en) | ||
JPS62181046U (en) | ||
JPS6197223U (en) | ||
JPH0178444U (en) | ||
JPS6261546U (en) | ||
JPH0344339U (en) | ||
JPH01179629U (en) | ||
JPH02128433U (en) | ||
JPH0170435U (en) | ||
JPH01133827U (en) | ||
JPH0293811U (en) |