JPS637620B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electric circuit technology for non-destructive testing of solids using ultrasonic energy, and in particular to an electric circuit technology for non-destructive testing of solids using ultrasonic energy, and particularly for detecting defects existing in close proximity within a solid. Regarding echo gate circuits.

Conventionally, gate circuits that use ultrasonic energy for non-destructive testing of solids have been used for porosity testing, material classification, general non-destructive testing, etc. using the ultrasonic pulse-echo principle. A plurality of timing gates having a predetermined pulse width are sequentially operated, and an echo signal indicating a defect is recorded at a gate that is open for a predetermined period of time. Therefore, this type of gate has the disadvantage that when multiple defects exist close to each other in a solid, two defect display signals are input to one gate and are treated as one defect. Another drawback is that if the defect indication signal is received at a transient time of the timing gate, the defect indication signal may not be processed. For this reason, in order to solve this problem, conventional devices are configured to open the two timing gates in duplicate, and generally a matching circuit is added to process and determine the number of signals in the duplication section. Not only was this complicated, but production costs were also high.

The present invention has been made in view of the above-mentioned problems, and aims to provide an ultrasonic multiple echo gate circuit that can reliably receive echo signals and obtain accurate measurement results without using a matching circuit or an expensive timing circuit. In response to ultrasonic reception echoes,
It has a basic gate that selectively accepts the range of the echo, holds the signal of the first echo, and at the same time has an arbitrary delay from the falling edge detection of an arbitrary n-th echo within the basic gate. Let n
The present invention provides an ultrasonic multiple echo gate circuit which constitutes circuit means for selecting and retaining multiple echoes by retaining the signal of the +1-th echo.

The configuration and operation of the present invention will be explained below with reference to the drawings. In the drawing, 1 is a synchronous circuit, and a basic gate 2 is connected to the synchronous circuit 1 through a conductor 31, and the basic gate 2 obtains timing from the synchronous circuit 1 and is connected through a conductor 32. At the same time, a first echo sampling start signal is applied to the flip-flop circuit 4 connected via a conductor 33.

On the other hand, the comparator 3 is input with a received echo signal 15 from a detection section (not shown) and a reference level signal 16 which can be set arbitrarily. When the comparator 3 detects that the reference level signal has been crossed during the falling phase, the comparator 3 outputs an echo falling detection output signal 17, which is inputted to the reset terminal of the flip-flop circuit 4 connected via the conductor 34 to output the first echo signal. Reset the sampling signal 18. Each sample/peak hold circuit S/PH ₁ to S/PH _o 7
The received echo signals 15 are connected to the inputs of 1, 72, . . . , 7n via conductors 35, respectively.
First sample/peak hold circuit S/PH ₁ 7
The first echo sampling signal 18 of the flip-flop circuit 4 is applied to the flip-flop circuit 4 through the conductor 36, and the peak value of the first echo is held in the sample/peak hold circuit S/PH ₁ 71 by this input. At the same time, the echo falling detection output signal 17 of the comparator 3 is inputted to the delay and control circuit 5 via the conductor 37, and a delay control is obtained that can arbitrarily delay each time the falling edge of the echo is detected. The timing clock signal 19 is outputted to the counter 6 via a conductor 38. The output of the ring counter 6 is sent to sample/peak hold circuits S/PH ₂ , S/PH ₃ ,...S/PH _o corresponding to the second echo, third echo,... and n-th echo, respectively.
Conductors 392, 393,...39 to 2, 73,...7n
The second, third, ..., and n-th echo sampling signals 20 are output to the respective sample/peak hold circuits 72, 73, . . . 7n, and the peak of the desired n-th echo is Hold the value. Each peak echo value 212, 213,...21n held in the sample/peak hold circuits 72, 73,...7n is connected to the conductor 402,
403, . The data signal 24 is converted into an analog-to-digital signal by . The converted data signal 24 is transferred to a memory circuit or the like that can be provided externally or internally, and performs necessary data processing.

As explained above, according to the configuration of the echo gate circuit of the present invention, the unnecessary received echo signal 15 is removed by the basic gate 2, the basic gate 2 is applied to the necessary range of the ultrasonic test, and the nth echo is A plurality of echoes can be processed by obtaining the (n+1)th echo sampling signal 20 with an arbitrary delay from the falling edge detection.

That is, according to the present invention, not only can multiple echoes be processed without adding special or expensive circuits, but also fine echoes can be processed by reducing the arbitrary delay value by adjusting the delay and control circuit 5. In addition to being able to obtain undulation data, by appropriately increasing the delay value, it becomes possible to perform a kind of masking on the minute echoes seen on the slope at the trailing edge of the echo of a single defect. It has features such as being able to remove complexity. Furthermore, since the echo gate circuit device of the present invention can perform multiple echo processing without using special additional circuits, it can be provided at low production cost. It's large.

[Brief explanation of the drawing]

The drawing is a block diagram showing one embodiment of the ultrasonic multiple echo gate circuit of the present invention. 1: Synchronous circuit, 2: Basic gate, 3: Comparator,
4: Flip-flop circuit, 5: Delay and control circuit, 6: Ring counter, 71, 72,...7n:
Sample/peak hold circuit, 8: Multiplexer, 9: Analog/digital converter, 15: Received echo signal, 16: Reference level signal, 17: Echo fall detection output signal, 18: First echo sampling signal, 19: Timing clock signal,
20: Echo sampling signal, 212, 21
3,...21n: Peak echo value, 22: Switching signal, 23: Conversion command signal, 24: Data signal.

Claims (1)

[Claims] 1. In multiple echo processing of an ultrasonic non-destructive flaw detection device, a basic gate that selects and receives the signal reception range for an ultrasonic received echo signal is compared with the echo in the output signal of the basic gate and a reference level. It includes a comparator that outputs a signal when it crosses the reference level at the time of echo falling, holds the first signal by the above-mentioned basic gate output, and obtains an arbitrary delay from the detection of the n-th echo fall. te n+
An ultrasonic multiple echo gate circuit consisting of a delay and control circuit to obtain the first echo sampling and an n sample peak hold circuit to hold the peak value of each echo sample.