JPS6375913A - Power controller for personal computer - Google Patents

Abstract

PURPOSE:To easily and effectively attain power saving, by supplying power only when it is detected that an operation control signal to operate a prescribed part to be power-saved is supplied to the part. CONSTITUTION:A ROM4 of N-channel is taken up as the object of a circuit part to be power-saved in which a considerable large amount of power is consumed. Before an access signal 6 is supplied to the ROM4, a power source control circuit 3 is controlled by supplying a power source control signal 7 to the power source control circuit 3, and a power source voltage is supplied to the ROM4. When the power source voltage is supplied to the ROM4 under the control of a discrimination circuit 2 through the power source control circuit 3, the discrimination circuit 2 supplies the access signal 6 to the ROM4. After the access signal 6 is supplied to the ROM4, and a bit of information is read out, no more bit of bank information 10 from a system part 1 is present, and when a ROM selection control signal 11 goes to a level O, the supplying of the access signal 6 to the ROM4 is also ceased, and a transistor 23 is turned off, and the supplying of the power source voltage to the ROM4 is stopped.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention aims to reduce power consumption as much as possible in a specific part of a personal computer, for example, a circuit part that consumes relatively large amount of power. The present invention relates to a power control device for a battery-powered personal computer, which controls the supply of power to the section.

(Prior Art) For portable devices such as personal word processors that use batteries as a power source, it is important to reduce the current consumption of the device as much as possible. In particular, personal word processors have become more sophisticated in recent years, with more dictionaries, more fonts, and floppy disk drives, and the current consumption of the devices has increased. In such a situation, in order to reduce the current consumption of the device as much as possible, components with relatively large current consumption, such as N-channel ROM that stores fixed information and programs, should be disconnected from the power supply voltage when not in use. A method of not supplying it is generally taken.

Conventionally, in order to implement such a method, when using a component with a relatively large current consumption, supply control information is provided to control the supply of power supply voltage to the component by a program shortly before the use of the component. When the supply control information is set in the register, the control circuit decodes this information and supplies the power supply voltage to the component.
tel L, and when the use of the part is finished, the program sets the supply stop υ control information to control the stop of supply of the N source voltage to the part in the register, and the above! I
The JI11 circuit performs tif control to stop the supply of power supply voltage to the component.

(Problems to be Solved by the Invention) The conventional method of fi-controlling the supply and stop of supply of power supply voltage to components using a program requires a great deal of effort when designing a program to control the supply/stop of supply of power supply voltage to the component. Since careful design is required, the design process is very time-consuming, and there is a problem that each time there is a change in the program, the design of the program for supplying/stopping the power supply voltage may also be changed. In addition, if the component is used frequently in a relatively short period of time, the power supply voltage will be continuously supplied to the component during the period, so power can be efficiently saved. The problem is that it cannot be done.

This invention has been made in view of the above, and its purpose is to reduce power consumption for personal computers that can easily and efficiently save power. I
The goal is to provide equipment.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, in a personal computer having a battery as a power source, the present invention provides a method for supplying power to a predetermined part where power is to be saved and a power switch means for stopping supply; a detection means for detecting that an operation control signal for operating the section is supplied to the section; and the detection means detects supply of the operation control signal to the section. and a control means for operating the power switch means so as to supply power to the portion only when the power switch is activated.

(Function) The personal computer power control m5Aw of the present invention supplies power to a predetermined part of the personal computer only when it detects that an operation control signal for operating a predetermined part to save power is supplied to the part. The section is operated by actuating a power switch means that supplies power from a barrel battery.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit block diagram of a mold IIJIII device for a personal computer according to an embodiment of the present invention.

The power control device shown in the figure is applied to, for example, a portable personal word processor that operates on battery power.
The N-channel ROM 4 is selected as a circuit part to save power because it consumes a relatively large amount of power in the word processor, and the supply and stop of supply of power supply voltage to the ROM 4 are controlled according to its use. In the figure, reference numeral 1 denotes the basic system section of the personal word processor, which is comprised of, for example, a microprocessor, RAM, and the like. The ROM 4 is provided as a memory for storing fixed information, programs, etc. of the basic system section 1. The ROM 4 has an address space coexisting with the memory in the basic system section 1, and is configured to be selected by the value of a bank register existing in the basic system fS1. A discrimination circuit 2 is connected between the basic system section 1 and the ROM 4, and bank information 10, which is an operation control signal for controlling the operation of the ROM 4 so that the basic system section 1 reads stored information from the ROM 4, is supplied to the discrimination circuit 2. ing. Further, the basic system unit 1 is supplied with operating power supply voltage from a battery power supply (not shown) via a system power line 8, and this power supply voltage is supplied to the ROM via a power supply control circuit 3.
The power is supplied to the ROM 4 through the power line 9. When the discrimination circuit 2 receives this bank information 10, before accessing the ROM 4, that is, before supplying the access signal 6 to the ROM 4, it supplies the power supply control signal @7 to the power supply υJilt circuit 3 to control the power supply control circuit 3. It controls and supplies power supply voltage to ROM4.

When the power supply voltage is supplied to the ROM 4 via the power supply tllt1 circuit 3 under the control of the discrimination circuit 2, the discrimination circuit 2 supplies the access signal 6 to the ROM 4. Note that, at the same time that this access signal 6 is supplied to the ROM 4, address information is supplied to the ROM 4 from the discrimination circuit 2 via the system bus 5. Further, a bus 5' for supplying information read from the ROM 4 is also connected from the discrimination circuit 2 to the basic system unit 1.

FIG. 2 is a detailed circuit diagram of the discrimination circuit 2 and power supply control circuit 3 shown in FIG. 1.

This discrimination circuit 2 receives from the basic system unit 1 a memory request signal MREQ and a clock signal CLK in addition to the bank information 10 . The bank information 10 is combined by an AND circuit 15 via an exclusive OR 13 and is supplied to the inputs of a NAND circuit 17 and a NAND circuit 21 as a ROM selection control signal 11 which is a ROM operation control signal.

The other input of the NAND circuit 17 receives the memory request signal MRE.
Q is being supplied, and when both the ROM selection control signal 11 and memory request signal MREQ become logic levels in the NAND circuit 17, the NAND circuit 17 becomes low level.

The low level output signal of the command circuit 17 is supplied to the base of the switching transistor 23 constituting the power switch of the NH control circuit 3 via the resistor 25, and turns on the transistor 23. Further, when the NAND circuit 17 is at the logic O level, the transistor 23 remains in the off state. Note that a resistor 27 is connected between the base and emitter of the transistor 23.

On the other hand, the memory request signal MREQ is supplied to the data input of the D-type flip-flop 19, latched by the clock signal CLK, and supplied to the input of the AND circuit 21. The AND circuit 21 also has a memory request signal MR at its input.
The AND circuit 21 is configured to output a low level signal to the ROM 4 as the access signal 6 when the EQ is supplied and the input power supplied to the AND circuit 21 becomes a logic level.

Next, the operation will be explained with reference to the tamping chart shown in FIG.

First, bank information 1 is sent from the basic system unit 1 to the discrimination circuit 2.
In a state in which 0 is not supplied, that is, in a state in which the ROM 4 is not used or not intended to be used, the ROM selection υIm signal 11 from the AND circuit 15 is at a logic 0 level, and the output of the NAND circuit 17 is at a high level. Therefore, since the transistor 23 of the power supply control circuit 3 is not turned on, the power supply voltage is not supplied to the ROM 4 via the transistor 23. Therefore, even if the memory request signal MREQ becomes level as shown in FIG. 3 during this period, no power supply voltage is supplied to the ROM 4.

When the bank information 10 is supplied from the basic system section 1 to the discrimination circuit 2, the ROM selection control signal 11 is output from the AND circuit 15, and the memory request signal MREQ is also supplied at this time, the output of the NAND circuit 17 is at a low level. This low level output signal turns on the transistor 23 of the power supply v control circuit 3. As a result, voltage from a battery power source (not shown) is supplied to the ROM 4 from the system power line 8 via the transistor 23 and further via the ROM power line 9.
ROM4 becomes operational. On the other hand, at this time the ROM
The m-selection control signal 11 is supplied to the AND circuit 21, and when the memory request signal MREQ and the search signal CLK are also supplied to the AND circuit 21 via the D-type flip-flop O-tub 19, the access signal 6 is output from the AND circuit 21. Output.

This access signal 6 is then supplied to the ROM 4 and R
Information is read from OM4. Like this R
The transistor 23 of the power supply control circuit 3 is turned on and power supply voltage is supplied to the OM4 only when the basic system unit 1 attempts to access it.

After the access signal 6 is supplied to the ROM 4 and the information is read out, the bank information 10 from the basic system section 1 disappears and the ROM selection control signal 11 goes to 0 level.
The access signal @6 is no longer supplied to the OM 4, the transistor 23 is turned off, and the supply of power supply voltage to the ROM 4 is stopped.

Note that when controlling the supply/stop of power supply voltage to other components that consume large current, a slight delay may be necessary after turning on the transistor 23 of the power switch to supply the power supply voltage. However, in such a case, a delay circuit may be provided in the discrimination circuit 2.

Further, although the above embodiment describes a personal word processor, it is not limited to this, and can be applied to all personal devices that use a microcomputer, etc., and can be applied to all personal computers. The portion that does this is not limited to the ROM.

[Effects of the Invention] As explained above, according to the present invention, operation 1 for operating a predetermined part for which power saving is to be performed (the operation to the part is performed only when it is detected that the Jtl signal is supplied to the part) Since the power switch that supplies power from the battery, which is the power source of the personal computer, is activated to operate the part, the power for the part with relatively large power consumption can be appropriately and efficiently supplied without considering the software operation. can be supplied and stopped.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a power control device for a personal computer according to an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the device shown in FIG. 1, and FIG. 3 is a timing chart of the device shown in FIG. be. 2... Discrimination circuit 3... Power supply control circuit 23.
・Transistor

Claims (1)

[Claims] In a personal computer having a battery as a power source, a power switch means for supplying and stopping the supply of electric power from the battery to a predetermined part whose power is to be saved is supplied to the part, and an operation control signal for operating the part is supplied to the part. and control means for operating the power switch means to supply power to the section only when the detection means detects supply of the operation control signal to the section. A power control device for a personal computer characterized by the following.