KR100481847B1 - Computer system having power management function - Google Patents

Abstract

The disclosed computer system includes a power management control unit that performs power management according to ACPI, and the power management control unit controls the power reduction step by step according to the state of the computer system. The power plan of the volatile memory included in the computer system is designed independently of other hardware devices and is provided with a switching circuit accordingly. The switching circuit is controlled by the power management controller, and supplies one of the main power and the standby power provided from the power supply circuit to the volatile memory.

Description

Computer system with power management function {COMPUTER SYSTEM HAVING POWER MANAGEMENT FUNCTION}

The present invention relates to a computer system, and more particularly to a computer system having a power management function for reducing power consumption.

In recent decades, semiconductor technology has advanced a lot. With the development of semiconductor technology, the performance of computer systems and peripherals has been rapidly developed. As computer system performance increases, so does power consumption. As a result, efforts are being focused in the industry to reduce the power consumption of computer systems. For example, if there is no data input from the input device for a certain time, the display operation of the display device is stopped, and if the hard disk drive is not accessed for a certain time, the operation of the hard disk drive is stopped. Power management minimizes the power consumption of computer systems.

These power management features are well known and are known as "Advanced Power Management" with improved power management from "Power Management System" with earlier simple power management. It has been improved and applied to computer systems. Recently, Advanced Configuration and Power Interface Specification (ACPI) has been proposed by Intel Corporation, Microsoft Corporation, and Toshiba Corporation. Details of ACPI are described in Advanced Configuration and Power Interface Specification Revision 1.0. According to ACPI, the operating state of a computer system is divided into several stages, and power consumption of hardware devices selected at each stage is reduced.

1 is a state diagram showing the system state and its transitions according to ACPI. As shown in FIG. 1, the overall system state of a computer system is largely divided into five states: a legacy state 20, a GO state 40, a G1 state 50, a G2 state 30, and a G3 state 10. to be. The legacy state 20 is a state in which the ACPI function is disabled and power management is not performed. The G3 state 10 is a mechanical off state in which power supply to the system is cut off. The G2 state 30 is a soft off state in which only minimal power consumption for detecting a soft switch occurs. The G0 state 40 is a working state in which the computer system normally operates. The G1 state 50 is a sleeping state in which power consumption is reduced in stages.

Again, the computer system is divided into six levels of sleeping state. The S0 state corresponds to the G0 40, the S1 to S4 states 50a to 50d correspond to the G1 state 50, and the S5 state corresponds to the G2 state 30, respectively. In the S1 to S4 states 50a to 50d, the power decreases step by step according to the operating state of the computer system. In particular, in the step S3 state 50c, a system context is stored in a volatile memory, and power supplied to other hardware devices except power supplied to the volatile memory is cut off. This operation is commonly referred to as SUSPEND_TO_RAM. In the S4 state 50d, the system context is stored in a non-volatile memory, and power to all hardware devices of the system is cut off. This state is commonly referred to as SUSPEND_TO_DISK. In the case of the S4 state 50d, the power supply state is the same as that of the G2 state 30.

As described above, ACPI is gradually applied to computer systems, and the computer system needs to have a power plane appropriately. In particular, the conventional computer system has a problem that the power plan of the volatile memory is not designed independently of the power plan of other hardware devices, so that the effective power reduction is not achieved in the step S3.

Accordingly, an object of the present invention is to provide a computer system that effectively reduces the power consumption of a memory in a computer system as proposed to solve the above-mentioned problems.

According to an aspect of the present invention for achieving the object of the present invention as described above, a computer system having a power management function having a normal operation mode and a power consumption reduction mode: supplying main power in the normal operation mode, A power supply circuit for supplying standby power in the power reduction mode; A power management control unit performing a multi-level power management function according to the normal operation mode and the power consumption reduction mode; A memory subsystem comprising a volatile memory and a memory controller for controlling the operation of the volatile memory; A power supply circuit and a switching circuit configured to supply power to the memory subsystem under control of the power management controller, the switching circuit comprising: (a) the A first power input for inputting / blocking the main power to a memory subsystem; (b) a second power input for inputting / blocking said standby power to said memory subsystem; (c) a switching controller for controlling a switching operation of the first and second power input units under the control of the power management controller.

In this embodiment, the first power input unit includes a transistor configured to switch under the control of the switching controller to supply / block the main power to the memory subsystem.

In this embodiment, the second power input unit includes: a regulator for inputting the standby power supply and outputting the standby power supply having a predetermined voltage level; And a transistor configured to perform a switching operation under the control of the switching controller to supply / block standby power output from the regulator to the memory system.

In this embodiment, the switching controller includes: a first transistor for controlling a switching operation of the first power input unit; A second transistor for controlling a switching operation of the second power input unit; A control unit configured to control on / off operations of the first and second transistors by being turned on and off in accordance with a predetermined control signal provided from the power management control unit and a predetermined signal output by the power supply circuit in a normal power supply state. Third and fourth transistors.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The novel computer system of the present invention includes a power management control unit for performing power management according to ACPI, and the power management control unit controls power reduction step by step according to the state of the computer system. In particular, the power plan of the volatile memory is designed independently of other hardware devices and is provided with a switching circuit accordingly. The switching circuit is controlled by the power management controller, and selectively supplies one of the main power and the standby power provided from the power supply circuit to the volatile memory.

2 is a block diagram showing a circuit configuration of a part related to a memory subsystem and a power supply circuit in a computer system according to a preferred embodiment of the present invention. Referring to FIG. 2, a computer system according to a preferred embodiment of the present invention includes a power supply circuit 100, a switching circuit 200, a power management controller 300, a memory subsystem 400, a soft switch 500 and Although not shown, functional circuits of the computer system are included.

The power supply circuit 100 is a switchable power supply circuit and supplies a plurality of powers having various voltage levels provided to the system. Although not shown, the power supply circuit 100 includes a separate linear regulator for the power management control unit 300, and thus supplies power to the power management control unit 300 whenever external power is supplied. This is indicated by reference numeral 101. Therefore, the power management control unit 300 operates continuously except when the external power supply is not blocked. This is commonly known as well.

The power management controller 300 controls the power supply circuit 100 and the switching circuit 200 to perform power supply control based on ACPI. The power supply control of the power management control unit 300 is based on the state information 600 of the system and the input of the resume event 700. The system state information 600 is information on a system operating state based on ACPI, and is preferably provided from a BIOS supporting ACPI.

Referring to FIG. 1, the resume event 600 is interrupt signals indicating that the computer system should return to the normal state from the sleeping state G1 50. For example, in the G1 state 50, an interrupt corresponding to an input of a keyboard device or an input from an external input / output port is generated and input to the power management controller 700. Then, the power management controller 300 controls the power supply circuit and the switching circuit 200 to return the system to the working state, that is, the G0 state 40.

The power management controller 300 detects an input of the soft switch 500 and controls a power supply operation corresponding thereto. The user can use the soft switch 500 to turn on / off the system or to enter the power saving mode. When the system is operating normally, when the soft switch 500 is briefly clicked within a predetermined time, the system enters a power saving mode. Preferably, the S4 state 50d of the G1 state 50, which is a sleeping state, is entered. Enter In this case the system context is stored on a hard disk which is a nonvolatile memory. This operation is performed by the power management controller 600 detecting an input of the soft switch and generating a system management interrupt (SMI) 800 corresponding thereto. SMI 800 is input to a CPU (not shown), so that the system context is stored in a specific area of the hard disk. When the system is operating normally, when the soft switch 500 is clicked for more than a predetermined time, the computer system enters the G2 state 30 which is in a soft off state.

As described above, the power management control unit 300 controls the power supply according to the state of the system, and outputs control signals SUSA *, SUSB *, and SUSC * for controlling the power supply. The SUSA * signal transitions to G0 state 40 where the system is in working state, the SUSB * signal transitions to S3 state 50c where the system is in SUSPEND_TO_RAM state, and the SUSC * signal transitions to G2 state 30 where the system is in soft off state. Are the signals that are output.

The memory subsystem 400 is comprised of a memory controller 410 and a memory 420. The memory 420 is a volatile memory and includes dynamic random access memory (DRAM), synchronous DRAM (SDRAM), and the like. The switching circuit 200 operates under the control of the power management controller 300, and receives the main power supplies Vmain1 and Vmain2 and the standby power supply Vsb1 output from the power supply circuit 100. Input the power of). The switching circuit 200 will be described in detail with reference to FIGS. 3 to 5.

3 is a block diagram illustrating a circuit configuration of the switching circuit illustrated in FIG. 2. Referring to FIG. 3, the switching circuit 200 is largely comprised of a first power input unit 210, a second power input unit 220, and a switching controller 230. The memory subsystem 400 receives power through the first power input unit 210 when the computer system is in the G0 state 40, and when the computer system transitions to the S3 state 50c of the G1 state 50. Power is received through the second power input unit 220. The switching controller 230 inputs control signals SUSB * and SUSC * provided from the power management controller 300 and a POWERGOOD signal provided from the power supply circuit 100 to the first and second power input units ( The switching operations of 210 and 220 are controlled. The POWERGOOD signal is a signal that is output when the power supply circuit 100 supplies power stably.

When the system is in the G0 state 40, the main power supply Vmain1 is supplied from the power supply circuit 100 to the memory subsystem 400 through the first power input unit 210. After a predetermined time has elapsed without the user using the system, the system transitions to the S3 state 50c, and the standby power supply Vsb1 is converted to a predetermined voltage level through the second power input unit 220 so that the memory subsystem 400 Is provided. Alternatively, the same operation is performed when a specific sleep switch provided in the system is inputted to transition to the S3 state 50c.

At this time, the power management controller 300 provides the memory controller 410 with a signal SUS_STATUS * (suspend status signal) indicating that the system transitions to the S3 state 50c. Accordingly, the memory controller 410 controls the memory 420 to operate in a self refresh mode. Therefore, after the system transitions to the S3 state 50c, the context of the system and the data currently in operation are preserved in the memory 420. When the user enters a resume switch (commonly used with the sleep switch) or when a resume event 700 occurs by an external input, the system transitions to the G0 state 40 (the time taken is within a few seconds). )do.

More specifically, the detailed configuration and operation of the switching circuit 200 will be described with reference to FIG. 4. 4 shows a detailed circuit diagram of the switching circuit shown in FIG. 2.

Referring to FIG. 4, the first power input unit 210 includes a MOS transistor Q7. From the power supply circuit 100, the main power supply Vmain1 is input to the MOS transistor Q7, and when the MOS transistor Q7 is turned on, the main power supply Vmain1 is input to the memory subsystem 400.

The second power input unit 220 includes a regulator 221, capacitors C1, C2, C3, C4 and C5, voltage divider R1, R2, and a MOS transistor Q1. The regulator 221 converts the standby power supply Vsb1 provided from the power supply circuit 100 into a standby power supply Vsb2 having a predetermined voltage level and outputs the same. The standby power supply Vsb2 is not shown but can be supplied to other circuits in the system. The standby power supplies Vsb1 and Vsb2 are preferably 5V and 3V, respectively. The standby power supply Vsb2 output from the regulator 221 is input to the MOS transistor Q1 via a smoothing circuit composed of capacitors C3, C4, and C5. When the MOS transistor Q1 is turned on, the standby power supply Vsb2 is input to the memory subsystem 400.

The switching controller 230 includes MOS transistors Q2, Q3, Q4, Q5, and Q6, resistors R3, R4, R5, R6, and R7, and divided resistors R8, R9, and R10. The switching controller 230 turns on / off the MOS transistors Q1 and Q7 under the control of the power management controller 300 according to the state of the system.

The first and second power input units 210 and 220 and the switching controller 230 configured as described above are supplied from the control signals SUSB *, SUSC * and the power supply circuit 100 provided from the power management controller 300. It is operated by POWERGOOD signal. 5 is a diagram illustrating a table showing voltage levels of main signals output from the power supply circuit 100 and the power management controller 300 for each power supply state of a computer system.

4 and 5, in the GO state 40 in which the computer system is in a working state, the SUSB * may be inactive high and the POWERGOOD signal may be kept in an active high state so that the MOS transistors Q2 and Q3 are maintained. The gate voltages of the MOS transistors Q4 and Q6 are turned low. Therefore, the MOS transistors Q6 and Q4 are also turned off. Thus, the MOS transistor Q6 is turned off, so that the gate of the MOS transistor Q7 is turned high by the divided resistors R8, R9, and R10, and the MOS transistor Q7 is turned on, so that the main power supply Vmain1 is supplied to the memory subsystem 400. In addition, the gate voltage of the MOS transistor Q1 remains high and is turned off so that the standby power supply Vsb2 is not supplied to the memory subsystem 400. The SUSC * signal remains in an active high state, turning the MOS transistor Q5 on.

When the computer system enters the SUSPEND_TO_RAM, i.e., the S3 state 50c, the SUSB * is in an active low state, whereby the main power supplies Vmain1 and Vmain2 output from the power supply circuit 100 are turned off, and the POWERGOOD signal is also in an active low state. It becomes a state. The MOS transistors Q2 and Q3 are also turned off by the SUSB * and POWERGOOD signals. As a result, the gate voltages of the MOS transistors Q4 and Q6 become high. When the MOS transistor Q6 is turned on, the gate voltage of the MOS transistor Q7 goes low and turns off. Since the SUSC * signal is high in the SUSPEND_TO_RAM state, the MOS transistors Q4 and Q5 are turned on so that the gate voltage of the MOS transistor Q1 is turned low, and the standby power supply Vsb2 is supplied to the memory subsystem 400. As such, power is supplied to the memory subsystem 400 by the standby power supply Vsb1 provided from the power supply circuit 100 in the SUSPEND_TO_RAM state.

When the computer system is in the soft off state G2 (30), the SUSB *, POWERGOOD, and SUSC * signals all remain low, with the MOS transistors Q2 and Q3 turned off, the MOS transistor Q6 turned on, and the MOS transistor Q7 turned off. State, the MOS transistor Q4 is turned on. However, the MOS transistor Q5 is turned off so that the gate voltage of the MOS transistor Q1 remains high. Therefore, no power is supplied to the memory subsystem 400 in the soft off state G2 (30).

According to the present invention as described above, since the power plan of the memory subsystem is configured independently of other hardware devices, effective power reduction is achieved in the SUSPEND_TO_RAM state. In particular, the configuration of the switching circuit is simple, there is an effect that can reduce the production cost.

1 is a state diagram showing states and transitions of each state of a computer system in accordance with ACPI;

2 is a block diagram showing a circuit configuration of a part related to a memory subsystem and a power supply circuit in a computer system according to a preferred embodiment of the present invention;

3 is a block diagram showing a circuit configuration of the switching circuit shown in FIG.

4 is a detailed circuit diagram of the switching circuit shown in FIG. 2; And

FIG. 5 is a table showing voltage levels of main signals output from a power supply circuit and a power management controller for each power supply state of a computer system.

* Description of the symbols for the main parts of the drawings *

100: power supply circuit 200: switching circuit

300: power management control unit 400: memory subsystem

500: soft switching 600: reset event

700: system status information

Claims (4)

In a computer system having a power management function having a normal operation mode and a power consumption reduction mode: A power supply circuit for supplying main power in the normal operation mode and supplying standby power in the power reduction mode; A power management control unit performing a multi-level power management function according to the normal operation mode and the power consumption reduction mode; A memory subsystem comprising a volatile memory and a memory controller for controlling the operation of the volatile memory; A switching circuit configured in a power supply path to the power supply circuit and the memory subsystem, the switching circuit for inputting power to the memory subsystem under the control of the power management controller; The switching circuit is: (a) a first power input for inputting / blocking said main power to said memory subsystem; (b) a second power input for inputting / blocking said standby power to said memory subsystem; (c) a switching control unit for controlling a switching operation of the first and second power input units under the control of the power management control unit. The method of claim 1, The first power input unit And a transistor configured to switch under the control of the switching controller to supply / block the main power to the memory subsystem. The method of claim 1, The second power input unit: A regulator 221 for inputting the standby power and outputting the standby power to a standby power supply having a predetermined voltage level; And a transistor (Q1) for switching / operating a standby power output from the regulator under the control of the switching control unit to the memory system. The method of claim 1 The switching control unit A first transistor (Q6) for controlling a switching operation of the first power input unit; A second transistor Q4 for controlling a switching operation of the second power input unit; The first and second transistors Q6 are turned on and off in accordance with a predetermined control signal SUSB * provided from the power management controller and a predetermined signal POWERGOOD output by the power supply circuit in a normal power supply state. And third and fourth transistors (Q2, Q3) for controlling the on / off operation of Q4).