JPS6358817A - Composite semiconductor crystal structure - Google Patents

Composite semiconductor crystal structure

Info

Publication number
JPS6358817A
JPS6358817A JP20124786A JP20124786A JPS6358817A JP S6358817 A JPS6358817 A JP S6358817A JP 20124786 A JP20124786 A JP 20124786A JP 20124786 A JP20124786 A JP 20124786A JP S6358817 A JPS6358817 A JP S6358817A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
etched
insulating film
composite
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20124786A
Other languages
Japanese (ja)
Inventor
Koichi Kitahara
北原 広一
Tamotsu Ohata
大畑 有
Yosuke Takagi
洋介 高木
Takeshi Kuramoto
倉本 毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20124786A priority Critical patent/JPS6358817A/en
Publication of JPS6358817A publication Critical patent/JPS6358817A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the structure with which a composite semiconductor device is integrated easily by a method wherein the element regions, which are left by performing selective etching on a semiconductor substrate, are completely element- isolated with each other using a junction insulating film and the insulating film formed on the etched part. CONSTITUTION:The surface on the side of the first semiconductor substrate 16 of a composite substrate 19 is etched until a junction oxide film is exposed leaving an element region 16a. Besides, another etching operation is performed as far as to the inside part of the second semiconductor substrate 17, and after a thermally oxided film has been formed on the etched surface, the thermally oxided film is selectively etched, and the thermally oxided film 21, whereon the desired second semiconductor substrate surface and the like are exposed, is formed. Subsequently, when N<-> type silicon has been vapor-grown on the etched surface, an epitaxial layer 22 is formed on the surface of the silicon single crystal and, at the same time, a polycrystalline silicon layer 23 is formed on the thermally oxided film 21. Accordingly, as each element can be isolated completely by the junction insulating film and the insulating material of the insulating film formed on the etched part, the degree of restrictions placed on the inverse vias of the constitution of circuits is small.

Description

【発明の詳細な説明】 1発明の目的] (産業上の利用分野) 本発明は、複合半導体結晶体構造に関するもので、特に
素子分離を必要とする複数個の機能素子を1!積する複
合半導体装置の基板に使用されるものである。
DETAILED DESCRIPTION OF THE INVENTION 1. Object of the Invention] (Industrial Application Field) The present invention relates to a composite semiconductor crystal structure, and in particular, the present invention relates to a composite semiconductor crystal structure, in which a plurality of functional elements that require element isolation can be integrated into one! It is used for the substrate of multi-layered composite semiconductor devices.

(従来の技術) 1つの基板に複数個の能動素子又は受動素子を集積する
複合半導体装置では、素子相互を電気的に分離する必要
がある。 これに用いられる主要な素子間分離法には逆
バイアスされたPN接合によるもの或いは絶縁体による
ものがある。 第3図にPN接合による接合分離法の1
例を示す。
(Prior Art) In a composite semiconductor device in which a plurality of active elements or passive elements are integrated on one substrate, it is necessary to electrically isolate the elements from each other. The main device isolation methods used for this purpose include those using reverse biased PN junctions and those using insulators. Figure 3 shows 1 of the junction isolation method using PN junction.
Give an example.

複数のN型半導体の素子領域4は、P型の半導体基板1
、素子分離領域3とN型の素子領域4とのPN接合に逆
バイアスを印加することによって、他のN型領域2とは
空乏層を介して電気的に分離される。 この方法は安価
ではあるが、逆バイアス電位を与える回路構成上の制約
があり、またPN接合のもれ電流が特性上の欠点になる
。 第4図に絶縁体による素子分離法の従来例を示1゜
複数のN型半導体の素子領域5は酸化シリコン膜6及び
多結晶シリコン層7により分離保持された島領域を形成
している。 この方式は前記PN接合分離に必要な逆バ
イアス回路が不要であり、また寄生素子による制約が少
ない等の利点がある。
A plurality of N-type semiconductor element regions 4 are connected to a P-type semiconductor substrate 1.
By applying a reverse bias to the PN junction between the element isolation region 3 and the N-type element region 4, it is electrically isolated from other N-type regions 2 via the depletion layer. Although this method is inexpensive, there are restrictions on the circuit configuration for providing a reverse bias potential, and the leakage current of the PN junction is a drawback in terms of characteristics. FIG. 4 shows a conventional example of the device isolation method using an insulator. A plurality of N-type semiconductor device regions 5 form island regions separated and held by a silicon oxide film 6 and a polycrystalline silicon layer 7. This method has advantages such as not requiring the reverse bias circuit required for the PN junction separation, and having fewer restrictions due to parasitic elements.

しかしこの方式では基板に相当するものを多結晶シリコ
ン層7で構成する形態となるので、非常に厚い多結晶シ
リコンを堆積する工程が必要となり経済的に不利である
。 またこの多結晶シリコン層7の一面は酸化シリコン
膜6で絶縁されているため、この基板としての多結晶シ
リコン層7を電流回路として使用することができないと
いう不利が釣る。
However, in this method, what corresponds to the substrate is composed of the polycrystalline silicon layer 7, which requires a step of depositing very thick polycrystalline silicon, which is economically disadvantageous. Furthermore, since one surface of the polycrystalline silicon layer 7 is insulated by the silicon oxide film 6, there is a disadvantage that the polycrystalline silicon layer 7 serving as a substrate cannot be used as a current circuit.

(発明が解決しようとする問題点) 本発明の目的は前記問題点を解決し、複合半導体装置を
容易に集積できる新規な構造の複合半導体結晶体を提供
することである。
(Problems to be Solved by the Invention) An object of the present invention is to solve the above-mentioned problems and provide a composite semiconductor crystal body with a novel structure that allows easy integration of composite semiconductor devices.

[発明の構成] (問題点を解決する手段と作用〉 本発明は第1半導体基板の1つの主面と第2半導体基板
の1つの主面とを絶縁膜を介して鏡面接合してなる複合
基板と、この複合基板の第1半導体基板及び接合絶縁膜
に選択的蝕刻をして設けた少なくとも一部で第2半導体
基板に達する蝕刻部と、この蝕刻部のいくつかに形成さ
れた絶縁膜と、この蝕刻部の第2半導体基板上に設けた
エピタキシャル層と、このエピタキシャル層と同時に前
記蝕刻部に形成された絶縁膜上に設けた多結晶シリコン
層とを具備することを特徴とする複合半導体結晶体であ
る。
[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a composite structure in which one main surface of a first semiconductor substrate and one main surface of a second semiconductor substrate are mirror-joined via an insulating film. a substrate, a first semiconductor substrate and a bonding insulating film of the composite substrate are selectively etched, and at least a portion of the etched portions reach the second semiconductor substrate; and an insulating film formed on some of the etched portions. an epitaxial layer provided on a second semiconductor substrate in the etched portion; and a polycrystalline silicon layer provided on an insulating film formed in the etched portion at the same time as the epitaxial layer. It is a semiconductor crystal.

本発明の複合半導体結晶体においては、第1半導体基板
を選択蝕刻して残された各素子領域は、蝕刻によって残
された接合絶縁膜と蝕刻部に形成された絶it膜とによ
って相互に完全に素子分離され、また第2半導体基板上
に設けたエピタキシャル層における素子領域に対しても
素子分離される。
In the composite semiconductor crystal of the present invention, each element region left after selectively etching the first semiconductor substrate is completely interconnected by the bonding insulating film left by etching and the insulating film formed in the etched portion. The elements are isolated from each other, and the elements are also isolated from the element regions in the epitaxial layer provided on the second semiconductor substrate.

第2半導体基板とそれに接続するエピタキシャル層には
、第1半導体基板から形成される素子領域とは独立に任
意の層厚と不純物濃度を調整して耐圧特性の異なるパワ
ー素子などの形成が可能であり、エピタキシャル層と同
時に絶縁膜上に堆積する多結晶シリコン層はX!i縁膜
溝部の充填などに利用することができる。
In the second semiconductor substrate and the epitaxial layer connected thereto, it is possible to form power elements with different breakdown voltage characteristics by adjusting the arbitrary layer thickness and impurity concentration independently of the element region formed from the first semiconductor substrate. Yes, the polycrystalline silicon layer deposited on the insulating film at the same time as the epitaxial layer is X! It can be used for filling the membranous groove.

(実施例) 第1図(e)は本発明の複合半導体結晶体の実施例の断
面図を示すとともに、第1図(a )ないしくe)はこ
の実施例結晶体の製造工程の主要部を示すものである。
(Example) FIG. 1(e) shows a cross-sectional view of an example of the composite semiconductor crystal of the present invention, and FIG. 1(a) to e) show the main parts of the manufacturing process of this example crystal. This shows that.

まず、第1図(a )に示すN型シリコンの第1半導体
基板16の被接合面(図の下面)とN1型シリコンの第
2半導体基板17の被接合面(図の上面)に、それぞれ
熱酸化膜18a、18bを約1μm程度形成する。 次
に第1及び第2の半導体基板に形成した熱酸化膜面18
a、18bを鏡面研磨し、充分清浄な雰囲気下で第1半
導体基板16と第2半導体塁板17の鏡面相互を密着し
熱処理することにより、第1図(b)に示すように接合
酸化膜18を介して強固に鏡面接合した複合基板19が
得られる。 次に、この複合基板19の第1半導体基板
16側の面を研磨し第1半導体基板16の厚さを例えば
100μm程度にした後、この面に選択的に公知の写真
食刻工程を施して、第1図(C)に示すように、素子領
域16aを残して第1半導体基板16を接合酸化膜18
が露出するまで食刻する。 次に第1図(d )に示す
ように露出した接合酸化膜18を除去し、さらに第2半
導体基板17の内部まで食刻し、蝕刻面に熱酸化膜をつ
けた後選択的にエツチングして、所望の第2半導体基板
面などが露出した熱酸化膜21を形成する。 このあと
蝕刻面にN−型シリコンを気相成長させるとシリコン単
結晶表面上にはエピタキシャル層22が形成され、同時
に熱酸化膜21の上には多結晶シリコン層23が形成さ
れる。
First, the bonded surface (bottom surface of the figure) of the first semiconductor substrate 16 of N-type silicon and the bonded surface (top surface of the figure) of the second semiconductor substrate 17 of N1-type silicon shown in FIG. Thermal oxide films 18a and 18b are formed to a thickness of about 1 μm. Next, the thermal oxide film surface 18 formed on the first and second semiconductor substrates
A and 18b are polished to a mirror surface, and the mirror surfaces of the first semiconductor substrate 16 and the second semiconductor base plate 17 are brought into close contact with each other in a sufficiently clean atmosphere and heat treated to form a bonding oxide film as shown in FIG. 1(b). A composite substrate 19 is obtained which is strongly mirror bonded via the substrate 18. Next, after polishing the surface of this composite substrate 19 on the first semiconductor substrate 16 side to make the thickness of the first semiconductor substrate 16, for example, about 100 μm, this surface is selectively subjected to a known photolithography process. , as shown in FIG. 1C, the first semiconductor substrate 16 is covered with a junction oxide film 18, leaving the element region 16a.
Etch until exposed. Next, as shown in FIG. 1(d), the exposed junction oxide film 18 is removed, and the inside of the second semiconductor substrate 17 is etched. A thermal oxide film is applied to the etched surface, and then selectively etched. Then, a thermal oxide film 21 is formed in which a desired second semiconductor substrate surface and the like are exposed. Thereafter, when N- type silicon is grown in vapor phase on the etched surface, an epitaxial layer 22 is formed on the silicon single crystal surface, and at the same time, a polycrystalline silicon layer 23 is formed on the thermal oxide film 21.

この後、第1半導体基板16、エピタキシャル層22、
多結晶シリコン層23を研磨すると第1図(e)の複合
半導体結晶体が得られる。
After this, the first semiconductor substrate 16, the epitaxial layer 22,
When the polycrystalline silicon layer 23 is polished, the composite semiconductor crystal shown in FIG. 1(e) is obtained.

第1図(e)に示した実施例は、エピタキシャル層に高
耐圧のパワー素子を形成するために第1半導体基扱16
におけるものよりエピタキシャル層22の厚さを厚(し
たが、エピタキシャル層22の領域に例えば比較的低耐
圧大電流のパワー素子を形成する場合などには、第2図
に示すようにエピタキシャル層22aの厚さと第1半導
体基板16からのものの厚さを同じにする。
The embodiment shown in FIG.
The thickness of the epitaxial layer 22 is thicker than that shown in FIG. The thickness is the same as that from the first semiconductor substrate 16.

[発明の効果] 本発明の複合半導体結晶体構造においては、各素子は接
合絶縁膜及び蝕刻部に形成した絶縁膜の絶縁体により完
全に分離できるため、逆バイアスにかかる回路構成上の
制約を受けることが少ない。
[Effects of the Invention] In the composite semiconductor crystal structure of the present invention, each element can be completely separated by the insulator of the junction insulating film and the insulating film formed in the etched portion, so that restrictions on circuit configuration related to reverse bias can be avoided. I rarely receive it.

また第1半導体基板部分からなる素子領域と第2半導体
基板とエピタキシャル層とのそれぞれの層厚及び不純物
濃度は任意に調整できるのでこれらに適当な差を持たせ
て耐圧特性が異なる機能素子を1つの複合半導体結晶体
に形成することが構造上可能である。 また機能素子と
してパワー素子を形成した際には、この複合半導体結晶
体の第2半導体基板側裏面をその電流通路として有効利
用できるため好都合である。
In addition, since the layer thicknesses and impurity concentrations of the device region consisting of the first semiconductor substrate portion, the second semiconductor substrate, and the epitaxial layer can be adjusted arbitrarily, functional elements with different breakdown voltage characteristics can be formed by creating appropriate differences in these. It is structurally possible to form one composite semiconductor crystal. Furthermore, when a power element is formed as a functional element, it is convenient because the back surface of the composite semiconductor crystal on the second semiconductor substrate side can be effectively used as a current path.

【図面の簡単な説明】[Brief explanation of drawings]

第1図<a )ないし第1図(0)は本発明の一実施例
にかかる複合半導体結晶体の製造工程を示す断面図(な
お、第1図(e )は該−実施例にかかる複合半導体結
晶体の構造を示す)、第2図は本発明の複合半導体結晶
体の別の実施例を示す断面図、第3図は従来のPN接合
による接合分離法素子の断面図、第4図は従来の絶縁体
による絶縁層分離法素子の断面図である。 16・・・第1半導体基板、 17・・・第2半導体基
板、 18・・・接合絶縁膜、 19・・・複合基板、
21・・・蝕刻部に形成された絶縁膜、 22゜22a
・・・エピタキシャル層、 23・・・多結晶シリコン
層。 第1図<C> 第1区(d) 第1図(e) 第2図 第3図 第4図
FIGS. 1<a) to 1(0) are cross-sectional views showing the manufacturing process of a composite semiconductor crystal according to an embodiment of the present invention (FIG. 1(e) is a cross-sectional view showing the manufacturing process of a composite semiconductor crystal according to an embodiment of the present invention). 2 is a sectional view showing another embodiment of the composite semiconductor crystal of the present invention, FIG. 3 is a sectional view of a conventional junction isolation device using a PN junction, and FIG. 4 is a sectional view showing the structure of a semiconductor crystal. 1 is a cross-sectional view of a conventional insulating layer separation method element using an insulator. 16... First semiconductor substrate, 17... Second semiconductor substrate, 18... Bonding insulating film, 19... Composite substrate,
21... Insulating film formed on the etched portion, 22° 22a
...Epitaxial layer, 23...Polycrystalline silicon layer. Figure 1 <C> Section 1 (d) Figure 1 (e) Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1 第1半導体基板の1つの主面と第2半導体基板の1
つの主面とを絶縁膜を介して鏡面接合してなる複合基板
と、この複合基板の第1半導体基板及び接合絶縁膜に選
択的蝕刻をして設けた少なくとも一部で第2半導体基板
に達する蝕刻部と、この蝕刻部のいくつかに形成された
絶縁膜と、この蝕刻部の第2半導体基板上に設けたエピ
タキシャル層と、このエピタキシャル層と同時に前記蝕
刻部に形成された絶縁膜上に設けた多結晶シリコン層と
を具備することを特徴とする複合半導体結晶体。
1 one main surface of the first semiconductor substrate and one main surface of the second semiconductor substrate
A composite substrate formed by mirror bonding two principal surfaces via an insulating film, and at least a portion of the composite substrate formed by selectively etching the first semiconductor substrate and the bonding insulating film to reach the second semiconductor substrate. an etched portion, an insulating film formed on some of the etched portions, an epitaxial layer provided on the second semiconductor substrate of the etched portion, and an insulating film formed on the etched portion at the same time as this epitaxial layer. A composite semiconductor crystal body comprising a polycrystalline silicon layer.
JP20124786A 1986-08-29 1986-08-29 Composite semiconductor crystal structure Pending JPS6358817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20124786A JPS6358817A (en) 1986-08-29 1986-08-29 Composite semiconductor crystal structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20124786A JPS6358817A (en) 1986-08-29 1986-08-29 Composite semiconductor crystal structure

Publications (1)

Publication Number Publication Date
JPS6358817A true JPS6358817A (en) 1988-03-14

Family

ID=16437775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20124786A Pending JPS6358817A (en) 1986-08-29 1986-08-29 Composite semiconductor crystal structure

Country Status (1)

Country Link
JP (1) JPS6358817A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
US5525824A (en) * 1993-11-09 1996-06-11 Nippondenso Co., Ltd. Semiconductor device with isolation regions
US6107125A (en) * 1997-06-18 2000-08-22 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
JP2007129256A (en) * 2007-01-05 2007-05-24 Toshiba Corp Element formation substrate
JP2007180569A (en) * 2001-12-27 2007-07-12 Toshiba Corp Semiconductor device
JP2008182281A (en) * 2008-04-21 2008-08-07 Toshiba Corp Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
US5525824A (en) * 1993-11-09 1996-06-11 Nippondenso Co., Ltd. Semiconductor device with isolation regions
US5650354A (en) * 1993-11-09 1997-07-22 Nippondenso Co., Ltd. Method for producing semiconductor device
US6107125A (en) * 1997-06-18 2000-08-22 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
JP2007180569A (en) * 2001-12-27 2007-07-12 Toshiba Corp Semiconductor device
JP2007129256A (en) * 2007-01-05 2007-05-24 Toshiba Corp Element formation substrate
JP4660489B2 (en) * 2007-01-05 2011-03-30 株式会社東芝 Element forming substrate
JP2008182281A (en) * 2008-04-21 2008-08-07 Toshiba Corp Semiconductor device

Similar Documents

Publication Publication Date Title
US5131963A (en) Silicon on insulator semiconductor composition containing thin synthetic diamone films
JPS6276645A (en) Structure of composite semiconductor crystal
JPS6159853A (en) Structure of silicon crystalline body
JPH01315159A (en) Dielectric-isolation semiconductor substrate and its manufacture
JPH01179342A (en) Composite semiconductor crystal
JPH04106932A (en) Manufacture of bipolar transistor
JPS6159852A (en) Manufacture of semiconductor device
JPS6358817A (en) Composite semiconductor crystal structure
US5521412A (en) Low and high minority carrier lifetime layers in a single semiconductor structure
JPS63246841A (en) Dielectric isolating method of silicon crystal body
JPH01302740A (en) Dielectric isolation semiconductor substrate
JP3243071B2 (en) Dielectric separated type semiconductor device
JP2839088B2 (en) Semiconductor device
JPH01259546A (en) Manufacture of semiconductor device
JPH05335649A (en) Hall element
JPS61182242A (en) Manufacture of semiconductor device
JPH03180070A (en) Semiconductor device and manufacture thereof
JPS61172346A (en) Semiconductor integrated circuit device
JPH0548108A (en) Semiconductor device and its manufacture
KR100511900B1 (en) Method of manufacturing SOI substrate
JPS63107161A (en) Manufacture of semiconductor element
JPS6334949A (en) Semiconductor device
JPS58159348A (en) Separation of semiconductor device
JPS58155739A (en) Semiconductor device
JPS61144037A (en) Semiconductor device and manufacture thereof