JPH01259546A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a series resistance of a collector and improve performance of a semiconductor element by selectively eliminating the main surface at the opposite side to the bonded surface of a first semiconductor substrate and by forming a semiconductor element part within a first semiconductor substrate on an insulating layer after forming a conductive layer and an insulating layer in sequence on the first semiconductor substrate and then bonding the second semiconductor substrate on the insulating layer. CONSTITUTION:After forming an area 22 with a low resistance consisting of metallic silicide on a substrate 21, SiO2 is piled on it to form an insulating layer 23 and contact bonding and heat treatment are performed on the insulating layer 23 to allow a supporting substrate 24 to be bonded. Then, by selectively eliminating a main surface B at the opposite side to a bonded surface A of the substrate 21 with polishing to make the layer thickness to be thin, a semiconductor element part C is formed within the substrate 21 on the insulating layer 23. Thus, since the metallic silicide low-resistance area 22 is formed on a supporting substrate 24 through the insulating layer 23, the collector series resistance is reduce and switching speed of a semiconductor element can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a method of manufacturing a semiconductor device, the purpose of this invention is to provide a method of manufacturing a semiconductor device that can reduce collector series resistance and improve switching speed of a semiconductor element. a step of sequentially forming a conductive layer on the first semiconductor substrate, a step of bonding a second semiconductor substrate on the insulating layer, and a step of selectively forming a main surface of the first semiconductor substrate opposite to the bonding surface. and forming a semiconductor element portion in the first semiconductor substrate on the insulating layer.

[Industrial application field]

The present invention is a so-called SOI (Silicon On Inverter) in which a semiconductor element is formed on an insulating layer.
) structure, in detail, an SOI structure can be realized by bonding a wafer to another wafer serving as a supporting substrate via an insulating layer, and in particular, the switching speed can be improved. The present invention relates to a method for manufacturing a semiconductor device.

In order to improve the performance of semiconductor integrated circuits, it is essential to form semiconductor elements with high switching speeds that eliminate parasitic capacitance. For this reason, various techniques have been proposed to reduce the junction capacitance, and among these, the most effective technique is to insulate the substrate immediately below the semiconductor element to reduce the junction capacitance between the substrate and the active region. In particular, in the case of bipolar transistors, for example, the junction capacitance between the buried collector layer and the substrate is very large, and it is necessary to significantly reduce this junction capacitance in order to achieve the high speeds required in the future.

[Prior Art] Hereinafter, a conventional method of manufacturing a semiconductor device that can realize a Sol structure by wafer bonding will be specifically described with reference to drawings.

FIGS. 5(a) to 5(h) are diagrams for explaining an example of a conventional method for manufacturing a semiconductor device. The illustrated semiconductor device is applied to a bipolar transistor.

In these figures, 1 is a single crystal St whose conductivity type is n-type.
The layer thickness is about 500 μm, and the specific resistance ρ is 0.
．． 003Ω·C or less. 2 has n-type conductivity and St
The semiconductor layer has a layer thickness of about 2.5 to 6 μm and a specific resistance ρ of about 0.5 to 1 Ω·cm. 3 has conductivity type n
° type semiconductor layer made of Si, layer thickness 1.5 to 3.0
The sheet resistance is about 20Ω/hole. 4 is an insulating layer having a layer thickness of about 1 μm and made of, for example, SiO□; 5 is a support substrate made of, for example, St; 6 is a resist; 7a, 7
b is a groove; 8 is an element isolation insulating film made of, for example, SiO□;
9a and 9b are windows, 10 is a base region whose conductivity type is p type, 1
1 is an emitter region whose conductivity type is n type, and 12 is an emitter region whose conductivity type is n type.
This is a type of collector area.

Note that the n-type semiconductor layer 3 functions as a buried low-resistance layer and a region from which current is taken out.

Next, the manufacturing process will be briefly explained.

First, as shown in FIG. 5(a), an n-type semiconductor layer 2 is formed on an n-type substrate 1 by epitaxial growth.

Next, as shown in FIG. 5(b), an n-type semiconductor layer 2
An n-type semiconductor N3 is formed thereon. At this time, the semiconductor layer 3 is made of As at 60KV and 5E by, for example, ion implantation.
15cm-”, 1000°C, to
1.5 to 3.0 by performing heat treatment of about o
It is formed with a layer thickness of about μm. Note that the semiconductor layer 3 can also be formed by heat dissipation.

Next, as shown in FIG. 5(C), an n-type semiconductor layer 3
After forming the insulating layer 4 by oxidizing the 0 surface,
The support substrate 5 is bonded onto the insulating layer 4 by heat treatment while being press-bonded.

Next, as shown in FIG. 5(d), the substrate 1 is removed by wet etching. At this time, the substrate 1 is etched using an etching solution made by mixing HF, HNO, and CH3CO0H in a ratio of 1:3:8, using the difference in impurity concentration between the n-type substrate 1 and the n-type semiconductor layer 2. Etch back removal is performed. This exposes the surface of the semiconductor layer 2,
The semiconductor layer 2 then has an appropriate thickness suitable for forming an active element.

Next, as shown in FIG. 5(e), the semiconductor element is turned upside down and a resist 6 is patterned on the semiconductor layer 2. Then, as shown in FIG.

Next, as shown in FIG. 2(f), the n-type semiconductor layer 2 and the n°-type semiconductor layer 3 are selectively etched by RIE using the resist 6 as a mask to form grooves 7a and 7b. After that, the resist 6 is removed. At this time, the insulating layer 4
is exposed.

Next, as shown in FIG. 5(g), after depositing Sin on the entire surface by CVD, the surface is etched back and planarized to form an element isolation insulating film 8.

Then, as shown in FIG. 5(h), the element isolation insulating film 8
After selectively etching to form a window (not shown), B is selectively implanted into the semiconductor layer 2 by ion implantation to form a p-type base region 10. Next, windows 9a and 9b are similarly formed in the element isolation insulating film 8, and then As'' is selectively implanted into the base region 10 and the semiconductor layer 2 by ion implantation to form an emitter region 11 and a collector region 12. Although not shown here, an emitter electrode, a base electrode, and a collector electrode are formed, and wiring and the like are formed to complete the semiconductor device.

[Problem to be solved by the invention]

However, in semiconductor devices obtained by such conventional semiconductor device manufacturing methods, the collector series resistance can be reduced to some extent because the semiconductor layer 3, which functions as a buried low-resistance layer, is a highly doped n-type semiconductor layer. In Although,
If further reduction in collector series resistance is required, the collector series resistance remains high, resulting in a problem in that the switching speed of the semiconductor device deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the collector series resistance and improve the switching speed of a semiconductor element.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a conductive layer and an insulating layer on a first semiconductor substrate, and bonding a second semiconductor substrate on the insulating layer. , a step of selectively removing a main surface of the first semiconductor substrate opposite to an adhesive surface; and a step of forming a semiconductor element portion in the first semiconductor substrate on the insulating layer.

In the present invention, the conductive layer functions as a region from which current is taken out as a buried low resistance layer.

The configuration of the present invention will be explained below using an embodiment of the present invention which will be described in detail later.

That is, the method for manufacturing a semiconductor device of the present invention is as shown in FIG.
As illustrated in a) to (d) and FIG. 2, first, as shown in FIGS. 1(a) and (b), a conductive layer (metal silicide After sequentially forming a low resistance region 22) and an insulating layer 23, and bonding a second semiconductor substrate (supporting substrate 24) on the insulating layer 23 as shown in FIG. The main surface B of the first semiconductor substrate (substrate 21) opposite to the adhesive surface A shown in FIG. 1(C) is selectively removed as shown in FIG. 1(d), and then as shown in FIG. A semiconductor element portion C is formed within the first semiconductor substrate (substrate 21) on the insulating layer 23.

[Function] In the present invention, a conductive layer and an insulating layer are sequentially formed on a first semiconductor substrate, and after a second semiconductor substrate is bonded onto the insulating layer, a conductive layer and an insulating layer are formed on the first semiconductor substrate on the opposite side to the bonding surface of the first semiconductor substrate. The side main surface is selectively removed, and a semiconductor element portion is formed in the first semiconductor substrate on the insulating layer.

Therefore, the collector series resistance is reduced and the performance of the semiconductor device is improved.

〔Example] Hereinafter, the present invention will be explained based on the drawings.

1(a) to 1(d) are diagrams for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 shows the structure of a semiconductor device obtained by the method for manufacturing a semiconductor device according to the embodiment. FIG. The illustrated semiconductor device is applied to a bipolar transistor.

In these figures, the same reference numerals as in FIGS. 5(a) to 5(h) indicate the same or corresponding parts, and 21 is a substrate of n-type conductivity and made of, for example, single crystal Si (the first semiconductor according to the present invention). (corresponds to the substrate), and the specific resistance ρ is, for example, 0.5Ω・c
m and the layer thickness is, for example, 500 μm. 22 is, for example, W
A low resistance region (corresponding to the conductive layer according to the present invention) consisting of a metal silicide layer (usually high melting point) such as S i, , MoS it , TiSix, etc., with a layer thickness of, for example, 0.1 to 1
It is about μm.

23 is an insulating layer made of, for example, Sin, and has a layer thickness of, for example, 0. It is about -5 to 2 μm. 24 is a support substrate (corresponding to the second semiconductor substrate according to the present invention).

Note that the low resistance region 22 functions as a region from which current is taken out as a buried resistance layer.

Next, the manufacturing process will be explained.

First, as shown in FIG. 1(a), a low resistance region 22 made of metal silicide is formed on a substrate 21 by, for example, a CVD method (sputtering method, vapor deposition method, etc.).
After forming a layer with a thickness of 1 to 1 μm, S is deposited on the low resistance region 22 by, for example, vapor phase growth, as shown in FIG.
The insulating layer 23 is formed with a layer thickness of, for example, 0.5 to 2 μm by depositing iO□. This corresponds to the step of sequentially forming a conductive layer and an insulating layer on the first semiconductor substrate of the present invention.

Next, as shown in FIG. 1(c), the support substrate 24 is bonded onto the insulating layer 23 by heat treatment while being pressure-bonded.

This corresponds to the step of bonding the second semiconductor substrate onto the insulating layer of the present invention.

Next, as shown in FIG. 1(d), the main surface B on the opposite side to the bonding surface of the substrate 21 shown in FIG. 1(C) is selectively removed, for example, by polishing, so that a Form thinly so that the layer is thick. This corresponds to the step of selectively removing the main surface of the first semiconductor substrate opposite to the adhesive surface of the present invention.

Then, by going through the manufacturing process similar to the conventional method shown in FIGS. 5(e) to 5(h), the substrate 2 on the insulating layer 23-
A semiconductor element portion C is formed in the semiconductor device 1, and a semiconductor device as shown in FIG. 2 is completed. This is the first layer on the insulating layer of the present invention.
This corresponds to the process of forming a semiconductor element part in a semiconductor substrate.

That is, in the above embodiment, since the low resistance region 22 made of metal silicide is formed on the support substrate 24 via the insulating layer 23, the collector series resistance is reduced (the parasitic resistance of the semiconductor element itself is reduced). ) (the conventional limit of 20 Ω/output has been reduced to 1 ohm/outlet or less), and the switching speed of semiconductor devices can be improved. In the above embodiment, the low resistance region 22 is made of a metal silicide layer, but the present invention is not limited to this. For example, WlMo
In this case, it can be formed by a method such as a CVD method, a sputtering method, a vapor deposition method, etc., as in the case of forming a metal silicide layer.

In the above embodiment, the case where the insulating layer 23 is deposited on the low resistance region 22 by vapor phase epitaxy is explained, but the present invention is not limited to this, and It may be made of metal silicide and formed by thermally oxidizing the low resistance region.

In the above embodiment, the substrate 21 is selectively removed by polishing to form a thin layer, but the present invention is not limited to this, and the substrate 21 is selectively removed by wet etching or the like. It is also possible to remove the substrate 21 and form it thinly. Specifically, as shown in FIG. 001 Ω·cm) and a low concentration (n-type) semiconductor layer 25b, which is thinner than the high concentration semiconductor layer 25a, and the n-type semiconductor layer 25a is removed by wet etching to form a substrate. This is a case where 21 is made thinner.

At this time, HF5HNO3 and CH, C0OH were mixed in l:3
The n-type semiconductor layer 25a is etched back and removed by using an etching solution mixed at a ratio of 1:8 to 100% by utilizing the difference in impurity concentration between the n-type semiconductor layer 25b and the n2-type semiconductor jW25a.

Alternatively, the substrate 21 may be mechanically or chemically polished to form a thin layer using a polishing liquid containing a slurry of Affi, 03 mixed therein.

In the above embodiment, the case where the semiconductor element section C is constituted by a bipolar transistor as shown in FIG. For example, it may be constructed of vertical MOS transistors as shown in FIG.

Here, in FIG. 4, the same reference numerals as in FIG. 2 indicate the same or corresponding parts, and 31 is a source region, which is composed of a P' type region and an n' type region.

32 is a gate electrode made of Si, for example, and 33 is an n-type contact)? In the J region, this region functions as a region for contacting an external wiring (not shown) and the low resistance region 22. The low resistance region 22 can function as a drain region.

〔effect〕

According to the present invention, the switching speed of a semiconductor element can be improved by lowering the collector series resistance, and a semiconductor device with good performance can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating an embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view showing the structure of a semiconductor device obtained by the method for manufacturing a semiconductor device according to the embodiment, and FIG. FIG. 4 is a cross-sectional view showing the structure of a semiconductor device obtained by the manufacturing method of another embodiment, and FIG. 5 is a conventional method. FIG. 2 is a diagram illustrating an example of a method for manufacturing a semiconductor device. 21... Substrate, 22... Low resistance region, 23... Insulating layer, 24... Support substrate.

Claims (1)

[Claims] A step of sequentially forming a conductive layer and an insulating layer on a first semiconductor substrate, a step of adhering a second semiconductor substrate on the insulating layer, and adhering the first semiconductor substrate. A method for manufacturing a semiconductor device, comprising the steps of: selectively removing a main surface opposite to the main surface; and forming a semiconductor element portion in the first semiconductor substrate on the insulating layer.