JPS6343771B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system switching control method for an information processing system.

2. Description of the Related Art As a means for improving the reliability of information processing systems, a configuration in which devices are duplicated, that is, a duplex system is known.

Figure 1 shows a conceptual diagram of the duplex system. This system consists of an active system 1, a standby system 51, and an intersystem interface signal line 110 that connects both systems.
It consists of The active system 1 and the standby system 51 are systems that can each independently process information, but they do not need to have exactly the same configuration. The active system 1 performs office operations, and the standby system 51 can be in several standby states. For example, there is a state in which the power is not turned on and is on standby, a state in which the power is turned on and waiting for a program to be loaded, or a state in which the program is loaded and a batch job is executed and on standby. Now, if some kind of failure occurs in the active system and it is determined that it is impossible to continue the work on the active system, the standby system is activated via the intersystem interface 110, and the work is transferred from the active system to the standby system. By transferring the system and continuing operations on the standby system, it is possible to build a highly reliable system that minimizes system downtime due to failures.

A conventional system switching control system will be explained with reference to FIG. 2, which shows an example of a duplex system. The active system 1 and the standby system 51 include a plurality of central processing units (CPUs) 2 and 53, and a main memory (MEM).
3 and 52, input/output control devices (IOP) 4 and 55, and communication control devices (ICA) 5 and 56. Furthermore, this system
Switching device (SW) 1 shared by these two systems
02, a switching control device (SWC) 101, and various input/output devices 103 to 108. Various input/output devices include, for example, file-based magnetic disk devices and magnetic tape devices, as well as terminal-based card readers, line printers, bank teller terminals, and the like. Interface signal line 1 between SVPs of both systems
10. The interface signal line 110 consists of a plurality of signal lines, and includes an SVP interrupt signal line and its acceptance signal line. SVP6 and SWC
101 and the signal line 40 between SVP56 and
The signal line 90 between the SWC 101 and the
This is a signal line for system switching instruction signals from SVP,
SWC101 connects each input/output device 1 via SW102.
The systems connected to 03 to 108 are switched. While the current system 1 is executing the work, the various input/output devices 103 to 108 connected to SW102 are connected to SW1.
It is connected to the IOP4 and ICA5 of the active system 1 by signal lines 20 and 30 via the line 02.

System switchover is performed when it is impossible for active system 1 to continue operations, and the reasons for this include, for example, SVP
failure, CPU failure, software failure, etc. Furthermore, when IOPs and ICAs are essential to the system, their failures can also be a factor in system switching. In case of failure of SVP6 of active system 1, SVP
6 reports the failure to the CPU 2 via the system bus 10, and the CPU 2 reports this to the software. The software on the active system 1 prepares for system switching and sends SVP5 of the standby system 51 to SVP6.
6, execute an instruction that generates an SVP interrupt. In addition, in the event of a software failure on the active system 1,
The software prepares for system switching and performs SVP6.
An instruction is executed to cause the SVP 56 of the standby system 51 to generate an SVP interrupt. In addition, the current system 1
When CPU2 fails, SVP6 detects the failure and
An SVP interrupt is generated to the SVP 56 of the standby system 51.
On the other hand, SVP5 of the standby system 51 that accepted the SVP interrupt
6 turns on the power if the standby system 51 is in a power-off state, loads the program if it is in a program load waiting state, starts the software, and connects the CPU to the standby system 51.
53 to generate an interrupt. The CPU 53 reports the interrupt to standby software, and the software executes a system switching command to the SVP 56.
The SVP 56 issues a system switching instruction to the SWC 101, and the SWC 101 connects the various input/output devices 103 to 108 connected to the SW 102 to the standby system 51. However, with this method, when switching systems in the event of an SVP failure, the software must execute an instruction that generates an SVP interrupt for the failing SVP, so its operation is not guaranteed. In order to guarantee this, there is a drawback that the generation of SVP interrupts and the control of the intersystem interface must be realized by hardware independent of SVP.

In addition, as another method, when SVP6 fails,
It is conceivable that the SVP 6 reports a failure to the CPU 2 and also generates an SVP interrupt to the SVP 56 of the standby system 51. The CPU 2 reports the SVP failure to the software of the active system 1, and the software of the active system 1 prepares for system switching. on the other hand,
The SVP 56, which has accepted the SVP interrupt, starts the software of the standby system 51 in the same way as described above, and the CPU 5
Generates an interrupt at 3. CPU53 is standby system 51
The interrupt is reported to the software, and a system switching command is executed to the software SVP 56.
Thereafter, system switching is performed in the same manner as described above. In this method, when an SVP failure occurs, the SVP itself generates an SVP interrupt, so hardware independent of the SVP is not required to generate an SVP interrupt, but synchronization is required between the active software and the standby software. Since this is not done, system switching may occur without the active software's knowledge or while the active software is executing a task, and there is a risk that file contents may be destroyed.

As a method to eliminate such drawbacks, the following method is available in which a simple interface is added between the two systems and synchronization is achieved between the two systems. In other words, both systems
A pair of forced stop signal lines are provided between SVPs, and after receiving the SVP interrupt, the software in the standby system 51 sends a forced stop instruction command to the active system 1 to stop instruction execution before issuing a system switchover instruction. Issue.
The CPU 2 of the active system 1, which has been instructed to forcibly stop, immediately stops execution of subsequent instructions at the end of the currently executing instruction. As a result, the continuation of business operations after switching the active system 1 is eliminated. However, in such a system, when a forced stop instruction is given, the execution of the instruction is unconditionally stopped, and even if a forced stop instruction instruction is issued by mistake, the execution of the instruction is also stopped. There is a drawback. For example, if a software bug (insect) in the standby system 51 erroneously issues a forced stop instruction command to the active system 1, or if a forced stop signal line is activated due to a hardware failure, the normal system is immediately restored. Active system 1 stops.

An object of the present invention is to provide a system switching control method for an information processing system that eliminates the above-mentioned drawbacks.

The method of the present invention is a system switching control method for an information processing system having a first and a second processing system, in which the second (or second) processing system responds to failure detection in the first (or second) processing system. a first signal sending means provided in the first (or second) processing system to send an interrupt signal to the first processing system; a storage means provided in the (or second) processing system; and a forced stop signal for stopping the instruction execution operation of the first (or second) processing system in response to the interrupt signal.
a second signal sending stage provided in the second (or first) processing system to send the signal to the second (or second) processing system, based on the contents of the storage means and the forced stop signal. The instruction execution operation of the first (or second) processing system is stopped, and the second (or first) processing system continues the processing of the first (or second) processing system.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows intersystem interface signal lines in the present invention. From the active system 1, there are an SVP interrupt signal line 111, a forced stop signal line 113, and an interrupt acceptance signal line 115, and from the standby system 51, an SVP interrupt signal line 112, a forced signal line 114, and an interrupt acceptance signal line. 116 are respectively connected to other systems.

FIG. 4 is a diagram showing a command to activate the forced stop signal line. The instruction length is 32 bits. Bit 0-
7 is an instruction (OP) code section, which here is a system call instruction SYC. I2 is instruction auxiliary information, and by giving 15 in hexadecimal, it becomes a forced stop instruction during a system call instruction. B1 indicates the value of the base register when modifying the address, α
1 indicates displacement.

FIG. 5 is a diagram showing the operations of the active system and standby system on the time axis when an SVP failure occurs. Next, the operation of the system of the present invention in the event of an SVP failure will be explained with reference to FIGS. 2 and 5. SVP at SVP6 of active system 1
When a failure occurs, an internal machine check interrupt is generated for the CPU 2 of the active system 1, and the SVP of the standby system is sent via the intersystem interface 110.
Generates an SVP interrupt for 56. The CPU 2 generates an interrupt to the software, and the software performs processing to interrupt normal operations and stops the instructions, but the instructions may continue to be executed due to some reason such as a software bug. In Figure 5,
As an example of this, a case where instructions B, C, D and E are continued is shown. On the other hand, the SVP56 that has accepted the SVP interrupt notifies the SVP6 of the acceptance via the interrupt acceptance signal line 116, and also
Generates an SVP interrupt to CPU52, and
2 interrupts the software. On the other hand, in SVP6, the interrupt request holding circuit is set by the interrupt acceptance signal line 116. The standby system software recognizes the SVP interrupt from the active system, prepares for system switchover, and executes a forced stop command (SYC command (I2 = 15) before actually issuing a system switchover instruction, and stops the active system 1. The SVP 6 instructs the CPU 2 to stop the instruction if the interrupt request holding circuit is set in response to this stop instruction.
If the CPU 2 is executing an instruction for some reason, the CPU 2 stops executing the instruction after the currently executing instruction (in this example, instruction E) is completed. Therefore, from this point on, the CPU 2 (software) of the active system 1 does not perform any operation on the various input/output devices shared by the system. After this, CPU52 of standby system 51
(Software) executes a command to instruct the SWC 101 to switch systems, connects the various input/output devices 103 to 108 connected to the SW 102 to the standby system, and can resume business on the standby system. . However, even if a stop instruction is received when the interrupt request holding circuit is not set in SVP6, this stop instruction is ignored. In this way, the system operates correctly even if a stop instruction is given by mistake.

FIG. 6 is a diagram showing an embodiment for carrying out the method of the present invention. In the figure, only parts related to the present invention are shown, and other components necessary for a general information processing device (for example, a storage device, a computing unit, etc.) are omitted. In the figure, intersystem interface lines 111 to 116 are connected to the standby system, respectively.
SVP interrupt line, SVP interrupt signal line from standby system, forced stop signal line to standby system, forced stop signal line from standby system, interrupt acceptance signal line to standby system, and interrupt acceptance from standby system It is a signal line.

This embodiment includes a holding circuit 201 that temporarily holds the SVP interrupt signal line 112, a masking circuit 202 that masks (makes it impossible to accept) SVP interrupts, and a holding circuit 201 that temporarily holds the SVP interrupt signal line 112.
01 and the output from the mask circuit 202
An AND circuit 203 that generates a (logical product) condition, another interrupt signal line group 207, an OR circuit 204 that generates an OR (logical sum) condition for various interrupt signal lines, and software activated by the output of the OR circuit 204. Output signals from the interrupt generation circuit 205 and the interrupt holding circuit 227 that generate interrupts, and the forced stop signal line 114
AND circuit 2 that generates an AND condition with the signal from
27. A holding circuit 211 that temporarily holds the output of the AND circuit 215, another instruction stop signal line group 214, an OR circuit 212 that generates OR conditions for various instruction stop signal lines, and an output that is activated by the output of the OR circuit 212 and is currently being executed. An instruction stop control circuit 213 that stops execution of instructions at the end of the instruction in the instruction register 22 that stores one word of instructions to be executed by software.
1. A decoder 222 that decodes the contents of the instruction register 221, a holding circuit 223 that temporarily holds the output signal when the decoder 222 decodes the SVP interrupt generation instruction, and an SVP interrupt that generates an output when an SVP failure or CPU failure occurs. inclusion generation circuit 225,
Holding circuit 223 and SVP interrupt generation circuit 225
an OR circuit 226 that generates an (OR) condition for the output of
The interrupt holding circuit 22 is set by the SVP interrupt signal 111 and the interrupt acceptance signal 116 from another system.
7. A holding circuit 224 is provided which temporarily holds an output signal when the decoder 222 decodes the forced stop instruction command. Although FIG. 6 shows the active system, it is assumed that the standby system has the same configuration.

In the active system, circuit 225 generates an output signal if the CPU or SVP fails. In addition, if the software is at fault, the software executes the SVP interrupt generation instruction, and the decoder 22
2 sets the holding circuit 223 by decoding this instruction. In either case, an SVP interrupt signal is sent to the standby system via line 111.

On the other hand, considering FIG. 6 as a standby system, when an SVP interrupt occurs via the signal line 112, it is held in the holding circuit 201, and if the mask bit of the mask circuit 202 is not "0", the AND circuit 20
3, an interrupt signal is generated, an interrupt acceptance signal is sent to the active system, and the interrupt generation circuit 205 notifies the software of the interrupt. The software checks the cause of the interrupt, and when it recognizes the SVP interrupt, prepares for system switching and issues a forced stop command (SYC command (I2 = 15)) to forcefully stop the active system.
Execute. The decoder 222 decodes this command, temporarily holds the result in the holding circuit 224, and instructs the active system to forcibly stop via the signal line 113.

Again, consider Figure 6 as the current system. Holding circuit 227
When receiving an interrupt acceptance signal via signal line 116, it is set by the interrupt signal already output to signal line 111, and holds that the active system has issued an interrupt request. In this state, if a forced stop signal given from the standby system via the signal line 114 instructs a forced stop, if the holding circuit 227 is set, this forced stop signal is held via the AND circuit 215. The instruction is temporarily held in the circuit 211 and sent to the instruction stop control circuit 2 via the OR circuit 212.
given to 13. This circuit 213 interrupts and stops execution of the next and subsequent instructions at the end of the currently executing instruction. On the other hand, due to some reason such as a bug in the standby software, the signal line 11
Even if a forced stop is instructed to the active system via 4, the holding circuit 227 of the active system is not in the set state, so the forced stop signal does not pass through the AND circuit 215, and the instruction stop control circuit does not operate.

As described above, the present invention has the advantage that system switching operations can be easily guaranteed with the addition of a small amount of hardware.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of a duplex system, Fig. 2 is a block diagram showing an example of a duplex system, and Fig. 3 is a block diagram showing intersystem interface signal lines of a duplex system according to the method of the present invention. 4 is a diagram showing the format of an instruction used in the present invention, FIG. 5 is a time chart showing the operation according to the method of the present invention, and FIG. 6 is a diagram showing an embodiment for carrying out the method of the present invention. It is a block diagram. In the figure, 1...active system, 2,53...central processing unit, 3,52...main storage device, 4,55...input/output control device, 5,54...communication control device, 6,56...
Monitoring device, 10, 60... System bus, 20,
30, 40, 70, 80, 90, 120, 13
0,140,150,160,170...signal line,
110-116...Intersystem interface signal line, 1
01...Switching control device, 102...Switching device, 103
~108...I/O equipment, 201, 211, 22
3,224,227...Holding circuit, 202...Mask circuit, 203,215...AND circuit, 204,2
DESCRIPTION OF SYMBOLS 12, 226...OR circuit, 205...Interrupt generation circuit, 213...Instruction stop control circuit, 221...Register, 222...Decoder.

Claims (1)

[Claims] 1. In a system switching control system for an information processing system having a first and a second processing system, in response to a failure detected in the first (or second) processing system, the second
A first (or second) processing system provided in the first (or second) processing system to send an interrupt signal to the first (or first) processing system.
a signal sending means, a storage means provided in the first (or second) processing system for storing the sending of the interrupt signal;
A forced stop signal is sent to the first (or second) processing system to stop the instruction execution operation of the first (or second) processing system.
the second (or first)
and a second signal sending means provided in the processing system,
The instruction execution operation of the first (or second) processing system is stopped based on the contents of the storage means and the forced stop signal, and the second (or first) processing system stops the instruction execution operation of the first (or second) processing system. 2) A system switching control method for an information processing system, characterized in that the processing of the processing system is continued.