JPS6342263A - Sound branching circuit - Google Patents

Abstract

PURPOSE:To easily set various types of sound branching modes by using a RAM as the holding part of a digital sound. CONSTITUTION:The holding part 12 is constituted of the RAM and an address input AD for writing and reading is applied from a branch mode setting part 14. A digital sound input Din (A-C) becomes A + B, A + B + C or A through an accumulation addition part 11, is held in a holding part 12 by a writing address input W and the A-C are written in the holding part 12. A prescribed one of accumulation addition outputs Dra (A + B, A + B + C, A) and a prescribed one of the sound input Din are selected by a reading address input R and read, a subtraction is carried out therebetween and a desired sound output Dout is obtained from a subtracter 13. Thereby, an arbitrary branching mode can be set only by changing the reading address input R.

Description

[Detailed Description of the Invention] 1.a Required] 2O through the phone, etc., and the voice portion IL, the torment circuit 3? There is an accumulative adder that cumulatively adds the digital audio inputs of the digital audio inputs, a cumulative adder that stores the result of the X product addition, and a memory that stores each digital audio input before the cumulative addition. ), and a subtraction section that subtracts the voice power of each ) from the cumulative addition result held in the holding section, and various voice branching modes are available by adopting RAM. Easily set to t+J function.

[Industrial application field]

The present invention relates to voice branching mode.

For example, when a conference call is established between subscribers, an audio branch circuit is essential for adding audio input signals and preventing overloads due to the addition. c.
The demand is increasing) Planning for the construction of the ζ Giant 1 List J1: 1 The 95-7 will become one of the main and functional parts of the car.

In the case of , 2, it is good for digitalizing the exchange system〉・ノ, the sound i! 'i input signal:: L digital signal Z1. ′
Stall (θ) (・L 6゛, digital processing 4 north body, audio branch circuit) [Conventional branch i Hol] Digital processing is 1 Ni, L, 16 audio branch episode hu6
I, E Existing 5 I have no suggestions, 5 R C) 1. In many cases, such as 2J, 7, etc., this is done by processing the microbe II cells as the core 1:J-1/'.

[Problems to be solved by the invention] ``The audio branching mode that relies on 1-gram processing is divided into 2, the core microphone 1 cob C sensor and its peripheral circuit group. There is an old problem in that it requires a huge number of steps to create 7grams.Also, such audio branching circuits are no longer necessary, and the predetermined audio branching mode is extremely faithful and high speed. However, after that, there may be changes in the branching processing function (changes in various voice branching modes), expansion of the function, etc.
When there is a need for reduction, etc., it is necessary to change the Progera J each time, which is disadvantageous in terms of flexibility.

[Means for solving problems]

FIG. 1 is a principle block diagram of an audio branch circuit according to the present invention. In this figure, an audio branching circuit 10 successively receives digital audio input DjK and outputs a branched digital audio output D0111.

This digital voice input Din is applied to the cumulative addition section 11 on the one hand, and also to the holding section 12 on the other hand. The holding section 12 also receives the cumulative addition output Di from the cumulative addition section 11 J1.

Here, the holding unit 12 is a random access memory (RAM).
), and this RAM 4: address manual AD for writing (W) and reading (R).
are, for example, 6 read data given from the branch mode setting unit 14, that is, Dm and Dta are the subtraction unit 13.
The signal is supplied to the signal, and is subjected to the calculation (D m, -""-D In ), and the result becomes a digital audio output.

[For production]

For example, if there is a conference with three speakers, the digital voice input from each speaker D in (A, B, C1
) is A+8, Δ+B throughout the cumulative addition section 11
+ remains as C or A. These A, a total of 8 and A+B+C are held in the holding unit 12 by address input AD(W) for writing e7. =-force, A, B,
C itself is also provided in the holding section 12 with write a.
is written and held by the input AD(W).

Next, the cumulative addition output Dra (A+B, A+B+C
and a predetermined one of A) and a digital voice human power L)
■ A predetermined one of (A, B, and C) is selected by the read address manually AD (R), read 1, 7 from the holding unit 12, and subtracted between them (D, a, -ri body).
I do. Here, by reducing r by 3, the desired tone output D out of I9L can be obtained from the device 13. For example, if the above-mentioned three speakers are in a branch mode in which they confer equally, the subtracter 13 would send out B+C, A+C, and A+8 in the time slots assigned to each speaker. If the mode is a branch mode in which only the speaker corresponding to A among the above speakers confers with the other three parties, the subtractor 13 sends out B+C, A, and A in the above time slot. Such an arbitrary branch mode can be performed using the read address input AD.
Setting is possible by simply changing (R).

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings, and the same components are designated with the same reference numerals or symbols throughout the drawings.

FIG. 2 is a diagram showing a first embodiment of the present invention.

The audio branching circuit 20 shown in this figure mainly consists of the cumulative addition section 11, the holding section 12, and the subtraction section 13 shown in FIG. Conversion unit (N-L) 22 and register (RG)
23 on the input side, and a linear-nonlinear converter (L-N) 2
4 and a parallel-to-serial converter (PS) 25 on the output side.

Further, a pulse generator (PG) 26 performs timing control for each of the above components, and outputs a synchronization signal Ss.
and the clock CLK are manually operated.

This synchronization signal Ss is a signal essentially necessary for synchronizing with other parts that cooperate with the audio branch circuit 20, such as a digital transmission line interface part and an analog-to-digital conversion part. The analog audio input signal corresponding to each channel (corresponding to the route of each speaker described above) from the analog-to-digital converter is converted into a PCM code by an analog-to-digital converter (not shown) corresponding to each channel, and is then converted into a PCM code for each time slot. It becomes a serial digital audio input DiR. This Din is D+a in the figure, and is converted into parallel data for digital processing within the circuit 20. The numbers shown in parentheses in each line in this figure represent the number of parallel bits.

The input Dtyr of the PCM code, which has become parallel data, is once converted into a PCM code having a linear relationship with the original analog signal in the nonlinear-linear converter 22. It is well known that the original analog signal is non-linearly encoded according to the so-called μ law or A law to become a PCM code.

The input Din from the converter 22 is once buffered in the register 23, and then sent to the adder (ADD) 111.
on the other hand a second random access memory (RAM
2) applied to 122, respectively. The adder 111 is
Three-state buffer 112 and register (RG)
It has a feedback loop consisting of 113 loops and performs cumulative addition. Note that the three-state buffer 112 is closed when reading data from the first random access memory (RAM 1) 121;
) When writing to 121, it is open.

The data subjected to the above cumulative addition is written to the memory 121. Then, subtraction with the data in the memory 122 is performed in the subtracter (SUB) 13 to obtain desired branch data. Since this branch data is parallel data of a linearly encoded PCM code, a linear-nonlinear converter (
L-N) At 24, return to μ-law or A-law data,
Further, the signal is converted into serial data by a parallel-serial converter (PS) 25, and a digital audio output 1) out is obtained.

The branch mode setting section 14 in this figure is the same as that shown in FIG. 1, but the address input AD is the first memory 1.
21 and 2nd memo i month 22 respectively/
Sends successive address (W/R).

FIG. 3 is a time chart used to explain the operation of the circuit shown in FIG. 2. The objects of fl) to (15) a in this figure are shown at the right end of each column. Also, (8) to (15) in this figure
1 is divided into 1 and H sections, each with two upper and lower stages.

(2) is the first branch mode, and (2) is the second branch mode. It has already been mentioned that the branching mode can be easily set in the present invention, and an example thereof is shown by two modes (1) and (2). According to this example, in the second branch mode l,
Three speakers (each digital voice human power D tl'L A,
B and C) hold a telephone conference Jk equally (the number of speakers is 3 for the sake of the festival), and in the second branch mode ■, only the speaker (A) is the other three parties ( Telephone conferences will be possible with B and C) (conferences will not be possible with the other three parties).

The time chart of FIG. 3 makes the operation of FIG. 2 more obvious. Referring to both figures, a synchronizing signal Ss is generated periodically, and the audio branching circuit 20 operates in synchronization with this.

Digital voice input D<n is the input A of each time slot
, B, and C, and the inputs A, B, and C, which change from time to time, appear repeatedly in this order.

The register 23 contains the third data in the form of 14-bit parallel data.
As shown in column (3) in the figure, inputs A, B, and C are buffered once. By buffering, inputs A, B, and C, which are stretched in time, are obtained as shown in column (4) in the figure. A, B, and C are added to the output from register 113 in adder 111. Register 113 is initially silent (initially, the contents of register 113 are zero), but are added to the human input A from register 23. This becomes input A, which is further added to human power B, resulting in A+8.

Eventually, the output of the adder 111 is cumulatively added to A, A+B, and A+B+C, as shown in column (6) of the same figure. These A, A+B, A+B+C, and the manual input (A, B, and C) in column (1) of the same figure are random access memories (RAM 1, RAM 2)
By writing address input AD to 121 and 122,
The data is written to each memory 121 and 122. How the thus written memories 121 and 122 are read out and input to the subtracter 13 is determined depending on what kind of branching mode is to be realized.

In branch mode 1, data is read from the memory 121 as shown in column (8) in FIG. 3, and read from the memory 122 as shown in column 00 in the same figure. Therefore, the output of the subtracter 13 is as shown in column (12) in the figure, and finally, the digital audio output D Out in column (14) in the figure is obtained. In the end, speaker (A) can hear the voices of speakers (B) and (C). Similarly, speaker (B) can hear (A+C), and speaker (C) can hear (A+8). Note that the output (B+C).

(A+C) and (A+8) are converted into analog audio signals by digital-to-analog converters (not shown) corresponding to each channel, and then transmitted to each speaker.

In branch mode ■, see Figure 3 (9) 4rii! The data is read from the memory 121 as shown in (11) 'M' in the same figure. Therefore, the output of the subtracter 13 is as shown in column (13) in the figure, and finally, the digital audio output D out in column (15) in the figure is obtained. In the end, speaker (A) hears the voices of speakers (B) and (C) in between.

Conversely, speakers (B) and (C) can only hear the voice of speaker (A). In this case as well, the signal is converted into an analog signal by the digital-to-analog converter, and then sent to each speaker. Note that "silence" in (11) +lJ in the same figure means that the read address input AD is not given to the memo January 22.

Although the first embodiment described above is implemented using a discrete hardware configuration, there are other ways of implementation.

FIG. 4 is a diagram showing a second embodiment of the present invention.

The audio branch circuit 30 in this figure is a digital signal processing processor, so-called DSP (Digital Sig).
nalProcessor > 31 as the core, and everything except the converters 21 and 25 in FIG. 2 is assembled as a one-chip IC. DSPs have been widely used in recent years as devices that perform digital processing of four arithmetic operations at high speed and with high accuracy. Since it is good at high-speed four arithmetic operations, the cumulative addition unit 11 and subtraction unit 1 in FIG.
Processing No. 3 is easily executed. Furthermore, since it is common for the DSP itself to have a built-in RAM, it can also perform the function of the holding section 12 in FIG.

Furthermore, the conversion unit 22 in FIG. It can also perform the function of permission.

Since this DSP 31 operates based on a reference clock like a normal microprocessor, an oscillator 32 is provided. Furthermore, since the above-mentioned processes such as cumulative addition, subtraction, and retention are performed according to a program, a glue-only memory (ROM) for storing the program is also required. In the present invention, as described above, it is possible to adapt to multiple types of branch modes, so it is convenient to use an external ROM 33 and replace it for each branch mode.6 Also, the branch mode is input by the DSP. There is also a way to process it.

FIG. 5 is a time chart used to explain the operation of the circuit shown in FIG. However, (11, (2), (3) in Figure 5
) and (4) correspond to (11, (2) in Figure 3, respectively).
1, (12) and (13). Therefore, column (5) in FIG. 5 is unique to the second embodiment. That is, the D S-P inputs the digital voice input D+a from each speaker corresponding to A, B, and C to the j primary input (
(see input A, large input, and input C in the figure), data processed in the cycle immediately before the illustrated cycle, i.e., digital audio output (output A in the figure).

(see Output B and Output C) are output sequentially. These inputs and outputs are performed alternately. Predetermined branch processing is performed on input A, large input, and input C obtained in the illustrated cycle ("branch processing" in column (5) in the figure) and output in the next cycle.

6A and 6B are flowcharts showing the processing performed within the DSP of FIG. 4. FIG. 6A corresponds to input/output processing, and FIG. 6B corresponds to branch processing. That is, steps 1 to 6 in Figure 6A are input A in column (5) of Figure 5.
, output A, input B...corresponds to output C. These are D
The data is temporarily buffered in RAM (not shown) in the SP.

Step 7 in FIG. 6B corresponds to the operation of the conversion unit 22 in FIG.
The cumulative addition section 11 of FIG.
Then, an operation corresponding to the operation of the subtraction unit 13 is performed. Furthermore, step 10 corresponds to the operation of the converter 24 in FIG. Note that the conversion operations in steps 7 and 10 are performed by the DSP.
This is done by referring to a conversion table stored in a ROM (not shown) within the computer. Regarding the conversion operation in step 10, there is a method suitable for DSP, and one proposal will be made below. In other words, from the linear PCM code to the μ-law PCM
This is a conversion method to code (CCITT G, 711). The aim of this conversion method is step 10 (Figure 6B)
The aim is to minimize the processing cycles required. The ROM table used for this conversion is as shown below, and is in accordance with the international standard (μ law).

The specific process will be explained below.

(1) Take the absolute value of the linear PCM code and convert it to A
Place it as “L”.

(2) If the absolute value AL' is larger than a certain value IEEEO (hexadecimal), the absolute value AM of the nonlinear PCM code is set to 7F.
(hexadecimal) and jumps to the process in (7) below.

(3) On the other hand, if the absolute value AL' is smaller than IEEEO, add 21 (IS base) to the absolute value AL' to obtain AL.

That is, AL=AL'+21 It is.

If +4JAL is smaller than 200 (hexadecimal), the process jumps to step (6) below.

(5) If AL is greater than 200 (hexadecimal), then A
Let the values of the 13th, 12th and 11th bits of L be a,
From the above ROM table, use this a as the address and
and Ya. Then, the absolute value AM of the non-linear PCM code is determined by the following formula using the above AL. Note that the address a specifies one of 0, 1.2, . . . 7 in the leftmost column of the ROM table.

AM=(AL+Xa)Integer part of XYa From the above process (4), proceed to the following process (6).

(6) Setting the values of the 9th, 8th, and 7th bits of the AL as b, read xb and Yb from the ROM table using this b as an address (same as the above process (5)).

Then, the absolute value AM of the non-linear PCM code is determined by the following formula.

AM=(AL+Xb) Integer part of xYb From the above process (2), proceed to the following process (7).

(7) When the linear PCM code is positive; non-linear PCM
Code = 7F (hexadecimal) - When the AM linear PCM code is negative; Non-linear PCM code = FF (hexadecimal) AM This process (7
) is a process to find the absolute value of a nonlinear PCM code,
A sign bit (“1” if positive, “0” if negative, indicating the most significant focus) is further added to the non-linear PCM code that is actually output.

According to this proposal, when adding this sign bit,
Processing is simplified by using judgment instructions within the DSP. Generally, four types of instructions are issued within a DSP: arithmetic operations, logical operations, transfer, and judgment, and the last judgment instruction among these is also used to add a sign bit. That is, when the result of the four arithmetic operations is O1 positive or negative, the judgment instructions for jumping to the address where the corresponding instruction is written are used as they are to determine the sign focus.

〔Effect of the invention〕

As described above, according to the present invention, an audio branching circuit that can easily handle various branching modes is realized using relatively simple hardware.

[Brief explanation of the drawing]

1 is a principle block diagram of the audio branching circuit according to the present invention; FIG. 2 is a diagram showing the first embodiment of the present invention; FIG. 3 is a time chart used to explain the operation of the circuit in FIG. 2; The figure shows the second embodiment of the present invention, FIG. 5 is a time chart used to explain the operation of the circuit in FIG. 4, and FIGS. 6A and 6B show the processing performed in the DSP in FIG. 4. It is a flowchart. 10... Audio branch circuit, 11... Cumulative addition section, 12... Holding section, 13... Subtraction section,
14... Branch mode setting unit, 20... Audio branch circuit, 30... Audio branch circuit, 31... Digital signal processing processor (DSP
) 111... Adder, 113... Register, 121... First random access memory, 1
22...Second random access memory, DtyL...
・Digital audio input, I) out...Digital audio output, 1) ra...
Cumulative addition output, AD...address input.

Claims (1)

[Claims] 1. Digital voice input from multiple speakers (D_i_n
); a cumulative addition unit (11) that sequentially receives and cumulatively adds the
a holding section (12) consisting of a random access memory that receives and holds the digital audio input (D_i_n) and the cumulative addition output from the cumulative addition section (11);
); and a subtraction unit (13) that sequentially reads out the digital audio input (D_i_n) and the cumulative addition output from the holding unit (12) and calculates the difference between them.
3), a predetermined audio branched digital audio output (
D_o_u_t). 2. The cumulative addition unit includes an adder (111) and a register (111) forming a feedback loop for the adder (111).
13), and the holding unit (12) includes a first random access memory (12) that holds the cumulative addition output from the adder (111).
1) and a second random access memory (122) that holds the digital audio input (D_i_n), and the subtractor (13) extracts the second random access memory from the readout output from the first random access memory (121). An audio branching circuit according to claim 1, which subtracts the readout output from the access memory (122). 3. At least the cumulative addition section (11) and the holding section (12)
) and the subtraction section (13) are integrally constituted by a digital signal processing processor (31). 4. The digital audio input (D_i_n) is non-linear P
When given in the form of a CM code, it is once converted into a straight line PC.
When converting into an M code, processing it in the digital signal processing processor (31), and converting the processing result back into a nonlinear PCM code and outputting it, the straight line →
The digital signal processing processor (
31) The audio branching circuit according to claim 3, wherein the audio branching circuit is performed using a judgment instruction executed in step 31).