JPS6338397A - Serial data transmission circuit device - Google Patents

Abstract

A circuit arrangement, for serial data transmission via at least one bus, is made up of plural subscriber stations each having a time circuit, by means of which faulty seizure of the bus can be discontinued. In order to achieve the highest possible level of availability with a comparatively large number of subscriber stations, the bus is connected to a data transmission network via a coupling device which itself includes a time circuit for the discontinuation of faulty seizures of the data transmission network by the bus. The circuit arrangement can be used advantageously in monitoring devices of electrical information transmission technology in which a plurality of stations each containing a plurality of locating devices are connected to a control processor.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a self-contained serial data transmission circuit device VC according to the generic concept of claim 1.

BACKGROUND OF THE INVENTION The above-mentioned circuit arrangement is described in German Patent Publication No. 3A33150. This known circuit arrangement has a control circuit with two optocouplers connected in series with each other. It is equipped with a monitoring circuit that blocks all connections between the input side and the optocoupler.In this way, data transmission is blocked for all subscribers in the event of one static false signal. It is possible to avoid being exposed.

In such a circuit arrangement, the subscriber circuit is connected in parallel, so the probability of failure of the monitoring circuit is
The number of subscriber circuits connected to the bus (increases with the number of connected subscriber circuits. Therefore, in circuit devices with a relatively large number of tInIn circuits, the demands on the use of the circuit devices are very severe. !,”i, the actual requirements cannot be satisfied by known means.

Problems to be Solved by the Invention Problems to be Solved by the Invention Problems to be Solved by the Invention Problems to be Solved by the Invention Problems to be Solved by the Invention Problem to be solved by the present invention The purpose is to configure the system to improve usability.

For example, to have the possibility of detecting faulty subscribers.

Means for Solving the Problem In the present invention, a serial data transmission circuit device is configured as described in the characterizing part of claim 1.

The advantage of this configuration is that the serial data transmission circuitry is protected against static error signals from the subscriber circuitry and is also protected against defects from the control circuitry that block the data communication network. It is in the fact that

DE 64 36 441 A1 describes a serial data transmission type data communication device having a data communication network having a tree-shaped network configuration. In this case the stations exist at multiple network levels. A network node is provided with a signal concentrator that collects the signals for further transmission. Since the signal concentrator does not create connections between bus systems, the data communication network is not blocked by static false signals. However, in this case, it is necessary to provide a net), work node, etc.

In the circuit arrangement of the present invention, the static error signal 1 transmits the data to be transmitted statically, that is, continuously over a relatively long period of time. can be applied to and detected by a timed circuit that does not respond to transmitted signals that have a change in state following a change in state.

In one advantageous embodiment as claimed in claim 2, the monitoring circuit comprises a monitoring circuit for the case where the subscriber circuit transmits a pulse train having a maximum period that has been determined in advance. It is configured to respond if the maximum period given in advance is exceeded. In this case, the pulse train formed using, for example, a retriggerable monostable multivibrator is converted into a continuous signal, and this continuous signal is then monitored by a monitoring circuit. The arrangement according to claim 2 is particularly advantageous in that the bus has one data bus and one filt bus, so that the circuit is able to control the pulse train, given in advance (
This is a case in which it is necessary to evaluate only the logic level that can be applied to the control output side of the subscriber circuit or applied to the control bus in order to fully evaluate the maximum value of 8. The advantage of this configuration is that - the generated static error signal; :
,do. The 110 friend circuit or some subscriber circuits in question are no longer responsive. It can be used as a criterion for detecting lack of response and faulty subscribers. If the probability (probability ratio) that the supervisory circuit itself in one switching device is defective is extremely low, then there is a possibility that the supervisory circuit in any group of subscriber circuits at the central station is defective. It is possible to detect whether a subscriber circuit is assigned.

The desired forced interruption of the bus or data communication network is advantageously effected by means of the measures defined in claim 4.

With the configuration described in claim 5, it is possible to more easily detect a failure location.

This arrangement is particularly advantageous if groups of subscriber circuits, each connected to a common data bus, are co-located (for example adjacent).

An advantage of the configuration according to claim 6 is that the self-retention of the timer circuit can be terminated by pulling out the device with the self-retaining timer circuit from the storage device. by arranging the subscriber circuit and the supervisory circuit, or the switching device and the supervisory circuit, in one and the same piece of equipment, which in any case must be withdrawn from the accommodation device for necessary repairs in the event of a defect; The desired termination of this self-retention takes place automatically.

Self-retention of the timer circuit can advantageously be obtained by the arrangement according to claim 7.

With the structure described in claim 8, by simple means,
The subscriber circuit of the data bus or the switching device may not affect the data communication network if the bus is blocked for an unacceptable period of time.

Further advantageous embodiments of the invention are set out in patent claims 9 and 10.

EXAMPLES Next, the present invention will be explained in detail based on examples with reference to the drawings.

The circuit arrangement has stations 1 to m which are spatially separated from each other. By connecting one processor 51 . . . 5 m with one switch device 41 . . . 4 m, the system stations . All stations...m are data line connection equipment (transmission equipment) cabinet modems (transmission equipment) that are interconnected via connection lines 6a...6a to one data transmission network. MODEM) 6a...6d.

Stations...m exchange information via a data communication network.

Each subscriber 111...1mn has one subscriber circuit 3.
11...3 mn and one interfnice device 21
1...2mn.

The subscriber circuits 311...31n of the station 1 are connected to the data bus 101 via interface devices 211...2in. In station 2, subscriber circuits 621...32n are provided. These subscriber circuits 621...32n are connected to the data bus 102 via interface families ft221...22n.

Only the home station m of the other stations 6...m is shown. This station m is connected to a data bus 1 via an interface device 2ml...2mn.
Subscriber circuit 3ml...3 mn connected to 0m
It is equipped with

The subscriber circuits 311...3mn are, for example, processors 5
1..5m is a microprocessor-controlled device that starts data transmission when called by one of the processors. Depending on the case, only some of the stations . . . m are equipped with one processor 51 . . . 5 m.

CI? :, is controlled so that only transmission can be performed.

The station 1 is provided with a switch device 41 which connects the local bus 101, the processor 51 and the data transmission device or modem 61al.
61b can be switch-connected to each other.

The station 2 is provided with a switching device 42, which is used to switch the local bus 102 to a data transmission device or a modem 62al (621). Station m is provided with a switch device 4m, which can be used to connect a local bus 10m, a processor 5m, and a data transmission device or modem 6ma.

One switch device 41...4m is provided for each data bus.
It consists of nine transmit/receive modules and nine distribution circuits connected to a control bus. The distribution circuit connects one of the control lines
A logic circuit is configured such that a blockage signal arriving on a control line connects the data bus assigned to that control line through to the data buses of all other controllers.

In this way, it can be ensured that information sent by one of the subscribers is provided to all other subscribers.

The circuit arrangement shown in FIG. 2 is used for serial data transmission, in which all data sources and data transmitters are connected in parallel to one common bus line or one common bus 101...10.
It is part of one bus system installed at various locations, connected to m. The bus has, for example, an interface module R8485.

In the dormant state, all interface devices 21
The output side of 1...2 mn is switched to a high resistance.

Installed in various locations or at various stations
・Bus system 101...10 assigned to m
4m and the digital data transmission equipment 61a...6ma, or alternatively, in the event of a delay in the start of data transmission and via the modem to one data set. be done.

The sequential data transmission between the various subscriber circuits 311...3 mn is preferably carried out using so-called polling.
fverfahren). In this case, only one subscriber circuit in each case is called by one processor and the subscriber circuits thus called transmit data. After the end of the data transmission, the output of the interface device of the called subscriber circuit is again switched to high resistance.

Another method of performing sequential data transmission is to synchronize the subscriber circuits and control them to send messages sequentially in time steps. This can be done, for example, by means of counters installed in the subscriber circuit and set at various step times.

If, due to a defect in the subscriber circuit, this subscriber circuit transmits permanently, this subscriber circuit subsequently blocks the bus 101...10m after the expiry of the predetermined waiting time. be prevented.

During each polling in each interface device 211...2 mn, the period of data transmission of the corresponding subscriber circuit is monitored. The period of data transmission following one poll is a predetermined waiting time t1
If this value is exceeded, the connection of the subscriber circuit to the bus system is forcibly interrupted. This connection can be interrupted, for example, by providing an electronic switch between the output of the interface device and the output of the bus line, which is connected through during signal transmission.

Such a circuit arrangement for connecting a subscriber circuit to a bus line is described in European Patent Application No. 0 150 457.

If the interface devices 211...2 mn use interface modules that can be selectively activated or put into a high-resistance state by a control signal, these interface modules are additionally connected to a corresponding monitoring circuit. It is preferable to control the number of times as many as 8.

Such a circuit arrangement is shown in FIG.

In order to easily detect a defective subscriber circuit 311...3 mn, it can be indicated by an indicator lamp and an alarm signal can be generated.

In FIG. 2, an interface circuit with a monitoring circuit is shown for a bus line of the RE148-5 type.

The subscriber circuit 311 has one data input 61 , one data output 62 and one control output 66 . The control output side 66 is directly connected to the input side of an AND circuit 82 and is connected to the input side of an AND circuit 84 via an inverter 83. The time limit circuit 81 is an AND circuit 82
one output 81 connected to one input of the AND circuit 84 and to the input of the display device 89
It has 2. The timer circuit 81 is, for example, a timer element of the CD4541 type, and includes a clock oscillator whose clock frequency is determined by an external connection circuit 81a.

The output side of AND circuit 84 is connected to the control input sides of interface modules 85 and 86. The type of these interface modules 85 and 86 is, for example, 5N75176. The output side of the interface module 85 is connected to the control bus 101a, and the output side of the interface module 86 is connected to the blade side bus 101.
data bus 101b. The interface module 86 is connected both to the data input 61 and to the data output 62 of the subscriber circuit 311 . The data input 61 is connected via a high resistance R to the supply voltage +5.

When the subscriber circuit 311 is polled by the processor 51, data from the data bus 1011 (data bus 1011) is sent to the subscriber circuit 31 via the interface module 86.
1 data input 61.

When the time limit circuit 81 is in the reset state, a logic level H is taken out from the output side 812 of the time limit circuit 81, so the AND
Circuits 82 and 84 are open to a blocking signal coming from control output 63. When the subscriber circuit 311 transmits data to the processor, the control output 66 becomes active and the control output 63 switches from the logic level {circle around (2)} to L. A logic level H is taken from the output of the inverter 83 and is applied via an AND circuit 84 to the control inputs VC of the interface modules 85 and 86. In this way, the data output 62 of the subscriber circuit 311 is connected to the data bus 1oibvc and the control bus 101a is switched into the active state. At the same time, timer circuit 81 is activated via AND circuit 82.

If the transmission time of the subscriber circuit 311 exceeds the predetermined waiting time, the logic level at the output 812 of the timing circuit 81 switches from H to L and the AND circuit 82
and prevent 84.

If AND circuit 82 is blocked, time limit circuit 81 cannot be activated via subscriber circuit 3110 control input 66 and output 812 is at logic state 11. In this state, the AND circuit 84 switches the symmetrical outputs of the interfaces 85 and 86 to high resistance irrespective of the logic level at the control output, so that the control bus 101a and the data bus 101b are connected to the input 61 and output of the subscriber circuit 311. The bus line 101, which is disconnected from the subscriber circuit 62, is not loaded by the interface module 85, 86 assigned to the subscriber circuit 311.

The response of the monitoring circuit 8 is displayed via the display device 89, and an alarm signal is sent via the terminal 811.

When the interface device 211 is withdrawn from the containment device and reinserted into the containment device, the timer circuit 81 is reset, since the automatic reset terminal 816 is connected to ground potential. In this case, a logic level H is available at the output 812, so that the initial state is established again.

FIG. 6 shows a switching device with a monitoring circuit. The time limit circuit 91 of the switch device 41 differs from that shown in FIG. 2 only in its construction. After this waiting time, the desired strong SIIg disconnection occurs.

In the case of the circuit arrangement shown in FIG. 1, one monitoring circuit is provided for monitoring the control lines assigned to the switch devices 41...4mVC and the data buses 101...10nn. Depending on the case, the data lines themselves are monitored. This takes place, for example, in bus systems where no specific control lines are provided. If several data buses are connected to one switching device, it is advantageous to provide a separate monitoring circuit for each data bus.

One interface! If the control bus of 211...2 mn color is blocked for a time longer than the set time t2, the data bus is disconnected from the station 1, 21 tall m (D switch device and other data communication networks). be separated.

The switch devices 41...4m are similarly configured.

FIG. 3 shows the configuration of the switch device 41 as an example. The monitoring circuit 9 is provided between the bus 101 and the distribution circuit 40.

The bus 101 includes a control bus 101a and a data bus 101b. The control bus 101a is, for example, Ds8.8.
It is connected to a level converter 97 of the type Ls120. The output side of level converter 97 is directly connected to one input side of NAND circuit 940 and, via inverter 96, to one input side of AND circuits 92 and 95.

The output side 912 of the timer circuit 91 is an AND circuit 92 and 9
5, one input side of the NAND circuit 94, and one input side of the display device 99.

Timing element 91 is, for example, a timer of the CD45410 type and has one clock generator, the clock frequency of which is determined by external connection circuit 91a. The output of the NAND circuit 94 is connected directly to the control input 981 of the interface element 98 and via the inverter 96 to the fljlJ 151 input 402 of the distribution circuit 40. Interface element 9
8 is a module for tights of 5N75176, for example. The output side of the interface element 98 is the data bus 10
1b.

Subscriber circuits 311...3 connected to bus 101
If the transmission time of 1n exceeds the waiting time of the supervisory circuit 9 due to a failure of the corresponding supervisory circuit 8, the output side 9 of the time limit circuit 91
The logic level at 12 transitions from H to L, blocking AND circuits 92 and 95 and NAND circuit 94.

By blocking the AND circuit 92, the timer circuit 91 cannot be started via the control bus 101a and the output 912 is at a logic state of 1.

In this state, the NAND circuit 94 is connected to the control bus 101a.
The control lines 401 and 402 of the distribution circuit 4D are not blocked by the bus 101 because the logic level is switched to (2) regardless of the level of The data bus 101b is the data line 406 of the timer circuit 40.
It is separated from ゜404.

The monitoring circuit 9 includes a distribution circuit 40 and a switch device 41.
It is located inside. When the switching device 41 is withdrawn from its housing and reinserted, the timer circuit 91 is reset, since the automatic reset terminal 913 is connected to ground potential. In this case, output side 9
12 assumes the logic level H, so the initial state is re-formed.

Subscriber circuits 311...3 connected to bus 101
One subscriber circuit of 1n connects to the data bus 1
01b to the switching device 41, the subscriber circuit in question previously activates the control bus 101affi, ie so that a logic level H is taken from the output of the level converter 97. In this way NAND
Via element 94, a logic level L is applied to a control input 981 of interface element 98, the receiver of which is switched internal. In this switching state, the data bus 101bU switch device 41
The processor 51 is connected to a data transmission device or modem 61a, 61b via a data line 404 and a distribution circuit 40.

At the same time, a logic level L is applied via the inverter 96 and the AND circuit 92 to the reset input 911 of the timer circuit 91, so that the timer circuit 91 is started.

If the transmission time of a subscriber circuit 311...31n exceeds the predetermined waiting time of the timing circuit 91, the output 912 of the timing circuit 91 takes a logic state. This logic level blocks AND circuit 92 so that the timer circuit locks itself. At the same time, a logic level H is applied via the NAND circuit 94 to the control input 981 of the interface element 98, the receiver in the interface element 98 is blocked and the control input 402 of the distribution circuit 4Q is disconnected from the control bus 101a. . Also, 6 people AND
The control output 401 of the distribution circuit 40 is also disconnected from the control bus 101a by the circuit 95, and the interface element 9
The control line connected to the fftlJ input side 982 of 8 becomes a logic level L, and as a result, the interface 2
The output side of the transmitter of child 98 is switched to a high resistance so that no data collisions occur on data bus 101b.

The response of the monitoring circuit 9 is displayed on the display device 99, and an alarm signal is sent out via the terminal 991.

By determining the waiting times t2 and tl so that t2 is larger than tl, it is ensured that the monitoring circuits 9 of the switching devices 41...4m will respond unless a failure occurs in the monitoring circuits 8 of the interface devices 211...2mn. You can prevent it from happening.

The serial data transmission circuit arrangement shown in FIGS. 1 to 6 is used, for example, to transmit data from a number of stations to a processor used as a central control circuit and an evaluation circuit. It is suitable for netting.

In one advantageous use case, at one station,
In each case, a predetermined number of line terminal devices of an information transmission device including all so-called CFF1 catering devices are provided. Each locating device is equipped with a microprocessor which evaluates the error messages of the system-specific monitoring devices and sends them to the central processor in response to inquiries.

By forcibly shutting down a defective locating device or a defective interface device in a monitoring device in a time-staggered manner, the central processor sends operating status messages, error messages, alarm signals, etc. to the locating device. It is also possible to detect the occurrence of a defect in one of the locating devices and/or in the monitoring circuit assigned to this locating device, which may disrupt the data network.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram in which multiple bus systems are integrated into one data communication network. Figure 2 shows the first
The circuit device shown in the figure is an interface device having a monitoring circuit, and FIG. 6 is a switching device having a monitoring circuit. m...Station, 1mn...Subscriber, 2mn...
・Interface device, 3mn...Subscriber circuit, I
D mn...Data bus, 4m...Switch device, 5m...Processor, 6ma...Data transmission equipment or modem, 6d...Connection line, 311...Subscriber circuit, 61. - Data input side, 62... Data output side, 66... Control output side, 211... Interface device, 8... Monitoring circuit, 81... Time limit circuit, 8
12... Output [ttL813... Automatic reset terminal, 82... AND circuit, 83... Inverter, 84
... Melon circuit, 85.86 ... Interface device, i, o, i ... Bus, 101a ... Control bus,
101b...data bus, 41...switch device,
4o...Distribution circuit, 51 river processor, 61a +
61b...modem, 91...time limit circuit, 91a...
・External connection circuit, 92...AND circuit, 99...display circuit, 96...inverter, 94...NANDA
ND circuit...AND circuit, 96...Inverter, 97...
-Level converter, 98...interface element.

Claims (1)

[Claims] 1. A serial data transmission circuit arrangement between a number of subscribers (111...1mn) via at least one bus (101...10m), comprising: 111...1mn) respectively connect one subscriber circuit (311...3mn) and the subscriber circuit (311...3mn).
One interface device (211...2) connecting the bus (101...10m) to the bus (101...10m)
mn) and one monitoring circuit (8) having one timer circuit (81), and using the monitoring circuit, the bus (101...10m
) is erroneously blocked by the subscriber circuit (311...3mn), the serial data transmission circuit arrangement is capable of resolving this blockage after expiry of a previously given waiting time. In the above, the bus (101...10m) is connected to one switch device (41...4m) that selectively connects one bus to one data transmission circuit network, and the switch device (41...4m) selectively connects one bus to one data transmission circuit network. ...4m) is equipped with one monitoring circuit (9) comprising one timer circuit (91), and using said monitoring circuit (9), the data transmission network (6a
. . 6d) is blocked by the bus (101 . 4m) is assigned to the monitoring circuit (
9) The waiting time of the subscriber (111...1mn)
A serial data transmission circuit device characterized in that the waiting time is set to be greater than the waiting time of the monitoring circuit (8) provided in the serial data transmission circuit device. 2. A subscriber circuit transmits a pulse train having a pre-given maximum period, and causes a monitoring circuit to respond if said pre-given maximum period is exceeded. A serial data transmission circuit device according to claim 1, configured as follows. 3. In the monitoring device (8) assigned to the subscriber (111...1mn) and/or in the switching device (4
Claim 1 or 2, in which the timer circuit (81, 91) in the monitoring circuit (9) assigned to the monitor circuit (1...4m) is provided with a self-holding device (AND circuit 82, 92). The serial data transmission circuit arrangement described. 4. Reset input side (811) of time limit circuit (81, 91)
.
81, 91) and connected to the output side (812, 912) of the serial data transmission circuit device according to claim 3. 5. Monitoring circuit (8) and/or switch device (41...4) provided in subscriber (111...1mn)
A monitoring circuit (9) provided in said monitoring circuit (8, 9) is connected to said monitoring circuit (8, 9).
89, 99), and the display and/or alarm device (89, 99) displays or transmits the response state of the monitoring circuit (8, 9). any one of the terms
The serial data transmission circuit device described in . 6. The timer circuit (81, 91) is connected to the timer circuit (81, 91).
91) is configured and/or connected in such a way that it is reset in the event of a temporary interruption of the supply voltage (+). circuit device. 7. A timer circuit (81, 91) is formed by one counter connected to one clock generator, the output side (812, 912) of said counter being connected before the reset input side (811, 911). Any one of claims 1 to 6 connected to the AND circuit (82, 92) connected to the
The data transmission circuit device described in . 8. The output side of the monitoring circuit (8) is connected to an AND circuit (84) which is pre-connected to the bus, and the bus (101) has one data bus (101b) and one control bus ( 101a), and the subscriber circuit (311) is equipped with one interface element (
85, 86) to the control bus (101a) and data bus (101b), and the control input side of the interface element (85, 86) is connected to A.
Connected to the ND circuit (84) (Fig. 2) Any one of claims 1 to 5
The serial data transmission circuit device described in . 9. The bus (1) connected to the switch device (41)
The control bus (101a) from 01) connects one level converter (97), the level converter (97) and the monitoring circuit (9).
) is connected to the control input side (402) of the distribution circuit (40) via a logical combination circuit (94) in the form of an AND circuit, which is connected to the output side of the three-input AND circuit (95). The three-input side AND circuit (95) connects the output side of the monitoring circuit (9), the output side of the level converter, and one of the distribution circuits (40) via one input side, respectively. Control output side (40
1), and the three-input side AND circuit (95) is connected to one control input side (95) of the interface element (98) via its output side.
82), and the interface element (
98) is provided between the data bus (101b) and the distribution circuit (40) via its transmitter and its receiver, respectively. or1
The serial data transmission circuit device described in . 10. Any one of claims 1 to 9 for use in a data transmission network that allows data from a plurality of stations to be transmitted after polling to one central control and evaluation device.
The serial data transmission circuit device described in .