JPS6336465A - Dma transferring method - Google Patents

Abstract

PURPOSE:To save the time to be spent for setting an unnecessary parameter and to improve a processing speed by detecting a specified transferring condition based upon a flag, and setting a necessary parameter only at the time of the next transferring. CONSTITUTION:When the transferring of DMA is the one from a pattern memory 3 to a VRAM 5, a flag 60 is hoisted, and namely, '1' is displayed. A CPU 1 outputs a starting signal to a DMA controller 4, a DMA transferring is started and thereafter, the DMA controller 4 controls a transferring action. After the transferring is completed, the CPU 1 executes the parameter counting for the next transferring based upon the request, etc., from the external part. Next, the CPU 1 checks the condition of the flag 60. When a flag is not hoisted, the transferring with the highest frequency is not obtained, therefore, all parameters are reset to a transferring mode register 50, and when the flag is hoisted, it is proved that the transferring with the highest frequency is obtained, therefore, the setting of the parameter is a source address and a destination address only. Thus, the efficiency of the setting of the parameter can be improved.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial usage volume) The present invention relates to a DMA transfer method.

(Prior art) Direct Memory A (Direct Memory A) is a technology for transferring the contents of one memory to another memory.
(ccess) method is known. If this is normally done - loading data into HCPLI and then allocating that data to destination memory, it would require two stages of processing, increasing the transfer time, and requiring less CPU time.
is occupied for transfer processing, so direct transfer is performed between memories.

Generally, in DMA transfer, a DMA controller for transfer control is placed between memories to be transferred, and control of the address bus, data bus, and control bus is transferred to this DMA controller. For this reason, DMA
When moving to transfer mode, CP Ll G,t DM
Each parameter necessary for DMA transfer is set for the A controller, and then it is activated to shift to DMA transfer. Here, the parameters to be set include, for example, the address of the transfer source (source), the transfer destination (
destination) address, number of repeated transfers,
There are various types such as transmission/reception magnification (duty ratio between transmission time and reception time).

By the way, conventionally, such parameter settings are all newly set each time DMA transfer is performed. This is because the CPU side does not particularly monitor the immediately preceding transfer status.

(Problems to be Solved by the Invention) However, it is often the case that the parameters set for DMA transfer are different from the previous transfer only for the source and destination, and the others are the same. In such a case, there is a problem that the transfer efficiency is low because all parameters are set even though most of the parameters that were set during the previous transfer are the same.

The present invention is a DMA that can improve the inefficiency of parameter settings and improve the speed of the entire processing system.
The purpose is to provide a transfer method.

[Structure of the invention]

(Means for Solving Problems) In the DMA transfer method according to the present invention, a transfer state is set in a flag arranged in parallel in a transfer mode register for setting transfer control parameters, and the flag is set at the start of the next transfer. The feature is that only necessary parameters are set according to the content.

(Function) According to this MA transfer method, the previous transfer status can be checked, so for example, if the previous transfer and the current transfer are between the most frequently used memories, a flag is set. Since it is not necessary to reset most of the parameters, it is possible to improve the processing speed.

(Embodiment) FIG. 3 is a block diagram of a DMA transfer system to which the present invention is applied.

According to the figure, the CPU i and the main memory 2 are connected by a data passco 1, an address bus 12, and a control bus 13, and a DMA controller is connected to these buses. This DMA controller 4 includes a data bus 21, an address bus 22, and a control bus 23.
A pattern memory 3 consisting of a read-only memory (ROM) is connected to the VRAM 5 via a data bus 31, an address bus 32, and a control bus 33. The parallel output of this VRAM 5 is converted into serial data by a shift register 6 and sent to a CR7 display 7. Here, pattern memory 3 is CR
Character information to be displayed on T7 is stored, and address information and control signals from the DMA controller 4 are sent to bus 2.
2 and 23, the character information is output to the bus 21 and transferred to the VRAM 5 or main memory 2 via the DMA controller 4.

FIG. 2 is a configuration diagram showing a group of internal registers of the DMA controller, which play an important role in the present invention. According to the figure, a transfer mode register 50 is provided which is set by CPLJl, and its most significant 1 bit is flag 6.
It is 0.

This flag is set, for example, in the case of inter-memory transfer, which is the most frequently used transfer.

The DMA transfer method according to the present invention will now be described with reference to FIG. 1, assuming that DMA transfer from the pattern memory 3 to the VRAM 5 is the most frequent transfer. Incidentally, FIG. 1 is a flowchart showing the processing performed by the CPtJ 1 alone or with respect to the DMA controller 4.

First, CPLll sets all parameters necessary for the first DMA transfer to the DMA controller 4 through the bus 11, 12, 13 in the transfer mode register 50 (step 101). As described above, these parameters include the source address, destination address, number of repeated transfers, transmission/reception magnification, and the like. If the transfer at this time is from the pattern memory 3 to the VRAM 5, the flag 60 is set, that is, it is set to 1''.

After the parameter setting is completed, the CPU 1 outputs an activation signal to the DMA controller 4, and DMA transfer is started. From then on, the DMA controller 4 controls the transfer operation (step 102).

After this transfer is completed, CPIJl calculates parameters for the next transfer based on an external request or the like (step 103).

Next, CPU 1 checks the state of flag 60 (step 104). If the flag is not set, this is not the most frequent transfer, so all parameters are reset in the transfer mode register 50 (step 106).
If the flag is set, it is known that the transfer is the most frequent, so set the parameters only for the source address and destination address (Step 1).
05). This eliminates the need to set unnecessary parameters, reduces parameter setting time to a fraction of the time, and
The PU occupation time is also reduced.

After setting the parameters, the CPU 1 activates the DMA 4 to start the transfer again (step 107), and the transfer is performed.

After confirming the completion of the transfer (step 108), steps 103 to 108 are repeated until the transfer is completed.

In the above embodiment, the flag is set as one bit and the flag is set for the most frequently used transfer between memories, but if the number of flag bits is multiple, the transfer status (type)
As a result, parameter settings can be simplified.

In the embodiment, the transfer mode register exists in the DMA controller 4, but it is not necessarily necessary, and may exist in the main memory 2, for example.

As described above in detail based on the embodiments, according to the present invention, a specific transfer state is detected based on a flag,
Since only necessary parameters are set during the next transfer, time for setting unnecessary parameters can be saved and processing speed can be improved. Furthermore, since the time occupied by CPLJ for parameter setting is reduced, the speed of the entire processing system can be improved, especially in systems operating on cell tasks.

[Brief explanation of drawings]

Figure 1 is a flowchart showing the operation of the present invention, Figure 2 is an explanatory diagram showing the transfer mode register and flags, and Figure 3 is an explanatory diagram showing the transfer mode register and flags.
The figure is a system diagram showing a system to which the present invention is applied. 1... CPU, 2... Main memory, 3... Pattern memory, 4... DMA controller, 5... VRA
M. 50...Transfer mode register, 60...Flag.

Claims (1)

[Claims] 1. In a DMA transfer method in which information is transferred directly between memories by a DMA controller, a specific transfer state is set in a flag arranged in parallel in a transfer mode register for setting transfer control parameters. . A DMA transfer method characterized in that only necessary parameters are set according to the contents of the flag at the start of the next transfer. 2. The DMA transfer method according to claim 1, wherein the transfer state set in the flag represents transfer between frequently used memories. 3. The DMA transfer method according to claim 1, wherein the necessary parameters are a source address and a destination address. 4. The DMA transfer method according to claim 1, wherein the transfer mode register is located within the DMA controller. 5. The DMA transfer method according to claim 1, wherein the transfer mode register is located in the main memory.