JPS6334665B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to correction of ternary decision identification errors in bipolar code transmission.

In bipolar transmission, a binary signal sequence, which is transmission information, is converted into a ternary signal sequence and sent out.
When converting from binary to ternary value, when a binary signal “0” is input, “0” is input, and when a binary signal “1” is input, “1” and “-1” are input. Sent alternately. Therefore, a prohibition rule holds that "1" or "-1" cannot occur consecutively without a sign of opposite polarity between them. Due to the above properties, an error detection circuit that detects a single bit error in bipolar transmission can be constructed. As a means for correcting this error, a most probable correction is performed by extracting and correcting the signal with the largest error among the received signals.

For example, if the sequence 1, 0, 0, 0, 1 is identified, it is considered that errors are included in these five signals. In this case, it is considered that either the first or last one is mistaken for "1", or one of the three is "-1" mistaken for "0". Therefore, in this case, the maximum error occurrence time memory circuit detects the maximum error in absolute value in the negative direction in this section, and the correction circuit corrects the identification signal at the detected time to correct the error. Corrections can be made.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal discriminator capable of correcting identification errors using bipolar code prohibition rules.

According to the present invention, by storing the time at which an error occurs, the range of the error can be specified, and therefore reliable correction becomes possible.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The received signal coming from terminal 1 is sent to threshold circuit 2.
The signal is identified as three values "1", "0", and "-1" and the identification signal is input to the delay circuit 3. The delay circuit 3 receives a delay corresponding to a time slot sufficient to detect and correct the error, and its output signal is input to the error correction circuit 4. On the other hand, the received signal supplied from the terminal 1 and the output identification signal of the threshold circuit 2 are input to the maximum error occurrence time storage circuit 6. In the memory circuit 6, an error signal is obtained from the two input signals at each time, and the maximum error signal in the interval from the occurrence of "1" or "-1" to the occurrence of the next "1" or "-1" is determined at each time. The time of occurrence of the value is stored. The identification signal output from the threshold circuit 2 is also input to the error detection circuit 7, and error detection is performed using the bipolar prohibition rule. That is, it is detected that symbols of "1" or "-1" are consecutive without intervening symbols of opposite polarity, and information about the error occurrence interval indicating the interval is output. The output signals of the storage circuit 6 and the detection circuit 7 are both input to the error correction circuit 4. In the error correction circuit 4, when an error is detected in the detection circuit 7, the delayed identification signal is corrected at the time indicated by the output of the storage circuit 6, and a correct identification signal is outputted to the terminal 5.

The present invention is carried out as described above, and the error detection circuit 7, maximum error occurrence time detection circuit 6,
A more detailed embodiment of the error correction circuit 4 will be shown.

FIG. 2 is a block diagram showing one embodiment of the error detection circuit. The identification signal created by the threshold circuit 2 enters the terminal 77, and the value is written into the register 71 only when "1" or "-1" is entered. In the comparison circuit 72, the identification signal input from the terminal 77 and the output signal of the register 71 are compared, and only when they match, "1" is output, otherwise "0" is output, and this becomes an error detection signal and is sent to the terminal 711.
is output to. In other words, only when "1" or "-1" arrive at the output of the identification signal consecutively without "-1" or "1" in between, "1" is output from 72, and this is an error. It becomes a detection signal.
On the other hand, counter 73 is operated by a clock representing the interval of signals coming from terminal 78, and is reset when the identification signal is "1" or "-1". The counter output is input to a decoder 75 via a parallel register 74. decoder 75
Then, "1" is outputted to an appropriate output depending on the value represented by the output of the register 74. In other words, the output of the parallel register 74 always has a "1" or "-" in front.
After obtaining the identification signal of "1", the number of consecutive "0"s is output. If continuous reception of "1" or "-1" occurs, the consecutive "1" or "-1" is received as an error occurrence interval. Consider an interval in which "-1" and "0" in between are added.For example, if the output of register 74 represents 3 when an error occurs, add "1" or "-1" at both ends. Since the error occurrence interval is 5 symbols, the decoder 75 outputs "1" to the five outputs from the left, and similarly, if it is 5, "1" is output to the seven outputs. The shift register 76 can switch between parallel and serial inputs, and if the output is "0" according to the output of the comparator circuit 72, it becomes a normal shift register that inputs "0" from the terminal 79, and the output of the comparator circuit 72 becomes "1". ”
If so, the logical sum of the output of the decoder 75 and each preceding stage output is input in parallel. In this way terminal 7
A signal indicating the error occurrence section when an error occurs in 10 is generated and output to the error correction circuit 4. Here, the number of stages of the shift register 76 must match the amount of delay of the delay circuit 3.

FIG. 3 is a block diagram showing an embodiment of the maximum error occurrence time storage circuit 6. In FIG.

In this figure, the terminal 61 receives the received signal branched from the terminal 1 in FIG. 1, the terminal 62 receives the identification signal 10 output from the identification circuit 2 in FIG.
The error detection signal obtained by the error detection circuit 7 shown in the figure, that is, the output signal of the terminal 711 shown in FIG. 2, is supplied respectively. The received signal coming from the terminal 61 and the identification signal coming from the terminal 62 are subtracted by a subtracter 66 to produce an error signal. In addition, the latch circuit 6
20 is latched when the identification signal "1" or "-1" is received. Sign inversion circuit 61
Reference numeral 9 inverts the sign of the error signal generated by the subtracter 66 according to the latch output when the latch output is "1", so that only positive error detection is possible for that output. It would be a good idea to do this. The comparison circuit 610 compares the error signal with the maximum error output from the storage circuit 69. When the error signal input to the comparison circuit is large, it outputs "1", thereby causing the storage circuit 69 to invert the sign. The new maximum error coming from circuit 619 can be written. The memory circuit 69 also has a reset terminal, and the reset signal is generated as follows. The identification signal input from the terminal 62 is input to the selection circuit 68 as is, and is also input to the circuit 68 via the register 67. In the selection circuit 68, selection is made based on the error detection signal obtained from the error detection circuit 7 that comes from the terminal 63, and when the signal is "1", the signal passed through the register is "0". The identification signal is selected as is and input to the converter 624. In the converter 624, when "1" or "-1" is received, "1" is converted to "0" when "0" is received, and a binary signal is output. This converter output and a signal obtained by delaying the error detection signal by one signal interval in a register 623 are logically summed by an OR circuit 622, and the output thereof becomes a reset signal. With this circuit configuration, the reset signal is reset every time "1" or "-1" is identified if no error is detected, and is delayed by one signal interval if an error is detected. The maximum error can be detected within all the sections where an error may occur. Next, the counter 611 operates using a pulse representing one signal interval input from the terminal 64 as a clock, and is reset by the reset signal. Both registers 618 and 617 are parallel registers with a 1-bit delay, but register 61
8 is updated every 1 signal interval, register 617
are updated each time the maximum error is detected, and both enter the subtracter 612. In subtracter 612, the output signal of register 618 is subtracted from the output signal of register 617, and its output is therefore a signal representing how many signal intervals ago from the present time the maximum error occurred. On the other hand, the shift register 614 is a parallel-serial switching type shift register, and a reset signal delayed by the register 616 signal interval is input as a switching signal. When the switching signal is "0", the switching circuit operates as a normal shift register that uses the "0" signal at the terminal 621 as a serial signal, and the switching circuit is "1".
In this case, the signal indicating the position of the maximum error appearing in the output of the subtracter 612 is sent to the decoder 61
3, and the signal only at the relevant position is “1”
The signal becomes the parallel input of the shift register,
This input is ORed with the previous stage signal of each register of the shift register and input to the next stage register. In this way, the correct maximum error occurrence time is output to the terminal 65 and input to the error correction circuit 4.

FIG. 4 is a block diagram showing a fourth embodiment of the error correction circuit. 4, a terminal 41 receives the output of the delay circuit 3 shown in FIG. 1, a terminal 42 receives a signal indicating an error interval output from the terminal 710 shown in FIG. A signal indicating the maximum error occurrence time outputted from 65 is supplied to a terminal 46 to obtain a corrected identification signal. Further, the terminal 46 is the same as the terminal 5 in FIG.
In FIG. 4, the delayed identification signal coming from terminal 41 is input to converter 45. In FIG. The AND circuit 44 calculates the logical product of the signal representing the error interval coming from the terminal 42 and the signal representing the maximum error occurrence time coming from the terminal 43, and inputs the result to the converter 45 as a converted signal. When an error occurs, the AND circuit 44 outputs "1" only at the time when the maximum error occurs, that is, at the time when the possibility of an error is highest. In the converter 45, only when the conversion signal is "1", "0" is converted to "1" or "-1", and "-1" or "1" is converted to "0", and the signal is corrected to the terminal 46. An identification signal is output. In these circuit configurations, circuits having substantially similar functions such as a shift register and a counter are included between the error detection circuit and the maximum error time storage circuit, but a configuration in which these circuits are used as a common circuit is also possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing an error detection circuit in this embodiment, FIG. 3 is a block diagram showing a maximum error occurrence time storage circuit in this embodiment, and FIG. 4 is a block diagram showing an embodiment of an error correction circuit. In the figure, 2 is a threshold circuit, 3 is a delay circuit, and 4 is a threshold circuit.
is an error correction circuit, 6 is a maximum error occurrence time storage circuit, 7 is an error correction circuit, 71, 74, 67, 62
3,618,617 are registers, 620 are latch circuits, 73,611 are counters, 75,613 are decoders, 76,614 are shift registers, 68
66 and 612 are selection circuits, 66 and 612 are subtracters, 69 are storage circuits, 72 and 610 are comparison circuits, 619 is a sign inversion circuit, 624 and 45 are converters, 44 is an AND circuit, and 622 is an OR circuit.

Claims (1)

[Claims] 1. A receiver used for bipolar code transmission includes a threshold circuit that obtains identification signals corresponding to three values of "1", "0", and "-1" from a received signal, and a threshold circuit that obtains identification signals corresponding to three values of "1", "0", and "-1" from the received signal, and 1” indicates that a signal of opposite polarity is received continuously without any intervening signal, and “1” or “-1” indicates an interval in which a signal of opposite polarity is continuously received without any intervening signal. an error detection circuit that outputs a signal indicating the error detection signal, and an error detection circuit that outputs a signal indicating the error detection signal detected from the received signal and the identification signal between the occurrence of "1" or "-1" and the occurrence of the next "1" or "-1". a maximum error occurrence time storage circuit for storing the occurrence position of the maximum error value; a delay circuit for delaying the identification signal to obtain a delayed identification signal; and a maximum error occurrence time storage circuit for storing the delayed identification signal using the output of the error detection circuit. A signal discriminator comprising an error correction circuit that corrects at a time stored in the circuit to obtain a correct discrimination signal.