JPS6332316B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for detecting a signal reception error rate in a receiving device that receives a binary multiplexed information signal, such as a teletext signal, which is transmitted superimposed on a television signal.

Information transmission systems in which multiplexed information signals are superimposed and transmitted during the vertical retrace period of a television signal are being put into practical use, one of which is a teletext system. This system generates a clock run-in signal, a framing code signal, a program code signal, and a Control signals such as line number code signals and pattern signals for one line or arbitrary column of character patterns to be transmitted are multiplexed and transmitted as binary signals, and on the receiving side, these two
By receiving a television signal in which value information signals are multiplexed, extracting only the binary information signal, and controlling the receiving circuit by detecting the control signal, the transmitted pattern signals are arranged in a predetermined order. The information is stored in a memory and then read out from the memory to display character pattern information on a cathode ray tube or the like. In addition, in the United Kingdom and other countries, there is a similar information transmission system called the Teletext System, which is a simultaneous system except that character patterns are coded for each unit character or figure rather than as a pattern signal. The information is multiplexed with the television signal as a binary information signal and transmitted.

Now, in such a system, as mentioned above, the receiving device extracts the binary information signal that is multiplexed into the television signal, and performs the necessary signal processing such as recording and playback in the memory, thereby transmitting the information. In order to receive accurate information during reproduction, it is necessary to accurately receive the binary information signal multiplexed with the television signal.

Therefore, it is an object of the present invention to provide a device that can easily and accurately detect how accurately the binary information signal is being received, or in other words, how much reception error has occurred. The purpose is to

Therefore, in the present invention, when a pseudorandom signal for testing, such as a PN code signal, is multiplexed as a binary signal and transmitted to the television signal, it is possible to A signal (comparison signal) of By counting the number of discrepancies,
The present invention is characterized in that the reception error rate of a binary information signal is detected.

Furthermore, the present invention is characterized in that when the reception error rate thus detected is equal to or higher than a predetermined value, the detection operation is automatically re-performed to more accurately detect the reception error rate. It is something.

EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment thereof.

In the figures, FIG. 1 shows a schematic configuration of a teletext receiver to which a reception error rate detection device according to an embodiment of the present invention is applied, and FIGS. 2 and 3 show a schematic configuration and specific details of the reception error rate detection device. A circuit example is shown, and the fourth
The figure shows the waveform diagram of each part.

First, in this teletext system, during normal text information transmission, as shown in Figure 4A,
A binary information signal is multiplexed and transmitted at the 20th H and 283rd H (hereinafter, both will be referred to as the 20th H) during the vertical retrace period of the television signal. This signal consists of a control signal and a pattern signal, the former includes a clock run-in signal,
It includes reception control signals such as a framing code signal, program code signal, page code signal, line code signal, etc., and the latter includes a character pattern signal for one line or arbitrary column of character information to be displayed. Both are transmitted as binary signals. For the latter, a code signal representing a pattern such as a character may be used.

Next, an overview of a receiving apparatus for receiving such a teletext signal will be explained with reference to FIG.
First, a television signal in which binary information signals as described above are multiplexed is received by the antenna 1, and converted into a multiplexed video signal by the tuner/VIF and the video detection circuit 2. Furthermore, the waveform equalization circuit 3 compensates the waveform of the binary information signal portion to a predetermined correct waveform,
Subsequently, the waveform shaping circuit 4 slices the signal into a binary signal waveform. After that, gate circuit 5
, only the portion of the binary information signal multiplexed at the 20th H is gated and extracted, and sampled by the sampling circuit 6 using the sampling clock to obtain two signals at a predetermined pulse position and a predetermined pulse width.
Obtain the value information signal. The binary information signal thus obtained is added to a signal processing circuit 8 including a memory 7 and a circuit for controlling the memory 7, which identifies a control signal among the received signals to control the memory 7, and processes the pattern of the received signal. The signals are written and stored in a predetermined position in the memory 7 in a predetermined order. The memory 7 has a storage capacity capable of storing pattern signals necessary to display character patterns for one screen or one line. Finally, the pattern signal is read out from the memory 7, amplified by the amplifier circuit 9, and then applied to the cathode ray tube 10, thereby displaying the transmitted character information pattern on the screen.

In addition, in order to control the above reception operation, the synchronization separation circuit 11 separates the horizontal and vertical synchronization signals, and based on this, the gate pulse generation circuit 12 generates a gate pulse at the 20th H and applies it to the gate circuit 5. . On the other hand, a color subcarrier generating circuit 13 reproduces a color subcarrier synchronized with the color burst signal, and a basic clock generating circuit 14 multiplies and divides this color subcarrier to create a basic clock. Furthermore, using this basic clock, a sampling clock generating circuit 15 generates a sampling clock having the same frequency as the data rate of the received signal and synchronized with the clock run-in signal and the framing code signal in the received signal. In addition, the main clock generating circuit 16 generates and supplies a main clock for driving the signal processing circuit 8.

Incidentally, since such teletext receiving apparatus 17 itself is well known, a detailed explanation of each part will be omitted.

As described above, the teletext receiving device 17 receives the binary information signal that has been multiplexed with the television signal and transmitted.In order to obtain accurate reception conditions, the input electric field strength must be set appropriately. In addition, it is necessary to correctly adjust the waveform equalization circuit 3 and the waveform shaping circuit 4 to a predetermined state.

For this reason, this device is equipped with a reception error rate detection device 18, which uses the received binary information signal and the sampling clock from the sampling clock generation circuit 15 to determine the error rate of the binary information signal. It detects whether it is receiving data and displays it. The principle of detection is that
When a PN code signal starts to be received, a predetermined number of bits of the received signal are extracted and added to the receiver's built-in comparison signal generation circuit as an initial state setting signal.Then, this comparison signal generation circuit independently generates a signal for comparison. Create a PN code signal. If you use a comparison signal generation circuit that generates the same PN code signal as the transmission side PN code signal generation circuit,
By setting the initial state using the received signal as described above, it is then sent from the transmitting side.
This means that the receiving side can independently create a PN code signal that is the same as the PN code signal, that is, a signal that does not contain any errors. Therefore, if you compare the received signal containing an error actually received by the receiver bit by bit with the predetermined comparison signal created as described above, it will be possible to compare both signals in the bit where the signal was received correctly. match, but the two signals do not match in the case of bits received in error, so the reception error rate can be detected by comparing both signals by a predetermined number of bits and detecting how many mismatched bits there are. It is something that can be done.

In addition, if the initial state of the comparison signal generation circuit provided in the receiver is set in the first part of the received signal in this way, the adjustment state of the receiver may be extremely poor when receiving in a weak electric field. The reception error rate is 0.01 at
If the value is as high as ~0.1, there is a high possibility that a reception error has already occurred in the received signal used for setting the initial state. If this occurs, the comparison signal created afterwards will inevitably be different from the PN code signal sent out by the transmitting side, and using such an erroneous comparison signal to compare with the received signal is itself a problem. It becomes meaningless.

Therefore, if you make a mistake in setting the initial state, the match rate when making a comparison will be extremely poor, generally reaching a match rate of 0.5 or less. When the matching rate falls below a predetermined rate, it is determined that the initial state setting is incorrect, an error rate detection circuit is reset, and the initial state setting is reset to perform angle detection. In this way, it is possible to perform efficient and accurate detection without unnecessary detection.

Details of such reception error rate detection device 18 will be explained below with reference to FIGS. 2 and 3. First, in FIG. 2, 19 is a clock generation circuit that creates a clock pulse synchronized with the received binary information signal, 20 is a delay sampling circuit that slightly delays and samples the received binary information signal, and 21 is the 20th H clock. a clock gate circuit that gates and outputs a 256-bit clock pulse during a period when a binary information signal is superimposed on the clock;
22 is a gate pulse generation circuit that generates different gate pulses for the first 16-bit period and the following 240-bit period of the 20th H binary information signal, and 23 is a gate pulse generation circuit that generates different gate pulses for the first 16-bit period of the 20th H binary information signal. A comparison signal generation circuit 24 compares the generated comparison signal and the received signal bit by bit, and when the two signals do not match, there is a mismatch. A comparison circuit that generates a detection output; 25 a counting circuit that counts the mismatch detection output to detect the number of mismatch bits; 26 a display circuit such as a numerical display element that displays the mismatch count output as a reception error rate;
7 is a detection time determining circuit that determines the time for comparing the received signal and the comparison signal and the time for counting the discrepancy detection output to a predetermined time width (here, the time width for comparing only 10 ^{to 16} bits), and 28 is the detection time determination circuit created above. A comparison circuit 29 compares the comparison signal and the received signal bit by bit and generates a coincidence detection output when both signals match, and 29 counts the coincidence detection output and determines that the coincidence rate in any given time is a predetermined rate. (here 0.5)
A counting circuit 30 generates a reset pulse to redo initial state setting and subsequent comparison/counting operations when the following conditions occur; 30 is a starting control circuit that starts the operations of each of the circuits described above;

FIG. 3 shows a specific example of the circuit. Note that parts corresponding to each circuit in FIG. 2 are given the same reference numerals.

The operation of this circuit will be explained below.

First, in the clock generation circuit 19, the received 2
A fourth clock synchronized with each bit of the binary information signal by using the clock run-in signal of the value information signal, etc.
Generate a clock pulse as shown in Figure D. In the delay sampling circuit 20, inverters 31 and 32
is used to slightly delay the received signal C, and
The received signal C is sampled by the flip-flop 37 using a clock pulse D delayed by about 1/2 of one bit by the inverters 33 to 35 and the time constant circuit 36, and the clock pulse D is delayed by about 1/2 from the Q output. Outputs a signal that is delayed from the received signal by the amount of bits. This is a pre-processing to ensure that each bit of the clock pulse is located in the center of each bit of the received signal in the subsequent circuit to ensure detection operation.

Next, at to, switch 3 in the starting circuit 30
8 is operated and activated. Then, a low level output is generated from the negative logic OR gate 39, and the flip-flop 40 is reset, and the flip-flop 42 is also reset via the negative logic OR gate 41. At this time, when resetting the flip-flop, a narrow reset pulse is generated from the NAND gate 43 using its Q output and output, and the flip-flop 46 is reset via the inverter 44 and the NOR gate 45. This completes the reset state at the start of operation.

On the other hand, in clock gate 21, first 2
A gate pulse that becomes low level only during the 1H period of the 20th H when the value information signal is superimposed is supplied from the gate pulse generation circuit 12, and is applied to the flip-flop 48 via the NOR gate 47, so that the flip-flop 48 It will be reset at the beginning of the 20th hour. On the other hand, the received signal from the monostable multi-49 triggered by the leading edge of the horizontal sync signal
A low level output is generated that terminates shortly before the first portion of the PN code signal, and this and the received PN code signal are applied to NAND gate 50 such that the first rising edge of the received PN code signal causes flip-flop 48 to It is set between bits.
Therefore, the Q output becomes high level from the first rising edge of the 20th H received signal, and the synchronous counter 51 is enabled to count from that time.

In this way, using the NAND gate 50, the received PN
By starting the operation from the first rising edge of the code signal, the starting point can be accurately controlled without being affected by fluctuations in the metastable time of the monostable multi 49. Note that when creating a PN code signal using a 16-bit shift register, as described later, the signal always rises at least once during any 16-bit period, so the 21st H For example, about 296 bits
Assuming that a PN code signal is transmitted, it is possible to perform start control at a sufficiently early stage, that is, within 16 bits from the beginning, and to have a sufficient number of bits for subsequent operations such as comparison. can.

Therefore, the counter 51 starts counting clock pulses, and when it finishes counting up to the 256th bit, it generates an output and resets the flip-flop 48 again via the NOR gate 47. Therefore, the flip-flop 48 receives 256 of the received PN code signals.
It will be left in the set state only during the period of the bit. Therefore, by using the Q output of the flip-flop 48 to gate the clock pulse with the NAND gate 52, a 256-bit clock pulse is obtained. This clock pulse becomes the reference for the locking operation.

Next, in the gate pulse generation circuit 22, the asynchronous counter 53 is put into a counting state by the output of the flip-flop 30 in the set state, and generates an output when it finishes counting clock pulses up to 16 bits. Set flip-flop 46. Therefore, this flip-flop 46 is activated when the start switch 38 is operated or when the
From the first rising bit of the PN code signal, it is in the reset state only for the following 16-bit period, and the 16th and earlier bits of the received PN code signal are
Generates a gate pulse that is inverted after the 17th bit. Note that when this gate pulse is generated, a pulse with a narrow pulse width is created by the time constant circuit 54 and the NAND gate 55, and the flip-flop 40 is set to reset the startup circuit 30.

Now, using the clock pulse and gate pulse obtained in this way, the comparison circuit 23 generates a comparison signal.
A 16-bit shift register 56 is driven by this clock pulse. This shift register 5
6 and exclusive OR gates 57 to 59 constitute the same PN code signal generation circuit as that used on the transmitting side. ~5
9, and is fed back to the input terminal of the shift register 56 and circulated to generate a so-called mode 2 (modal 2) PN code signal. The generated PN code signal is determined by the initial state set in the shift register 56 first. Therefore, at the beginning of the received PN gate signal,
During the 16-bit period, the NAND gate 60 is made conductive by the Q output and the output of the flip-flop 46, the NAND gate 61 is cut off, and the received PN code signal is transferred to the shift register via the NAND gate 60 and the negative logic NOR gate 62. 56 to set its initial state to match the received PN code signal. After that,
Shut off NAND gate 60 and NAND gate 61
is made conductive, and the feedback signals from the exclusive OR gates 57 to 59 are added to the shift register 56 and circulated to independently generate the subsequent PN code signal. Since this created signal is error-free and is the same as the PN code signal originally sent from the transmitting side, it is used as a reference signal for comparison.

Therefore, in the comparison circuit 24, the comparison PN code signal generated by the comparison signal generation circuit 23 as described above and the received PN code signal sampled by the delay sampling circuit 20 are connected to the exclusive OR gate 63 and the NAND gate 64. The NAND gate 64 generates a detection output when the two signals do not match, that is, when a reception error occurs. However, this NAND gate 64 is supplied with X to X+239 bits from the gate pulse generation circuit 22 in order to perform comparison only after the 17th bit counting from the first rising bit (x bit) of the PN code signal. A gate pulse is applied only during the second period, and a clock pulse is applied to enable a bit by bit comparison and a detection output to be generated bit by bit.

Therefore, each time a reception error occurs in the received PN code signal, the comparison circuit 24 generates a detection output for each bit. This is counted by the counter 65 of the counting circuit 25, and the counted value is calculated. By displaying this on the numerical display element 66 of the display circuit 26, the number of reception errors can be displayed numerically. In this case, if the total number of bits to be compared is kept constant as described below, it is possible to display the number of received error bits, that is, the reception error rate, relative to the total number of bits.

In order to determine the total number of bits to be compared, the detection time determination circuit 27 first uses the AND gate 67 to determine the number of bits X to X+239 of the PN code signal.
The clock pulse for the period up to the th bit, that is, the period for comparison, is extracted. The number of bits of this extracted clock pulse represents the number of bits of the PN code signal to be compared. Therefore, these clock pulses are counted by a counter 68, and when a predetermined number of bits, for example ¹⁰⁶ bits, have been counted,
Output is generated from NAND gate 69, negative logic OR
Flip-flop 42 is reset via gate 41. Then, the counter 68 is cleared by the Q output that becomes low level, and the NAND gate 64 in the comparator circuit 24 is shut off, thereby completing a series of comparison detection operations.

Therefore, when the comparison and detection of the predetermined number of bits is completed, the display on the display circuit 26 indicates the number of received error bits, that is, the reception error rate for the predetermined number of bits. For example, if the number of comparison detection bits is ¹⁰⁶ bits, the reception error rate is [number of displays x
10 ^-6 ].

As described above, by comparing the received PN code signal bit by bit with the standard PN code signal for comparison created independently on the receiving side, and counting the number of bits with reception errors, 2. It is possible to easily and accurately detect the reception error rate that represents the reception state of the value information signal.

However, the above operation can only be performed accurately if the comparison signal creation circuit on the receiving side can correctly create a PN code signal that is the same as the sending PN code signal on the transmitting side. If a reception error has already occurred in the 16-bit received PN code signal used to set the initial state of the signal creation circuit, the comparison signal created afterwards will be completely incorrect. Therefore, the comparison detection operation becomes meaningless. In such a case, experiments have shown that the reception error rate of the detected result exceeds 0.5. Therefore, in such a case, it is necessary to have the above-mentioned initial state setting and comparison detection operations performed again from the beginning.

Therefore, in this device, first, the comparator circuit 28
In NAND gate 70, exclusive OR gate 6
3 (the output when the received PN code signal and the comparison PN code signal do not match) is inverted by the inverter 71, that is, the output when both signals match is counted by the counter 72. Then, when the counter 72 counts a predetermined number of bits or more, the output is sent to the flip-flop 73.
Add to. On the other hand, a count output that changes every time a certain number of bits (N bits) of clock pulses are counted is taken out from the counter 68, and a narrow reset pulse is created by an inverter 74, a time constant circuit 75, and a NAND gate 76. counter 7
2 is cleared every fixed number of bits (N bits), and the flip-flop 73 is triggered every fixed number of bits (N bits). In this way, it is possible for the counter 72 to detect how many of the bits are in agreement during a period for every fixed bit (N bits) during which the output from the counter 68 is taken out. Therefore, when both signals match for a majority of bits (more than N/2 bits) in the N-bit period, the flip-flop 73 is not inverted, and both signals match for less than half the bits (less than N/2). The count value of the counter 72 is set so that the flip-flop 73 is inverted when they do not match, and the output of the inverted flip-flop 73 is sent to the start-up circuit 30 when there is a match in less than half the bits. negative logic
By adding it to the OR gate 39, all the operations described above can be redone in such a case. That is, the count value n of the counter 72 may be set to N/2. Note that the interval N bits for taking out the output from the counter 68 may be set arbitrarily, but if the 20th H PN code signal is
In order to be able to detect it at least once every time it is received, it is desirable that the number of bits be less than half of the total number of bits to be compared in the 20th H. For example, in the example above,
If you want to compare 240 bits every 20th hour,
The count output is taken every 64 bits from the ^25th digit of the counter 68 and sent to the counter 72 and the flip-flop 7.
3 may be cleared and triggered, and the counter 72 may be configured to generate an output when it counts the number of matching bits that is 32 bits or more.

In addition, if you want to make a retry when the number of matched bits is less than three-fourths for further safety, it is sufficient to generate an output only when the counter 72 counts 48 bits or more. . Of course, instead of counting the number of matching bits in this way, the number of mismatching bits may be counted to make the determination. Further, the criteria for determining whether or not to retry may be determined arbitrarily.

As described above, according to the present invention, the reception error rate when receiving a binary information signal can be easily and extremely accurately detected and displayed. Therefore, the state of the transmission path and the adjustment state of the waveform equalization circuit and waveform shaping circuit in the receiving device can be determined at a glance, and each part can be maintained and adjusted to minimize the reception error rate. This can be done easily and greatly contributes to obtaining the best reception conditions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a reception state detection device according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of its main parts, FIG. 3 is a specific circuit diagram of its main parts, and FIG. The figure is a waveform diagram for explaining the operation. 1...Antenna, 2...Video detection circuit, 3...
Waveform equalization circuit, 4...Waveform shaping circuit, 5...Gate circuit, 6...Sampling circuit, 7...Memory, 8...Signal processing circuit, 9...Amplification circuit, 10
...Cathode ray tube, 11...Synchronization separation circuit, 12...
Gate pulse generation circuit, 13... Color subcarrier generation circuit, 14... Basic clock generation circuit, 15...
Sampling clock generation circuit, 16... Main clock generation circuit, 17... Teletext receiver, 18
... Reception error rate detection device, 19 ... Clock generation circuit, 20 ... Delay sampling circuit, 21 ...
Clock gate, 22... Gate pulse generation circuit, 23... Comparison signal generation circuit, 24... Comparison circuit, 25... Counting circuit, 26... Display circuit, 27
...Detection time determination circuit, 28...Comparison circuit, 29
... Counting circuit, 30 ... Starting circuit.

Claims (1)

[Claims] 1 means for receiving a binary information signal transmitted while being intermittently superimposed on a television signal, and an initial state is set by the signal of the first part of each superimposition period of the received binary information signal; a comparison signal generating means for forming a comparison signal identical to the transmitted signal; a counter for comparing the actually received reception signal and the formed comparison signal and counting the number of reception errors in which the two signals do not match; and a counter for counting the number of reception errors in which the two signals do not match; a reset means for clearing a counter that counts the error rate and redoing the measurement when the number of pulses exceeds a certain value with respect to the number of received pulses; and a binary information signal in each superimposition period to set the initial state of the comparison signal generation means. 1. A reception state detection device comprising means for setting by a signal of a predetermined number of bits from the first rising edge of the signal.