JPH0131354B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that receives and displays dual information signals, such as a teletext system, and the present invention relates to a device that receives and displays dual information signals, such as a teletext system, in which the reception condition deteriorates to the extent that error correction cannot be performed sufficiently. When the screen becomes extremely difficult to see, it is possible to display in an easy-to-understand manner to the recipient that the reception condition is poor, and to detect the deterioration of the reception condition without the need to change to a special transmission method. It is an object of the present invention to provide a device that is equipped with means that allow direct, accurate and short-term detection using directly influencing control code signals and coded data signals.

First, an example of a receiving device with a reception status display function devised prior to the present invention will be described with reference to the drawings. Here, as an example, a receiver for the Teletext (CEEFAX) system in the UK will be described, but it goes without saying that the present invention can be applied to receivers for other information transmission methods.

Now, Figure 1 shows the transmission signal of the CEEFAX system, and T ₀ in the 10th and 18th horizontal periods during the VBL period (vertical retrace period) of the television signal.
A coded binary signal is sent in a superimposed manner, with the ₂₄ -bit part consisting of the part .about.T24 always starting at the beginning. After _T24 in FIG. 1, control code signals such as the type of signal being transmitted and the display position are sent in units of 8 bits (1 byte) of 4 message bits and 4 correction bits. However, even if such a correction bit is provided, if the signal is received in a place where the electric field strength is weak, that is, where the S/N ratio is poor, even if error correction is performed, the error cannot be completely corrected, and errors will inevitably occur. For example, when only a parity check is performed, a 2-bit error in one byte cannot be removed, and when a Hamming code is used and 4 bits out of 7 bits are used as message bits, a 3-bit error cannot be removed. Even if the error correction method is different, if the S/N ratio deteriorates, an erroneous signal may be mistakenly recognized as a correct signal. In such a case, information based on the received signal will be displayed incorrectly. For example, as shown in Figure 2, part a may not be displayed with flashing even though it should be displayed correctly (or vice versa), or part b may be displayed as "Z" instead of "Y". , c is actually a space but is displayed graphically, and d
That part should be displayed, but it's missing. Also, the positions of "119" and "105" are reversed.

If such an error occurs, the display screen will be extremely difficult to read. If the number of errors increases further, it may be better not to display them. When information is transmitted in a pattern, there are no errors in the characters themselves, but there are errors in the color of the characters or the background color, flashing, blanking, display position disturbances, etc., making the screen similarly difficult to view. Therefore,
Regardless of the signal format, if there are many errors, it is better not to display them.

Therefore, in this device, the occurrence rate of such reception errors is detected and displayed, and if there are particularly many errors, no information is displayed, but a message indicating poor reception is displayed.

Figure 3 shows an example of a configuration in which a reception error display function is introduced into a CEEFAX receiver. Here, 1 to 14 are similar to the so-called CEEFAX receiver,
To explain briefly, 1 is the television receiver.
VIF and video detection circuit, 2 is synchronous separation circuit, 3
4 is a video output amplification circuit, and 4 is a cathode ray tube. They are similar to regular televisions. Reference numeral 5 denotes a gate circuit that switches between a binary information signal representing characters or figures and a video signal output from the video detection circuit 1.

Using the horizontal and vertical synchronizing signals output from the synchronization separation circuit 2, the 17th and 18th H of the television signal is
A gate pulse generation circuit 7 generates a gate pulse to extract the part of the CEEFAX signal superimposed on the eye.
to form. 6 is a slicing circuit that slices the video detection output at an appropriate level and forms the waveform into a binary signal as shown in FIG. As shown in Figure 1 for the 17th and 18th H.
Extract the CEEFAX signal. On the other hand, 9 is a data sampling clock regeneration circuit, which is shown in Figure 1.
A ringing signal is formed using a filter such as a crystal oscillator using the clock run-in signal from T ₀ to _{T 16} to reproduce a continuous sampling clock for each 1H. This sampling clock is synchronized with the control code signal in Fig. 1 and each bit of the coded information signal that follows.
The output of the sampling circuit 8 is sampled by the sampling circuit 10 using the output. 11 is the first
Detecting reception of the framing code signal shown in the figure
The FC detection circuit detects main memory 1 by its detection output.
Memory control circuit 12 that controls writing and reading to and from 3
Perform initial settings. Hereafter, this memory control circuit 1
2 extracts the control code signal and the like, determines the writing position of the coded information signal in the main memory 13, and controls the writing. The stored contents of the main memory 13 are read out in accordance with the vertical and horizontal (scanning) of the cathode ray tube 4.
The ROM 14 converts it into a character pattern signal or a graphic pattern signal. The output of the gate circuit 5 is
It is controlled by the memory control circuit 12 so that the output of the ROM 14 is passed through as is. 16 is a control key.

Now, in such a receiver, a specific example of detecting an increase in reception errors as described above will be described with reference to FIGS. 3 and 4. In FIG. 3, reference numeral 15 denotes a reception error detection circuit mainly consisting of two sets of counters, which counts, for example, 50 fields of vertical pulses output from the synchronization separation circuit 2. in between
The superimposed sections of the CEEFAX signal are two sections per field, for a total of 100 sections. During that time, the number of times the output of the FC detection circuit 11 appears is counted by another counter, and for example, when the FC detection output becomes 90 times or less, or in other words, when the reception error becomes 10% or more, the gate The output of the circuit 5 is switched from the output of the ROM 4 to the output of the video detection circuit 1, and at the same time the warning lamp is controlled to be turned on.

This will be explained in detail with reference to FIG. The resistor 17 and capacitor 18 in FIG. 4 are a circuit that integrates the composite synchronizing signal output from the video separation circuit 2 and extracts the vertical synchronizing signal, and its large time constant eliminates high-frequency noise. In the output of No. 19, a vertical synchronization pulse at the correct position appears at an electric field strength within a range in which the vertical synchronization of the television receiver is stable. The counter 20 counts 50 outputs. The output of FF21 is applied to the reset terminal, and when the power is turned on or the control key 16 is operated, the monostable multivibrator MM22 is triggered and outputs a pulse of approximately 1 μs, for example.
At the trailing edge of the pulse, FF21 is set and the count operation begins after its Q goes low. Note that the output of the counter 20 remains at a high level until 50 vertical synchronization pulses are counted. It is also assumed that the input side of the MM22 is a two-input OR circuit. As a result, the counter 23 can also count at the same time, and counts the output of the FC detection circuit 11, that is, the number of times the framing code is detected.

Count 50 vertical synchronization pulses with counter 20.
When the 51st field pulse is counted, its output becomes low level and resets FF21, and MM
Trigger 22. As a result, the output of the FF 21 becomes high level, and the counters 20 and 23 are reset. Considering the second output of the counter 20 excluding the first output, the first output is
Approximately 1μsec after FF21 is reset, MM
At the trailing edge of the output of FF 22, the FF 21 is set again and the counters 20 and 23 become capable of counting.
Count the FC detection output of each eye by two. Therefore, the FF24 is reset at the 90th bit of the output of the counter 23, and the FF24 is reset until the output of the MM22 is finished.
The output of FF24 becomes high level, and the output of NAND gate 25 is approximately the inversion of the output of MM22.
It becomes a 1 μsec pulse, sets the FF27, makes its Q output high level, and makes its output low level. Therefore, the lamp light emitting diode 28 is not turned on at this time.

On the other hand, during the output of the memory control circuit 12, if only characters and figures are displayed and the output a is at a high level, the AND gate 29 is cut off by the output and the b output of the memory control circuit 12 is is at a high level, and the rest are at a low level.
AND gate 30 is also blocked. On the other hand, the output of the AND gate 34 becomes high level, and the wired OR
An OR gate 32 such as a gate becomes conductive, and an AND gate 31 is cut off by the output of an AND gate 33. Therefore, only the output of the ROM 14 is transmitted to the output circuit 3, and character or graphic information is displayed as shown in FIG.

If the S/N is poor and there are many errors, the framing code will also be detected incorrectly. The position of this FC signal is from T ₁₆ to _{T 24} as shown in Figure 1, and at the 17th H and 18th H.
In both eyes, the positions of T ₁₆ to _{T 24} with respect to the horizontal synchronizing signal are almost fixed, so as shown in Fig. , excluding the influence of input noise, two monostable multivibrators 35 generate gate pulses including T ₁₆ to T ₂₄ (particularly including only before and after T ₂₄ ), and the output of the FC detection circuit 11 during that period is FC Counter 23 as detection output
If it is less than 90, the FF24 is not reset, so the output of the FF24 is at a low level, Q remains at a high level, and when the output of the MM22 is at a high level, the output of the NAND gate 26 becomes a low level.
Reset FF27. Therefore, the light emitting diode 28 lights up, indicating that the S/N ratio of the received signal is poor, and since the Q of the FF 27 is at a low level, the output of the AND gate 34 is at a low level. Therefore, AND gate 32 is cut off and gates 31 and 29 are made conductive. Therefore, the output of the video detection circuit 1 is transmitted to the output circuit 3. Since the output of the AND gate 37 is also at a low level, the AND gate 30 is shut off, and superimposed display of text information on the television screen is also prohibited.

Note that gates 29 and 30, 31 and 32 are MOS
It is an analog gate formed by transistors, and its output is an IC that can be wired OR-combined.

Next, when the pulse of the 50th field appears in the output of the counter 20 for the third time, the counter 23
If you count 90 or more outputs of the FC detection circuit 11,
As explained at the beginning, characters and figures are displayed on the TV screen. The output of the counter 20 appears every 50 fields, that is, once every second, so if there is a sudden noise, it will immediately return to its original state and the memory contents will remain unchanged, so there will be no negative effect. , the lamp 28 is activated when the FC signal is continuously detected incorrectly.
lights up and the display of characters and figures disappears, making it possible to issue a warning. It is also easy to find the optimum point for local readjustment.

Now, in the circuit shown in FIG. 4, the detection error of the framing code signal is checked, but since the framing code signal is just a control signal for phase synchronization, it is the signal that should originally be transmitted. It is not possible to detect whether the reception state of the data signal itself is good or bad. Furthermore, since the framing code signal is transmitted only once for a group of data signals, it is not possible to detect the quality in a short period of time.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a device that can directly detect the quality of the reception state of the original signal itself to be transmitted, and can also detect quality in short time units. .

Therefore, in the present invention, the number of error corrections of the control code signal in the information signal and the number of parity checks of the coded data signal are detected, and these numbers are detected within a predetermined period of time to determine whether the reception condition is good or bad. I try to do that.

In the CEEFAX system, except for the page header, a coded character signal for 40 8-bit characters and a 2-byte (16-bit) control code signal are sent after the FC signal. Therefore, the parity check is performed 40 times per line, and the error correction is 4 bits (2 = 8).
This is done on bits.

Therefore, in the present invention, by checking the number of error corrections and the number of parity detections of the control coded data signal that directly indicates the content to be transmitted and displayed, the reception error rate is determined to be above a predetermined value. It is detected whether or not there is a predetermined number, and if the number is greater than a predetermined value, a message to that effect is displayed.

FIG. 5 shows the main parts of an embodiment of the present invention that performs such detection. Figure 5 shows the fourth
This figure shows a circuit in which the error rate detection part in the figure is modified according to the present invention. The remaining parts have the same configuration as in FIG.

In the circuit shown in Figure 5, if there is an error of 3 or more bits in 2 bytes of the control code signal,
The output of the correction bit counter 122 that counts the output of the correction bit detection circuit 121 is set to high level,
Reset FF27 via the NOR gate.
Also, if the output of the parity counter 123 is 16 or more (error rate of 40% or more), the same operation as shown in Figure 4 can be expected by setting the output to a high level, and even if the FC signal is correct, there will be many errors. It is effective in such cases. Note that both counters 122 and 123 are
It was cleared at the beginning of the 18th H, and FF27 was also cleared at the beginning of the 18th H.
Set at the beginning of the 17th and 18th hours. Therefore, it is also possible to erase the display line by line on the screen. Clear counters 122 and 123 at the page header instead of the beginning of the 17th and 18th H.
By setting FF27, processing can be performed on a page-by-page basis. The error rate to be tolerated can be determined by freely selecting the number of bits output from the error counters 23, 122, and 123.

Note that although the above embodiment is for the CEEFAX system, it can also be applied to other systems. Further, the warning display may be displayed in text such as ``input failure'' on the television screen, or may be expressed by voice synthesis saying ``I'm in trouble!''.

Furthermore, with the configuration of the present invention, the control code signal and coded data signal originally included in the information signal are effectively used to count the number of error corrections and parity checks, thereby determining the reception state. Since it is possible to detect pass/fail, there is no need to change to a special transmission method to detect the reception error rate, and there is no need to add a special signal to detect the reception error rate. It is possible to maintain high efficiency and maintain a large amount of data transmission.

In addition, since the control code signal and coded data signal, which are the signals that should be transmitted, are used, it is possible to directly and reliably detect the reception quality of the signals that should be transmitted. Since the amount of transmission is large, in short time units, for example,
It is also possible to determine the quality of reception on a line-by-line or page-by-page basis.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram of an example of a received information signal, FIG. 2 is a front view showing an example of how the information is displayed, FIG. 3 is a block diagram of a signal processing device devised prior to the present invention, and FIG. The figure is a detailed circuit diagram of a portion thereof, and FIG. 5 is a detailed circuit diagram of a portion of a signal processing device according to an embodiment of the present invention. 5... Gate circuit, 10... Sampling circuit, 11... FC detection circuit, 12... Memory control circuit, 13... Main memory, 14... ROM, 15
...Reception error detection circuit, 20, 23...Counter, 28...Lamp.

Claims (1)

[Claims] 1. A receiving circuit that receives an information signal in which a phase synchronization control signal, a control code signal, and a coded data signal are transmitted in a time-series manner as a binary signal, and the received information signal. a detection circuit for detecting the number of times the control code signal in the coded data signal is error-corrected within a predetermined time and the number of times the coded data signal is parity-checked within a predetermined time; 1. A signal processing device comprising: a display circuit that displays a poor reception state when the number of signals exceeds a predetermined number. 2. Claim 1, characterized in that the display circuit switches between displaying information based on the received information signal and displaying a state of poor signal reception. signal processing device.