JPS6331331A - Decoding circuit - Google Patents

Abstract

PURPOSE:To obtain a decoding circuit capable of taking block synchronization without any adjustment, by using a J-K flip-flop in a frequency division circuit, and inputting a step out detecting signal to the J and the K terminals of the J-K flip-flop. CONSTITUTION:The negative phase output f0CLKi of the J-K flip-flop 16 is phase-compared with a block detecting signal (d) at a phase discrepancy detec tion circuit 10, and a phase discrepancy detecting signal (j) set at 'H' when the phases are discrepant, can be obtained. The content of a phase discrepancy counter 13 is increased by one, at every setting of the phase discrepancy detecting signal at 'H' and a step out signal (n) is set at 'H' when the content detected at a phase discrepancy number detection circuit 14 arrives at a constant number. The timing of the step out signal (n) is rearranged by a 2f0 CLK at a step out detection circuit 15, and a step out detecting signal 0 can be obtained. When the step out detecting signal 0 is set at 'H', the J terminal and the K terminal of the J-K flip-flop 16 are set at 'H's, and the toggle operation of the J-K flip-flop 16 is stopped, and the phase of the f0CLK is shifted by (pi).

Description

[Detailed description of the invention] [Industrial field of application] This invention converts 1B2BB binary data into NRZ (non
-return -to -zero) code.

[Conventional technology]

Figure 4 shows Japan, for example! "Integrated circuit for secondary group transmission power type repeater" in "Research and practical application report" published by Telephone and Telephone Corporation's Heart and Heart Communication Research Institute, No. 32%, No. 11 (1983) P.
, 2405 is a diagram illustrating a conventional CMI decoding circuit described in . In the figure, 1 is a decoding unit, 2 is a D-flip-flop (D-F/F), 3 is a shift register, 4 is a "10" detection circuit, 5 is an "11" detection circuit, and 6 is a "00" detection circuit.
"detection circuit, 7 is rxx, oo" detection circuit, 8 is a D-flip-flop (D-F/F), 9 is a block synchronization section,
10 is a phase mismatch detection circuit; 11 is a phase match detection circuit;
12 is a phase mismatch number counter reset circuit, 13 is a phase mismatch number counter, 14 is a phase mismatch number detection circuit, 15
18 is an out-of-sync detection circuit, 18 is a clock gap generation circuit, and 19 is a T-flip-flop (T-F/F).

FIG. 5 is a signal waveform diagram of each part in the CMI decoding circuit of FIG. 4.

Next, a recommended circuit for the conventional CMiff1 coding circuit shown in FIG. 4 will be explained. First, in a4 part 1, D-F/F
2, the decoding circuit input data is retimed, and a positive phase output a and an inverse 4fi output are obtained.

Next, by shifting the positive 2 . . . output a by 1 bit using the shift register 3, output No. 1 C is obtained. In the case of CMI code,
Since the falling point of the data corresponds to a block break, the rlOJ detection circuit 4 obtains a block detection signal (=falling detection signal) d. In addition, the "11" detection signal e from the "11" detection circuit 5 and the roOJ detection signal f from the roOJ detection circuit 6 are added, rl 1 and the OOJ detection circuit 71'c are ORed. ,rll
, OOJ detection signal g is obtained. rll, oOJ detection signal g is sampled at D-F/F8 with block-synchronized CLK of frequency f0 (hereinafter abbreviated as 90LK). From this, the output of D-F/F8 is N RZ This is the decrypted data.

On the other hand, the block synchronizer 9 operates as shown below using the block detection signal d. Here, FIG. 5 shows the process of pulling in block synchronization. C of frequency zfo
LK (hereinafter abbreviated as 2f, CLK) is T-F
/F19 divides the frequency by two.

The reverse phase output CLKi is phase-compared with the block detection signal d in a phase mismatch detection circuit 10, and a phase mismatch detection signal j which becomes "H" when the phases do not match is obtained. The phases of the positive phase output focLKh are compared in a phase coincidence detection circuit 11, and a phase coincidence detection signal k which becomes "H" when the phases match is obtained. Every time the phase mismatch detection signal j becomes "H", the content of the phase mismatch counter 13 is incremented by 1, and when the phase mismatch detection signal k becomes mHII, the content of the phase mismatch counter 13 is reset to O. be done. phase mismatch★ The contents of the phase mismatch counter 13 are detected by the phase mismatch number detection circuit 14,
When the contents of the phase mismatch counter 13 reach a certain number (
3) in FIG. 4), the out-of-synchronization signal n becomes H''. The out-of-synchronization signal n is retimed by 2foCLK in the out-of-synchronization detection circuit 15, and an out-of-synchronization detection signal 0 is obtained.

When the out-of-synchronization detection signal O becomes "H'", focLK
The phase of is shifted by π. Out-of-synchronization detection signal O and 2f
The phase of OCLK is adjusted at the input part of the tooth gap CLK generation circuit 18 so that a bridge does not occur, and tooth gap CLKq is obtained. At the position where the tooth gap occurred, the frequency division of T-F/F19 by two stops and f6CLKh.

The phase of i is shifted by π.

Here, if the above phase adjustment is not performed, the out-of-synchronization detection signal O changes to "H" as a result of the n-th CLK of 2 foCLK, and this out-of-synchronization detection signal O changes to "H".
Since the out-of-sync CLK generation circuit 18 (in the n-th CLK of 2 fo CLK) is caused to have an error, a bridge indicated by J is generated due to the propagation Ei of the out-of-synchronization detection circuit 15. As a result, the block synchronizer 9 does not operate normally.

[Problems that the invention attempts to solve] The above conventional CM
Since the No. Ii f signal path is constructed as described above, the timing of 2f0CLK and the out-of-synchronization detection signal O must be adjusted precisely to prevent bridging from occurring in the missing CLK generation circuit 18 of the block synchronizer 9. There was a problem that needed to be adjusted.

The present invention was developed to solve these problems, and an object of the present invention is to provide a decoding circuit that can achieve block synchronization without adjustment.

[Means for solving problems]

In the decoding circuit according to the present invention, a flip-flop is used for J- in the frequency dividing circuit, and J- of the flip-flop is used for J-.
The out-of-synchronization detection signal is input to the - terminal.

[Effect]

In the decoding circuit of this invention, a flip-flop is used for J- in the frequency dividing circuit, and a groove is formed in this J- so that the out-of-synchronization ejection No. 1 is input to the terminal of the flip-flop. The operation of shifting the phase by π is J
This is done by not toggling the flip-flop at J- by operating the terminal at -.

〔Example〕

FIG. 1 is a diagram showing a decoding circuit according to an embodiment of the present invention, in which the same or corresponding parts as in FIG. In the figure, 1
Reference numeral 6 designates a flip-flop at J-, to which the out-of-synchronization detection signal O is input to the J and 2 terminals, and the 2faCLK signal is input to the T terminal.

FIG. 2 is a diagram showing the logic of the flip-flop at J- in the decoding circuit of FIG. 1, and FIG. 3 is a signal waveform diagram of each part in the decoding circuit of FIG. 1.

Next, the operation of the decoding circuit shown in FIG. 1, which is an embodiment of the present invention, will be explained. FIG. 1 In the decoding circuit shown in FIG. 1, the operation of the decoding section 1 is similar to the conventional example shown in FIG. 4 above.

The block synchronizer 9 operates as described below using the block detection signal d. FIG. 3 shows the process of pulling in block synchronization, in which 2 fa CLK is divided by two by the flip-flop 16 to J-. Normally, the J- terminal of the J- flip-flop 16 is at "L". J
−, the reverse phase output CLKi of the flip-flop 1G is phase-compared with the block detection signal d in the phase shifter matching output circuit 10, and the phase mismatch detection signal i becomes “H” when the phase mismatch occurs.
d number j is obtained. In addition, the phases of the positive phase outputs f and CLKh are similarly compared with the block detection signal d in the phase coincidence detection circuit 11, and a phase coincidence detection signal P which becomes 'H'' when the phases match is obtained.Phase mismatch detection; Each time the signal j goes to "H", the contents of the phase mismatch counter 13 are incremented by 1, and when the 1 phase match detection signal k becomes "1", the contents of the phase mismatch counter 13 are reset to O. The contents of the phase mismatch number counter 13 are detected by the phase mismatch 'I!L detection circuit 14.
Detected with? - When the contents of the U-phase mismatch counter 13 reach a certain number (31 in FIG. 1), the out-of-synchronization signal n becomes 'H'. The retiming is performed, and an out-of-synchronization detection signal O is obtained. When this out-of-synchronization detection signal 0 becomes "H", both the J terminal of the flip-flop 16 at J- and the terminal at J- become "H", and the flip-flop 16 toggle operation stops and fo CL
The phase of K shifts by π.

In the case of the circuit configuration of the decoding circuit as shown in Fig. 1, 2
"H" of the out-of-synchronization detection signal 0 is outputted by the n-th CL K of fo CL K, and then "H" of the out-of-synchronization detection signal O is output at the flip-flop 16 to J-.
+1st 2 fo CL K sampled, fn
Since the phase of CLK is shifted by π, J-
The flip-flop 16 outputs out-of-synchronization detection signals O and 21.
1. There is no need to adjust the phase of CLK.

〔Effect of the invention〕

As explained above, in this invention, in the decoding circuit,
A flip-flop is used for J- in the frequency dividing circuit, and an out-of-synchronization detection signal is input to the J- terminal of the flip-flop, so a decoding circuit that can achieve block synchronization without adjustment can be obtained. This has an excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a decoding circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a flip-flop circuit connected to J- connected to the decoding circuit l of FIG. 1, and FIG. Figure 1 is a signal waveform diagram of each part in the decoding circuit, and Figure 4 is the conventional C
FIG. 5 is a diagram showing signal waveforms of various parts in the CMI conversion circuit of FIG. 4, which is a diagram showing MI conversion. In the figure, l...decoding unit, 2...D-flip-flop (D-F/F), 3...shift register, 4
... "10" detection circuit, 5 ... "11" ejection circuit,
6... "OO" detection circuit, 7... rll, oOJ↑
Roasting circuit, 8...D-flip-flop (D-F/F
), 9... Block synchronization unit, 10... Phase mismatch production: ] path, 11... Phase match detection circuit, 12... Phase mismatch number counter reset circuit, 13... Phase mismatch number counter, 14...Phase mismatch number detection circuit, 15
・-・Same, +[l is a shift detection circuit, 16...J- is a flip-flop, 18... Tooth gap clock generation circuit, 19...T-7 lip-flop (T-F/F)
It is. In each figure, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa No. 2rJA Figure 3 Figure 5 PCM ○ 001 Procedural Amendment (Voluntary) To the Commissioner of the Japan Patent Office
;Please see Σ゛1, Incident display Patent Application No. 174960/1982,
Invention title decoding circuit 3, relationship with the case of the person making the amendment Patent applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Column 6 of "Drawings" subject to amendment, Contents of amendment (1) One amendment will be made to the attached drawings Figures 1 and 4 as shown in the attached sheet.

Claims (1)

[Claims] In a decoding circuit that encodes NRZ data to be transmitted into a 1B2B code such as a CMI code or a Manchester code and transmits and receives the code, the encoded data and the frequency 2f_0 and the CLK of the frequency f_0 output from the block synchronization unit are input, A decoding unit that outputs decoded data and a block detection signal, and inputs the CLK of frequency 2f_0 and the block detection signal, toggles the J-K flip-flop using CLK of frequency 2f_0 to obtain CLK of frequency f_0, and outputs CLK of frequency f_0. The phase of CLK of frequency f_0 and the block detection signal are compared, and if it is determined that the phase is shifted, the toggle of the JK flip-flop is stopped, the phase of CLK of frequency f_0 is shifted by π, and the phase of CLK of frequency f_0 is shifted by π, and the phase of the CLK of frequency f_0 is shifted by π. and the block synchronization section that outputs CLK of frequency f_0 synchronized with the decoding circuit.