JPS58131816A - Synchronizing pattern generating circuit - Google Patents

Abstract

PURPOSE:To generate a synchronizing pattern signal having a pattern of a limited range by using a fewer logical gates. CONSTITUTION:A counter 1 is a Johnson counter of three-stage and 6-notation, and a counter 2 is a one-stage binary counter. The counter 1 starts counting of an input pulse signal from a time A and gives a signal (a) transmitted from an output terminal Q1 of the 1st stage to the counter 2 and a signal (b) transmitted from an output terminal Q2 of the 2nd stage to one input terminal of an exclusive logical sum gate (EX-OR)7. The counter 2 counts the pulse of signal (a) and gives a signal (c) transmitted from an output terminal Q4 to the other input terminal of the EX-OR 7. In the signal (a)[or (b)], the same pattern appears in 6=bits from the time A to B and time B to C. In the signal (c), the inverted pattern appears in 6-bits from the time A to B and from the time B to C.

Description

[Detailed description of the invention] The present invention relates to a synchronization pattern generation circuit.

In a system that transmits digital signals by time division multiplexing, in order to achieve frame synchronization between the transmitting and receiving parts of the multiplex conversion system, a circuit that generates a synchronization pattern with a predetermined number of bits synchronized with the transmission lock signal is used. It is included in the transmitter.

FIG. 1 is a block diagram showing a conventional synchronization pattern generation circuit. The figure shows an example of generating a 12-bit synchronization pattern. The counter 1 is a three-stage di-math counter and performs hexadecimal counting. Also, counter 2 is 1
Binary counting is performed using a stage counter. Counter l counts input pulse signals with a predetermined period, and outputs signals sent from output terminals Q1 to Q3 of each stage to decoders 3 and 4.
are applied as respective selection inputs to the counter 2, and a signal sent from the output terminal Ql of the first stage is applied to the counter 2. The signal sent from the output terminal Q4 of the counter 2 is sent to the decoder 3 as a data input, and is also sent to the decoder 4 as a data input through all the negative gates 5.

During the 12-bit period from when counter l starts counting input pulse signals, the selection inputs of decoders 3 and 4 repeat the same pattern twice, and the data input of decoder 3 (or 4) The first 6 bits are at high level (H), and the latter 6 bits (or first half) are at low level (L). Decoders 3p and 4 each have six output terminals, and send a data input signal to one output terminal in accordance with a selection input. In other words, during the 6-bit period from when the counter 1 starts counting the input pulse signal, the six output terminals of the decoder 3 (or 4) first receive the input data at the topmost output terminal at the first bit. A signal is sent nl. Thereafter, each time the bit advances one by one, a data input signal is sent to the next lower output terminal, and at the sixth bit, a data input signal is sent to the lowest output terminal. Therefore, during the 12 bits after the counter 1 starts counting the input pulse signal, the first six bits are sequentially sent to one of the six output terminals of the decoder 3. Output terminals of the six output terminals of each of the decoders 3 and 4, which correspond to the high level bit of the synchronization pattern signal, are connected to the OR gate 6. Therefore, the OR gate 6 is (H, L, L, L, H, H
, L, H, H, f (, L, L) is repeatedly sent out. In order to generate a similar pattern signal different from this pattern, the connection between the output ends of the decoders 3 and 4 and the OR gate 6 may be changed depending on the pattern.

As explained above, the conventional synchronization pattern generation circuit generates a synchronization pattern signal having a predetermined pattern by passing the output signals of each stage of the counter to a logic circuit equipped with a decoder. In this case, the pattern of the synchronization pattern signal can be determined without particular limitation, but as the bit length of the pattern increases, the number of logic gates included in the decoder increases, and accordingly, the wiring for circuit connection increases. Since the number of circuits increases, there are disadvantages in that the size of the circuit becomes larger and the power consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization pattern generation circuit which eliminates the above-mentioned drawbacks and can generate a synchronization pattern signal having a pattern within a limited range using a smaller number of logic gates than conventional ones.

The circuit of the present invention includes a first counting circuit that counts pulse signals having a predetermined period and sends out a first signal group;
a second counting circuit that counts pulses of one signal of the signal group and sends out a second signal; and another signal of the first signal group and the second signal. and a logic circuit that generates a third signal that is the exclusive OR of

Next, the present invention will be described in detail with reference to the drawings.

FIGS. 2a) and 2b) are a block diagram and a waveform diagram showing an embodiment of the present invention, respectively, and show a case where a 12-bit synchronization pattern is generated similarly to FIG. The counter 1 starts counting the input pulse signal using a 3-stage hexadecimal input pulse signal, and sends the signal a sent from the output terminal Ql of the first stage to the counter 2, which is then sent from the output terminal Q2 of the second stage. The signal S is sent to one input terminal of an exclusive OR (EX-OR) gate 7. The counter 2 counts the pulses of the signal a and sends the signal C output from the output Q4 to the other input of the EX-0 gate 7. signal a (or b)
Then, the same pattern appears between 6 bits from time A to time B and between 6 bits from time B to time C.

- In the power signal C, a pattern appears that is inverted between the 6 bits from time A to time B and the 6 bits from time B to time C. Therefore, the signal and ct-
The synchronization pattern signal obtained through EX-0 gate 7 consists of the first 6 bits (from time A to time B) and the second half (from time B to time C) of the 12 bits from time to time C. It has a pattern that is inverted from the 6 bits in between). The circuit illustrated in FIG. 2(a) is
b) and ((H, L, L, L, H, H, L, H,
H, H, L.

A synchronization pattern signal having a 12-bit pattern of L) is repeatedly sent out.

FIG. 2(a) shows one embodiment of the present invention, and shows the type and number of stages of counter 1, and the output terminals of counter 1 connected to counter 2 and EX-C)R gate 7, respectively. It is not limited to this. That is, the number of stages of the counter l is determined based on the bit length of the synchronization pattern signal, and a list is created in which the generated patterns are listed for each connection of the β expression of the counter l and its output terminal to the counter 2 and the EX-OFL gate 7. The configuration of the circuit is determined by creating a synchronization pattern and selecting from the list a pattern that meets the requirements for the synchronization pattern.

This has the advantage that it is possible to realize a synchronization pattern generation circuit that can generate a synchronization pattern using a smaller number of logic gates.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional synchronization pattern generation circuit, and FIG. 2 1a) and +b) are a block diagram and a waveform diagram showing an embodiment of the present invention, respectively. 1.2...Counter, 3,4...Decoder, 5...Negation gate, 6...OR gate, 7... Exclusive OR (EX-OR)
Gate. Agent Patent Attorney Uchihara Oto 7 Rin 4

Claims (1)

[Claims] a first counting circuit that counts pulse signals having a predetermined period and sends out a first signal group; and a first counting circuit that counts pulses of an f signal of one of the first signal groups and outputs a second signal. A logic circuit that generates a third signal that is an exclusive OR of another signal of the first signal group and the second signal. A synchronous pattern generation circuit characterized by: