JPS6331247A - Communication control equipment - Google Patents

Abstract

PURPOSE:To improve a processing speed by realizing the management of a buffer of a CPU charging respective layers, the synthesis of the headers of all the layers and the transmission to a line by a DMA controller by a hardware means. CONSTITUTION:Independent buffer pools 15-18 are disposed for every CPU 11-14 charging the respective layers. The CPU 14 obtaining the buffer for storing the header to the respective layers and charging the highest order layer stores the header in the buffer obtained by the hardware means from the buffer pool 18 and inputs the address of the buffer to an FIFO memory 22 for the highest order layer. Thereafter, the request for forming the header is carried out to the CPU 13 charging an adjacent low order layer with an interruption. A similar processing is performed to the CPU 11 charging the lowest order layer and a packet obtained by synthesizing the headers of all the layers is transmitted to a line by the DMA controller 35.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a communication control device that executes a protocol and performs data communication.

Conventional technology Figure 1 shows a communication control program using a conventional multi-CP tJ.
2 shows the configuration of a communication control device that processes protocols in parallel.

In Figure 2, there is J3, 1 and -4 are CPUs, and
The power is manually supplied to an engine 55 that performs competition control.

6 is an r) MA control circuit, and 7 is a shared memory, which is accessed by the arbiter 5. 8 is D M A lb'l
This is a circuit 4111/F section driven by the 111 circuit 6.

Next, the above conventional operation will be explained. In FIG. 2, CPU 1 to CPU/I share layers A71 to Layer 4. When performing protocol processing, acquire the buffer pool J and rebuffer 7 that can be accessed by all CPUs (located in memory 7), and use Jf for this.
It stores the program header of the next layer and notifies the CPUs 1 to 3 of the adjacent lower layer together with parameters such as a buffer address. Therefore, C.P.
When LJ /I is reduced by [- minutes, C', P U '
If I first grabs the buffer then J's descends each CPU
Store the headers of the layers shared by 3 to 1 in buffer 7 (
), which are sequentially delivered to CPU1. Then CI'L
The DMA control circuit 6 is activated by I1, and the line 1/[
The data is sent out onto the line via section 8.

In this manner, even in the conventional communication FF and IJ ill devices described above, control is transferred between CP1 and CP1 using buffers, and protocol processing can be performed in a multi-CPU configuration.

Problems to be Solved by the Invention However, in the conventional communication control device, in order to enable all CPUs to obtain and return buffers in the shared memory 7, all CPUs 4 have to use software for controlling the buffers. In addition, it is necessary to provide a control flag for management in the shared memory 7, which complicates the management of the buffer.

Furthermore, since a buffer is used to transfer control between CPUs, there are problems such as a decrease in processing speed.

Mizumoto Akira Yokono J: This solves and overturns the conventional problem, and allows buffer management to be done without software.
The purpose of this invention is to provide a communication control device expressed in hardware.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a buffer pool for each layer in the CP (J fij), and from there, the header of each ray A7. The CP that acquires a buffer for storing the
tJ stores the header in a buffer acquired by hardware means from the buffer pool, and inputs the address of the buffer to the [■[0 memory for the top layer. After that, a request to create a header is sent to CP (J), which shares the adjacent lower layer A7, using 811. The same process is performed up to CP U, which shares the lowest layer, and the MA control device r) MA control device When transmitting a packet in which the headers of all layers are combined, the addresses of the buffers are sequentially taken out from the FIFO memory of the lowest layer A7, and the contents of the buffer are transmitted to the line. After sending Xlj, the empty buffer number is returned to the corresponding buffer pool. The CPU that has completed the protocol processing of its own layer is configured to have a function that allows it to immediately accept the next protocol processing after outputting the Barafun address to the IFo memory.

Takeda: With the above configuration, each CPU manages an independent buffer pool for each layer using hardware, without having to manage the buffer pools using software, and once the headers for all layers are created, they are processed by the DMA controller I7 device. Since it is possible to send packets on the line, the CPLJ that is responsible for the primary layer creates its own header, and after completing the header creation request to the adjacent lower layer, it can immediately concentrate on the next protocol processing. can. This bundling can reduce software A-barhead and enable high-speed processing of protocols.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. Figure 1;
I"U, 11-14 are CPLIr, CI' U 14
shall be in charge of the upper layer, and the upper layer CP LJ 1
4, a header is created and a request is sent to the CPUs 13 to 11 in the lower layer. 15 to 18 are C that share each layer
This is a buffer pool provided independently for each of PU11 to PU14. 19-22 are buff) 7 pools 15-18
Take out the address of each buffer in - IFIFO memory,
23 to 26 are latch circuits that latch this. 27
~3o is an FTFO memory without taking out the address of the buffer latched at 26 to the latch circuit 23, 31 to 34 are three-state gates, 35 is a DMA control circuit, 3
6 is a line 1/F section.

Note that in FIG. 1, path lines, control lines, etc. for 32-light are omitted.

FIFO memories 19 to 22 go to CPU 1i.14
The addresses of the buffers in the buffer pools 15 to 18, which are independently owned by the CPUs 11 to 14, are set up in correspondence with each other at every turn of the CPUs 11 to 14. For example, when a packet transmission request is sent to the layer of the CPU 14, the CPU 14 sends [I'0 memory 22
Outputs the 5IFT/IN clock pulse to the buffer address and takes out the address of the buffer (c) This is sent to the latch circuit 26 to latch 3.
-14ru. CI"'U for the address of this buffer
Create a header for layer 14 and add C of adjacent lower layer A7.
Notification is made to the PU 13 using an interrupt or the like. At this time FI
Input the 5IFT-IN clock to the FO memory 30 and set the address of the buffer latched by the latch circuit 26 as "
I[0 input to memory 30. Hereafter, c p U 13
Similar processing is performed from to 11. At this time, the FIFO files 27 to 30 store the address of the buffer storing the layer header of the CPU 14 to the address of the buffer storing the layer header of the CPU 11.

When the CPU 11 reads a transmission request to the DMA control circuit 35, the MA open control circuit 2835
The 5 IFT/OUT clock is outputted to the memory 27, and the three-state gate 31 is interrupted for an hour, and the DMA IIJ control circuit 35 outputs it to the line 1/F section 36 from the lowest layer header. From then on FIFO memory 2
Similar treatment is applied to 8-30.

DM A l1ill no circuit 35 l') M
After completion of A, process each buffer correspondingly CPU 11~1
In order to return to the buffer pools 15 to 18 of 4, 5 IFT-IN is sent to the corresponding F r F O mail 19 to 22.
Output clock and input address of free buffer 1J
Ru.

By repeating the above series of operations, the header is transferred from lower layer to lower layer to each CPU.
14 to 11, and the line "2" can be closed by bucket 1 and the headers can be combined and output can be overwritten.

In addition, CPUs 11 to 14 create a link to the protocol, and the buffer addresses are stored in FIFO memories 19 to 2.
After storing to 2, it accepts instructions from the next adjacent upper layer.
By queuing the buffer address to IFO memory 19 to 22, each CI'1J
11 to 14 can perform protocol processing without depending on the transmission degree of the line.

The present invention has the following advantages: Management of buffers owned by the CPU that covers each layer 7, and composition of headers of all layers.
M A ff+'J By realizing the transmission to the line by the sending device using hardware means, it has the advantage that software-based buffer management, packet composition, and transmission queue management of transmission packets can be omitted. This has the effect of reducing software processing and improving processing speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a communication control device showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example.

Claims (1)

[Claims] 1. A communication control device that executes a communication control protocol that has a layered structure, and includes means for parallel processing of the protocol using a multi-CPU configuration with one CPU per layer, and a buffer that stores the protocol header of each layer. a buffer pool formed independently for each CPU; a means for managing the buffer with hardware; a means for combining the protocol headers of each layer and sending this as one packet onto a line; A communication control device that has means for returning the buffer to the corresponding buffer pool, processes protocols in parallel by multiple CPUs, and implements an interface with an adjacent lower layer using hardware.