JPH05342172A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To efficiently execute the two kinds of the communication modes of broadcast communication and adjacent parallel communication. CONSTITUTION:This multiprocessor system is provided with the even number of three-state buffers 331-336, plural first buses 341-346 to connect these three- state buffers 331-336 in the shape of a ring, plural second buses connected to the buses between the respective adjacent three-state buffers in the state of wired OR, plural processors 311-316 to exchange data through the second buses to the first buses, and host computer to exchange data while selectively controlling the processors 311-316 and the three-state buffers 331-336 according to either broadcast communication or shift communication.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to interprocessor communication in a multiprocessor system, and is particularly used for those having two modes of broadcast communication by bus connection and parallel shift communication between adjacent processors by ring connection. Multiprocessor system.

[0002]

2. Description of the Related Art Conventional multiprocessor systems include
There are a bus connection type (Fig. 4) and a ring connection type (Fig. 5). In the case of the bus connection type, broadcast communication for transferring data from one transmitting processor to another receiving processor can be performed in one cycle.

[0003]

However, in the above-mentioned conventional multiprocessor system, when the communication data is shifted in parallel between the adjacent processors like the systolic array, the bus for each set of the transmission / reception processors is changed. It has to be divided and used inefficiently. On the other hand, in the case of the ring connection type, shift communication between adjacent processors (adjacent parallel communication) is possible in one cycle, which is suitable. However, the broadcast communication is inefficient because it takes (number of processors-1) cycles until data is transferred from one transmitting processor to the last receiving processor. For this reason, when a bus connection or ring connection is selected when configuring a multiprocessor system that uses two types of modes, that is, broadcast communication and adjacent parallel communication, the efficiency of either one of the communication modes is poor.

In view of the above problems, an object of the present invention is to provide a multiprocessor system capable of efficiently executing two types of communication modes of broadcast communication and adjacent parallel communication, and a processor suitable for constituting the multiprocessor system. Is to provide.

[0005]

In order to achieve the above object, a feature of the present invention is that in a multiprocessor system, an even number of three-state buffers and a plurality of first three-state buffers that connect the three-state buffers in a ring shape. Bus, a plurality of second buses connected to the bus between adjacent three-state buffers by wired OR, and a plurality of data exchanges with the first bus via the second bus, respectively. And a host computer that selectively controls the processor and the three-state buffer to perform the data exchange according to either broadcast communication or shift communication.

[0006]

According to the above-mentioned configuration, the host computer is configured to control the three-state buffer via the gate control function built in each of the processors. It is possible to efficiently execute two types of communication modes of parallel communication.

[0007]

1 shows a multiprocessor system according to an embodiment of the present invention. 311, 312, 313, 3 in the figure
14, 315, 316 are processors, 321, 322,
Reference numerals 323, 324, 325, and 326 denote processor input / output buses, and 331, 332, 333, 334, 335, and 33.
6 is a three-state buffer, 341, 342, 34
3, 344, 345 and 346 are buses between the three-state buffers. 32n processor input / output and 34n
The output of the three-state buffer is wired-ORed and input / output to / from the three-state buffer of the next stage. Also, the number of processors is even.

The operation of the entire system is controlled by a host computer 35 connected to these processors and buffers via control lines 361 and 362. The operation of this multiprocessor system will be described below.

First, the operation for broadcast communication will be described. First, the three-state buffer in the preceding stage of the processor that performs transmission is opened, and the other three-state buffers are closed. Next, the transmitting processor outputs communication data from the input / output, and the receiving processor puts the input / output in the input / output state. Then, since the three-state buffer in the preceding stage of the transmitting processor is open, the bus between the three-state buffers to which the input / output of the transmitting processor is wired-OR is driven by the transmitting processor to communication data. Further, since the three-state buffers other than the preceding stage of the transmitting processor are closed and the input / output of the receiving processor is in the input state, the bus between the three-state buffers is sequentially driven to communication data by the preceding three-state buffers. ..
This allows the receiving processor to capture the communication data.

For example, when the processor 314 is transmitting / receiving by another processor, the three-state buffer 33 is used.
4 is opened / other three state buffers are closed, and the transmission processor 314 outputs the communication data to the bus 344 between the three state buffers. Communication data is closed Three-state buffers 335, 33
Buses 345, 346, 341, 342 between the three-state buffers via 6, 331, 332, 333.
343, and receive processors 315, 31 respectively
6, 311, 312, 313. Since the three-state buffer 334 is open, communication data is not propagated anymore, and oscillation due to loopback is prevented. The consistency of the operation of each processor and the three-state buffer is managed by the host computer, and, for example, no two or more processors are in the output state at the same time.

That is, the host computer manages the mode of each processor so that one processor does not switch the communication mode without grasping the states of the other processors and the like. Regarding the consistency of the modes, there is a method of using a token as described later in an application example, in addition to the management by the host computer. However, in the case of the host computer method,
By opening the buffers 331 and 334 and closing the other buffers, the data transfer from the processor 331 to the processor 313 and the processor 31 are performed.
It is also possible to perform data transfer from 4 to the processor 316 at the same time.

Next, the operation for shift communication will be described. First, the three-state buffer is alternately opened / closed. Further, the processor in which the preceding three-state buffer is open outputs communication data from the input / output, and the processor in which the preceding three-state buffer is closed sets the input / output to the input state. Then, the bus between the three-state buffers in which the input / output of the transmitting processor is wired-OR is driven by the transmitting processor to communication data, and the bus between the three-state buffers in which the input / output of the receiving processor is wired-OR is the previous stage. It is driven by the communication data output from the transmission processor in the previous stage by the three-state buffer. As a result, the receiving processor can capture the communication data output from the preceding transmitting processor. Next, if the open / close of the three-state buffer is reversed and the transmission / reception of the processor is also switched, the processor transmitting previously can capture the communication data output from the processor in the preceding stage, and in the above two cycles. Shift communication of one open is performed. Again, each processor and
The consistency of the operation of the buffer is ensured by the host computer 35, and the shift communication is executed in correct synchronization.

For example, first, the three-state buffer 3
Open 31,333,335, 332,334,3
36 is closed, and processors 311, 313, 31
5 is transmitted and 312, 314, and 316 are received. The transmission processors 311, 313, 315 send the communication data to the buses 341, 34 between the three-state buffers, respectively.
Output to 3,345. The communication data includes three-state buffers 32, 334, and 3 that are closed.
Bus 34 between three-state buffers via 36
2,334,346 and receive processors 312,3
It is input to 14,316. Next, the three-state buffers 331, 333, 335 are closed, 332, 3
34,336 are opened and the processors 311 and 31
3, 315 is received and 312, 314, 316 are transmitted. The transmission processors 312, 314, and 316 send the communication data to the bus 34 between the three-state buffers, respectively.
2, 344, 346. The communication data is the three-state buffers 333 and 3 which are closed.
Three-state buffer 34 via 35,331
3, 345, 341 and receive processor 333, 3
35,331. From the above, the processor 3
11 to 312, 312 to 313, 313 to 31
Communication is made from 4, 314 to 315, 315 to 316, 316 to 311.

In the above embodiment, the control of the three-state buffer is performed by the host computer 35. However, the control line 361 is omitted and the processor 311 controls the buffer 331 and the processor 312 controls the buffer 332. May control the corresponding buffer.

An example of such a processor is shown in FIG.
In the figure, 41 and 42 are processors which are alternately arranged in the processors 311 to 316 of FIG. That is, for example, the processors 311, 313, 315 use the type 41 and the processors 312, 314, 316 use the type 43. However, when these processors are used, the control line 361 is not used. Reference numerals 411 and 421 denote core parts of the processor excluding the communication function and have normal processor functions. Reference numerals 4131 and 4231 denote communication status registers.
2, 4232 broadcast / shift communication status signals and 4133, 4233 broadcast communication transmission /
It is a control line that outputs a reception status signal to the gate control logic circuit. Input / output buses 412 and 421 of the processor are switched between input and output by the internal three-state buffers 4121 and 4221. The internal three-state buffer is opened / closed at the output of the gate control logic circuit. The output of the gate control logic circuit is inverted and output as a gate control signal (positive logic) of the corresponding three-state buffers 413 and 423 (for example, the buffer 331 of FIG. 1), and this signal of the preceding stage of the processor. Controls the three-state buffer. 414, 42
Reference numeral 4 denotes an input / output control input to the processor provided from the host computer 35, which is common to all the processors. However, in the processor 42, since the inverter 425 is provided, this control input is inverted. less than,
The operation of the multiprocessor system using these processors 41 and 42 will be described.

First, the case of broadcast communication will be described. In the transmitting processor, 4131 or 4
231, the communication status register is broadcast communication,
The transmission state is set, and the broadcast / shift communication state signal of 4132 or 4232 is the “L” level, 4133.
Alternatively, the broadcast communication transmission / reception status signal of 4233 becomes "L" level. Therefore, 4134 or 42
The output of the gate control logic circuit 34 is "H" level, the internal three-state buffer 4121 or 4221 is closed, and the gate control signal output of the external three-state buffer 413 or 423 is "L" level. As a result, the input / output of the transmitting processor is in the output state,
The three-state buffer in the preceding stage is in the high in-piece state.

In the case of receiving broadcast, 41
The communication status registers of 31 and 4231 are set to the broadcast communication and reception statuses, 4132 and 4232.
The broadcast / shift communication status signal of 1 is "L" level, and the broadcast communication transmission / reception status signals of 4133 and 4233 are "H" level. Therefore, 413
4 and 4234 gate control logic output is "L"
Level 4121 and 4221 internal three-state buffer buffer is oven 413 and 42
The output of the gate control signal of the external three-state buffer No. 3 becomes "H" level. As a result, the input / output of the receiving processor is in the input state, and the three-state buffer in the preceding stage is in the transfer state.

As described above, a communication path from the transmitting processor to all the receiving processors is secured.

Next, shift communication will be described. In all the processors, the communication status register of 4131 or 4231 becomes the shift communication status, and the broadcast / shift communication status signals of 4132 and 4232 become the “H” level.

When the input / output control input to each processor of 414 and 424 is at "H" level, the output of the gate control logic circuit of 4134 is "H" level, and the output of the gate control logic circuit of 4234 is "L" level. Then, the internal three-state buffer 4121 is closed, the internal three-state buffer 4221 is open, the gate control signal output of the external three-state buffer 413 is "L" level, and the gate control signal output of the external three-state buffer 423 is " H "level. Therefore, the input / output of the processor of 41 is in the output state, the input / output of the broadcast of 42 is in the input state, the three-state buffer in the preceding stage of the processor of 41 is in the high-in-piece state, and the three-state buffer in the stage of 42 processor is in the transfer state. Become. This will allow all 41 processors on the ring to
At the same time, a communication path to the processor at the subsequent stage 42 is secured.

When the input / output control input to each processor of 414 and 424 is at "L" level, the output of the gate control logic circuit of 4134 is at "L" level, and the output of the gate control logic circuit of 4234 is at "H" level. Then, the internal three-state buffer 4121 is open, the internal three-state buffer 4221 is closed, the gate control signal output of the external three-state buffer 413 is "H" level, and the gate control signal output of the external three-state buffer 423 is " Therefore, the input / output of the processor 41 is in the input state, the input / output of the processor 42 is in the output state, the three-state buffer before the processor 41 is in the transfer state, and the three-state buffer before the processor 42 is Is in high in-peace state, so all 42 From the processor, the communication path to 41 processors in its subsequent stage is ensured at the same time.

As described above, one cycle communication path for shift communication is secured for each H / L cycle of input / output control to the processor.

An application example of the multiprocessor system according to the present invention will be shown below. FIG. 3 shows a graphic system according to the present invention. In FIG. 3, 511, 512, 513, 51
A multi-chip compatible graphics processor 4 according to the present invention has a graphic drawing function. 521, 522, 52
Reference numeral 3,524 denotes an input / output bus for inter-processor communication, which is a bus 54 between three-state buffers in which three-state buffers 531,532,533,534 are connected in a ring shape.
1,542,543,544 are wired-ORed and connected. Reference numerals 551, 552, 553 and 554 are gate control signal outputs of the three-state buffer. 56
Reference numerals 1, 562, 563 and 564 denote frame memories having an interleave bank structure. 57 is a CPU bus, and each processor receives commands and data from the host system via this bus. 581, 582, 583
Reference numeral 584 denotes an input / output control input to the processor, which inverts every other common signal so that input / output during shift communication alternates and inputs / outputs. 59 is a CRT.

In this system, one graphics processor receives a graphic drawing command from the host system and performs preprocessing. The preprocessed graphics processor sends the resulting parameters to the other graphics processors, and each graphics processor writes to the bank of frame memory to which it is connected. As described above, drawing is performed in parallel in each bank.

In this system, there can be a plurality of graphics processors for performing preprocessing. Therefore, it is necessary to arbitrate the transmission of the pre-processing, but this can be realized by exchanging one logical transmission right token. For example, when some processors have completed preprocessing, the processor having the transmission right token transmits the parameter, and after the transmission and the processing resulting therefrom are completed, the transmission right token is transferred to the next processor. .. A processor that does not have the transmission right token holds the transmission until the transmission right token comes around. A processor that has a transmittal token but has not completed preprocessing,
Transfer the transfer right token to the next processor promptly. Transfer of the transfer right token is realized by setting the system to be in the broadcast communication state, stipulating that the processor having the transmission right token becomes the transmitting processor of the broadcast communication, and performing the broadcast communication with address specification. it can.

By the way, some parameters calculated by the preprocessing are common to the graphics processors of all banks, and some parameters need to be corrected according to the deviation of the banks. For example, in the case of straight line drawing, the ratio of horizontal / vertical displacement and the amount of change in the brightness value for each pixel in glow shading are information common to all banks,
The position of the first Vixel to be drawn and the absolute value of the brightness value there are information that differs from bank to bank.

However, in the latter case, since most of them are linear differences with respect to the horizontal position of the bank, it can be calculated by adding a constant to the nutrition method of the adjacent bank. For example, in glow shading, the pixel value I is expressed as I = Is + (dI / dX) * (X-Xs). Here, Is is the brightness value of the start pixel, dI / dX is the change amount of the brightness value for each pixel, X is the horizontal position of the pixel, and Xs is the horizontal position of the start pixel. The multiplication is realized by addition by the DDA. To enable this to be processed by DDA for each bank,
The following parameters may be given to each processor.

I = (Is + (dI / dX) × shift of bank) + ((dI / dX) × number of banks) × (X−Xs)
/ Bank number) "(dI / dX) x bank number" is a value common to all processors, and "(Is + (dI / dX) x bank deviation)" is corrected according to the bank deviation. It is a value.
However, in the latter case, the value of the processor in the previous stage is "(dI / d
X) ”is added.

Therefore, in this system, communication between the graphics processors is performed by transmitting the former by broadcast communication and the latter by shift communication. At this time, by complying with the multiprocessor system according to the present invention, both communication modes can be efficiently executed.

[0030]

The inter-processor communication speed in the graphic system shown in the embodiment of the present invention is estimated.

Broadcast Communication Logically, it is possible to communicate from the transmitting processor to all other receiving processors in one cycle. In terms of timing, since it passes through the three-state buffer of (the number of processors-1), it takes time for this gate delay. Although the gate delay is related to the load of the bus that drives the three-state buffer, in the multiprocessor system according to the present invention, the bus driven by each three-state buffer has one processor input / output and the next-stage three-state buffer. Since only buffers are connected, the bus load is constant regardless of the number of processors. Therefore, assuming that the gate delay per one three-state buffer is Td, the time T = To + Td * (number of processors-1) + Ts is required. Where T is the insertion communication cycle, To is the output delay of the transmitting processor, and Ts is the input setup time of the receiving processor. Actually, when TTL logic or the like is used for the three-state buffer, Td = 2
Since it is about 0 ns, a 4-processor system as in the embodiment can communicate at 80 ns + α.

On the other hand, according to the present invention, when the input and output are directly connected by the adjacent processors and connected in the ring shape,
Logically, (number of processors-1) cycles are required.
In terms of timing, it is high-speed because it is communication between processors directly connected, but a basic cycle of the processor is required, and when this is Tc, T = Tc * (number of processors-1) is required. However, T is a total communication cycle.
The basic cycle of a processor operating at 33 MHz is 3
0ns, so 240ns in a 4-processor system
It will hang. Further, in this case, since the input and output for communication are separated, the number of pins becomes large when the processor is made into an MPU.

Shift communication Logically, transmission / reception can be performed by all the processors in two cycles. Also in terms of timing, the speed is high because it only passes through the one-stage three-state buffer. The gate delay per three-state buffer is T
If d, then T = (To + Td + Ts) × 2. Where T is the total communication cycle, To is the output delay of the transmitting processor, and Ts is the input setup time of the receiving processor. If Td = about 20 ns, communication is possible at 40 ns + α regardless of the number of processors.

On the other hand, if all the processors are connected to one bus without using the present invention, logically, cycles corresponding to the number of processors are required. Also in terms of timing, as the number of processors increases, the load on the bus increases, making it difficult to complete the processing within the basic cycle of the processor. Assuming that the time required for one cycle is Tc, T = Tc × number of processors is required. However, T is a total communication cycle.
Since Tc depends on the number of processors, T is on the order of the square of the number of processors, and if Tc = 30 ns, a system of 4 processors requires 120 ns.

[Brief description of drawings]

FIG. 1 shows a multiprocessor system apparatus embodying the present invention.

FIG. 2 shows a processor used in the system according to the invention.

FIG. 3 shows an application example of a multiprocessor system according to the present invention.

FIG. 4 shows a conventional bus-connected multiprocessor system.

FIG. 5 shows a conventional ring-connected multiprocessor system.

[Explanation of symbols]

111,112,113,114,115,116 Processor 121,122,123,124,125,126 Processor input / output 13 Bus 211,212,213,214,215,216 Processor 221,222,223,224,225 , 226 Output of processor 311, 312, 313, 314, 315, 316 Processor 321, 322, 323, 324, 325, 326 Processor input / output 331, 332, 333, 334, 335, 336 Three-state buffer 341, 342 343, 344, 345, 346 Buses between three-state buffers 41,42 Processors 411,421 Processor cores 412,421 Processor inputs / outputs 4121,4221 Internal three-state buffers 413,423 Part Three-state buffer gate control signal output 4131, 4231 Communication status register 4132, 4232 Broadcast / shift communication status signal 4133, 4233 Broadcast communication send / receive status signal 4134, 4234 Gate control logic circuit 414, 424 Input / output control to processor Input 511, 512, 513, 514 Multi-chip compatible graphics processor according to the present invention 521, 522, 523, 524 Input / output for inter-processor communication 531, 532, 533, 534 Three-state buffer 541, 542, 543, 544 Three-state Bus between buffers 551,552,553,554 Gate control signal output of three-state buffer 561,562,563,564 Frame memory 57 CPU bus 58 , Input and output control input 59 CRT to 582,583,584 processor

Claims (2)

[Claims] 1. An even number of three-state buffers, a plurality of first buses connecting the three-state buffers in a ring shape, and a plurality of wired-OR connected to the buses between adjacent three-state buffers. A second bus, a plurality of processors each exchanging data with the first bus via the second bus, and the processor and the three-state buffer selectively according to either broadcast communication or shift communication A multiprocessor system comprising: a host computer for controlling the data exchange to exchange the data. 2. The multiprocessor system according to claim 1, wherein the host computer controls the three-state buffer via a gate control function built in each of the processors.