JPS6329867A - Dma controller - Google Patents

Abstract

PURPOSE:To attain DMA transfer between memories without sharply deteriorating the response of a CPU by counting the number of times of continuous DMA transfer, and when the count value coincides with a previously set up value enabling continuous DMA transfer, interrupting a DMA cycle and actuating the CPU. CONSTITUTION:When the count value 22 of a counter 15 coincides with the number 23 of continuous transfer data set up in a data number register 12, a coincidence signal 18 from a comparator 16 is activated, the output of an AND gate 25 is deactivated and a DMA control circuit 14 transfers its but using right to the CPU to activate CPU cycles 102, 104.... When the bus using right is transferred to the CPU and a DMA enabling signal 20 is deactivated, the contents of the counter 15 are cleared, a DMA request signal 19-1' is activated again and DMA is restarted. When the contents of a data counter register 11 are turned to zero, the bus using right is transferred to the CPU after the end of a DMA cycle 106 and a CPU cycle 107 is started.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention 1"j relates to a DMA controller, and particularly relates to a DMA controller having an inter-memory transfer function. [Prior Art] An example of the prior art is shown in FIG. 4. In the figure, 1' is DM
A controller outputs an external address bus I2, an external data bus 3, an external control signal 4, an external DMA%lIm signal 5. Address bus buffer 6, -r-Mebus buffer 7
, internal data bus 8, D mode/status register 9.D indicating the operating mode and status of the DMA controller 1'. D
Address counter/counter register 10 that holds the λIA transfer address. L) A data counter register 11 that holds the number of MA transfer data, a control timing circuit 13 that performs internal and external control of the DMA controller 1', and DMA-related control? The DMA control circuit 17 generates a transverse wave.

When performing data transfer between memory devices using DMA.

From the CPU to external address bus 2, external data bus 3, external control signal 4, area address count register 10, transfer source memory address and transfer destination memory address, all data count register; 5+11, transfer data count, and mode/status register. The transfer is started by setting the operation mode (in this case, memory-to-memory transfer mode) to the mode/status register 9 and inputting a start command to the mode/status register 9.

When the transfer starts, the external DMA control signal 5 is used to
Takes bus usage right from PU and sends DMA enable signal 20tl
-Activate the transfer source memory address from the address counter register 10 to the address bus buffer 6tl.
-Output to external address bus 2 and external control signal 4
A full reading instruction is given to the transfer memory to be built, and the data is written to the temporary register 24 via the booter external data bus 3 read from the transfer source memory and the data bus buffer 77% internal data bus 8. At this time, the transfer source memory address of the address counter register 10 is counted by the count clock 21 and becomes the next transfer source memory address.

Next, the transfer destination memory address from the address counter register 1o is outputted to the external address bus 2 through the address bus buffer 61'1, all transfer destination memories are selected, and all the data written in the temporary register 24 is written to the internal memory bus 8.
．． It is output to the external data bus 3 via the data bus buffer 7 and written to the transfer destination memory where it is processed as the external control signal 4.

At this time, the data counter register 11 also counts down at the same time as the next transfer destination memory address.

[Problem to be solved by the invention] The above-mentioned conventional DMA controller is , the flDMA controller controls the bus usage mt- until the transfer of the number of transfer data set in the data counter register 11 is completed.
In order to maintain the data, once the -degree transfer starts, the CPU cannot do anything until the transfer ends.

For this reason, there are disadvantages in that it is not possible to deal with cases where urgent processing is required, and in a system in which the CPU performs a dynamic train transfer MOI 77 refresh operation, there are disadvantages in that refreshment cannot be performed during DMA.

In addition, in order to avoid these drawbacks, if the number of data transferred at one time is set to a small number, the above-mentioned steps to the mode/status register 9, address count register 10, and data count register 11 will be reduced. This method has the disadvantage that the hub program becomes complicated because it tends to be necessary to transfer the entire set of parameters many times until the transfer is completed.

[Means for solving problems]

The DMA controller of the present invention includes a register that holds the number of data that can be continuously transferred, a counter that counts the number of consecutively transferred data, a comparison circuit that compares the count value from the counter and the value of the register, and a comparison circuit that compares the count value from the counter and the value of the register. When a match signal is received from the circuit, the error DMA transfer is interrupted and the right to use the bus'! After transferring to rcPU, 9DM will be given the right to use the bus again.
It has a control circuit that fully restarts A transfer.

[LOL example]

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a DMA controller according to an embodiment of the present invention.

The DMA controller 1 has an external address bus 2, an external data bus 3, an external control signal 4, and an external DMA control signal 5.
All communication with the outside of the F is performed, including an address bus buffer 6, a data bus buffer 7, an internal data bus 8, a mode/status register 9, an address counter register 10, a data counter register 11. Data number register 12. Control timing circuit 13. DMA control circuit】4.
Counter 15, comparison circuit 16, temporary register 24
and mutual exchange signals (18 to 23) Lr).

The external address bus 2 is used to specify registers inside the DMA controller 1 (hereinafter referred to as internal registers) and to select memory during DMA via an address bus buffer 6.
, the external data bus 3 is used for receiving and passing data to and from the internal register via the data bus buffer 7, and the external control signal 4 t'! It is used for sending information from the CPU to internal registers, for reading instructions, and for controlling memory and Ilo during DMA. The DMA control signal 5 is used to request DMA to the DMA controller 1 and to give and receive the right to use the bus between the DMA controller 1 and the CPU.

Mode/Status Register 9fl Depending on the operating mode and internal state of the DMA controller 1, the address count register 10 holds and counts the memory address during DMA transfer, and the data count register 11 holds and counts down the number of data to be transferred by DMA. .

The data number register 12 holds the number of data that can be transferred continuously, and the counter 15 controls the pDM by the DMA enable signal 20.
When ADMA transfer is started, the number of transfers is counted. 5 comparison circuit 16 is a counter 15
The count value is compared with the value of the data number register 12, and if they match, a match signal 18t- is output to the DMA control circuit 14.

The control timing circuit 13 receives an external control signal 4 from the CPU.
In addition to generating necessary control signals internally, %DM
During A, the necessary external control signal 4 is generated at the necessary timing, and the DMA control circuit 14 receives a DMA request from the outside,
It controls the transfer of bus usage rights to and from the F CPU and the execution of DMA cycles in response to DMA requests based on commands from the CPU.

Figure 2 shows the DMA control circuit 14F of Figure 1 - conventional DMA
AND gate 2 in the DMA control circuit 17 in the controller
5t- added and configured to show the next side, internal DMA request signal 19-1 from mode/status register 9
Then, it is gated with the match signal 18 from the comparison circuit 16 and becomes an internal DMA request signal 19-1'.

The DMA operation in the above configuration will be explained.

The necessary parameters from the CPU are stored in internal registers (9°10
．． 11, 12) and issues the DMA start command to activate the internal DMA in the internal status signal 19.
Request signal 19-1 becomes active. At this time, since the coincidence signal is not active, the DMA request signal 19-1'
becomes active, the DMA control circuit 14 obtains the right to use the bus from the CPU and starts a DMA cycle.

When a DMA cycle starts, the DMA enable signal 20 becomes active, and the counter 15 is not cleared.The n1 count clock 21 causes the address count register 10, data count register 11 .
The counter 15 performs a counting operation. Until the value of the data count register 11 becomes zero or the count value 22 of the counter 15 and the number of continuous transfer data 23 set in the data number register 12 become equal, the DMA cycle ( 101-1, 101-2...
...103-1 ...-105-1...
) is repeated.

Count value 22 of counter 15 and data number register 12
becomes equal to the number of continuous transfer data set to 23 (DMA cycle 101-n #103-n in FIG. 3...
) and the match signal 18 from the comparison circuit 16 become active, and in FIG. 2, the AND gate 25 output (DM
A request signal 19-1') becomes inactive and the DM
The A control circuit 14 transfers the right to use the bus to the kcPU, and the CPU cycles 102, 104, . . .
...becomes.

When the right to use the bus is transferred to the CPU and the DMA enable signal 20 is no longer active, the counter 15 is cleared.
Since No. 8 is no longer active, the DMA request signal 19-
1' becomes active again and DMA is restarted. Also, when the data counter register 11 becomes zero, the internal DM
Since the A request signal 19-1 is no longer active, the DMA
After cycle 106 ends, the right to use the bus is transferred to the CPU.C
PU cycle 107 starts at 0. Note that the execution of data transfer itself is the same as the operation of a conventional DMA controller.

〔Effect of the invention〕

In accordance with the above-described method, the present invention counts the number of consecutive DMA transfers in which the child is transferred.

When it becomes equal to a preset value that allows continuous DMA transfer, the entire DMA cycle is interrupted and the CPU's operation is not allowed, and urgent processing is performed during the interruption of the DMA cycle. Furthermore, by modifying the above settings, the CPU cycle and DMA cycle can be operated alternately, so DMA transfer between memories can be performed without significantly deteriorating the response of the CPU.

[Brief explanation of drawings]

Figure 1 is a block diagram of a DMA controller that is an embodiment of the present invention, the second cause is a block diagram of the DMA control circuit shown in Figure 1, and Figure 3 is a case where the DMA controller of Figure 1 is used. FIG. 4 is a block diagram of a conventional DMA controller. 1.1'...DMA controller, 2...
...External address bus, 3...External data bus, 4...External control signal, 5...External D
MA system a signal, 6...address bus buffer,
7...Data bus buffer, 8...Internal data bus, 9...Mode/status register, 10...Address counter register, 1
1...Data count register, 12...Data number register, 13...Control timing circuit, 14.17...DMA control circuit, 15...
...Counter, 16...Comparison circuit, 18...
...-matching signal, 19°19-2...internal status code, 19-1...internal DMA request signal, 19-1'...DMA request signal , 20...
... DMA enable signal, 21 ... Count clock, 22 ... Count value of counter 15. 23...Number of continuous transfer data, 24...
Temporary register% 25...AND gate, 100,102°104.107...CPU
Cycle, 100-1, 102-2--101-n, 1
03-1...-103-n, 105-1...
...106...DMA cycle. \-J' Cow /T21 Figure 2 Muscle Figure 3 Figure 4

Claims (1)

[Claims] D having a transfer function between a CPU and a memory connected to a bus
In the MA controller, there are a register that holds the number of data that can be transferred continuously, a counter that counts the number of continuously transferred data, and a comparison circuit that compares the number of data held in the register and the count value of the counter. and a controller having a control circuit that interrupts DMA transfer in response to a match signal from the comparison circuit, transfers the right to use the bus to the CPU, and then takes the right to use the bus again and restarts the DMA transfer.