JPS63283136A - Method for packaging circuit substrate - Google Patents

Method for packaging circuit substrate

Info

Publication number
JPS63283136A
JPS63283136A JP62118252A JP11825287A JPS63283136A JP S63283136 A JPS63283136 A JP S63283136A JP 62118252 A JP62118252 A JP 62118252A JP 11825287 A JP11825287 A JP 11825287A JP S63283136 A JPS63283136 A JP S63283136A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor element
film
circuit
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62118252A
Other languages
Japanese (ja)
Inventor
Yoshihiko Kasahara
笠原　良彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62118252A priority Critical patent/JPS63283136A/en
Publication of JPS63283136A publication Critical patent/JPS63283136A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To render a circuit module to be extremely thin by a method wherein an element installation position is a hole in a circuit board and a lining sheet or film capable of separation is bonded to one side of the circuit board. CONSTITUTION:At a position for the installation of a semiconductor element 3 on a circuit board 1, a hole is provided, which is large enough to accommodate the semiconductor element 3. For the fixation of the semiconductor element 3, a lining sheet or film 2 is bonded to a surface of the circuit board 1 opposite to the side whereon a circuit pattern 5 exists. The semiconductor element 3 is provisionally fixed to the film 2, connection is established by wire bonding or the like between the semiconductor element 3 and the pattern 5, sealing is accomplished by a sealing resin 6, and then the film 2 is peeled off the circuit board 1. In this way, a circuit board wherein a semiconductor element is fixed may be lessened in thickness and the element height after packaging may be reduced to the minimum, which results in an extremely thin circuit module.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は回路基板の実装方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for mounting a circuit board.

〔発明の概要〕[Summary of the invention]

本発明は回路基板の実装構造において、後工程で？り離
可能な裏打ち板又はフィルムを貼合せた回路基板にＩＣ
及び素子類を実装し、後に前記裏打ち板を♀りがすこと
により、回路基板の厚さが厚くなることなく、ＩＣ及び
素子類の実装高さを最小限に押え、容易に実装を行なえ
る様にしたものである。Is the present invention applicable in the later process in the circuit board mounting structure? IC is mounted on a circuit board with a removable backing plate or film attached.
By mounting the IC and elements and then peeling off the backing plate, the mounting height of the IC and elements can be minimized without increasing the thickness of the circuit board, and the mounting can be easily carried out. It was made in a similar manner.

〔従来の技術〕[Conventional technology]

従来の回路基板の実装構造は第２図、第３図の様に回路
基板上にＩＣチップを固定するか、回路基板の一部を座
ぐり加工した所にＩＣチップを固定しワイヤーボンディ
ング等により回路基板上の配線パターンとＩＣチップの
端子パッドとを接続させ、樹脂等により封止を行なうも
のであった。Conventional circuit board mounting structures include fixing the IC chip on the circuit board as shown in Figures 2 and 3, or fixing the IC chip in a counterbore in a part of the circuit board using wire bonding, etc. The wiring pattern on the circuit board and the terminal pad of the IC chip were connected and sealed with resin or the like.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、前述の従来技術では薄型回路モジュールを提供
するためには、回路基板を薄＜シ、ＩＣチップのチップ
厚を薄クシ、樹脂封止の封止厚を薄くするという様に構
成部品の厚みを薄くするというものであり、さらに薄型
を要求される回路モジュールに対しては、それぞれの部
品及び封止厚みの積算された厚み以下にすることができ
ない。However, in order to provide a thin circuit module with the above-mentioned conventional technology, it is necessary to reduce the thickness of the component parts by making the circuit board thinner, making the IC chip thinner, and reducing the resin sealing thickness. For circuit modules that are required to be even thinner, it is impossible to reduce the thickness to less than the cumulative thickness of each component and the sealing thickness.

そこで本発明はこの様な問題点を解決するもので、その
目的とするところは、超薄型回路モジュールを提供する
ところにある。The present invention is intended to solve these problems, and its purpose is to provide an ultra-thin circuit module.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の回路基板の実装方法は、半導体素子及び集積回
路用チップ素子を電気的接続を行なうための設置部を穴
構造として、回路モジュールの前記素子部の厚みを薄く
する様回路基板に設け、前記素子を設置する前に回路基
板の一方の面に、後に？す離可能な裏打ち板、もしくは
裏打ちフィルムを貼り付け、これにより前記素子の設置
穴を座ぐり加工をほどこした基板の様にし前記素子を保
持させ、電気的接続及び樹脂による封止等実装を行ない
、その後に前記裏打ち仮６しくは裏打ちフィルムを♀り
離することを特徴とする。The circuit board mounting method of the present invention includes providing a mounting part for electrically connecting a semiconductor element and an integrated circuit chip element with a hole structure on the circuit board so as to reduce the thickness of the element part of the circuit module. Before installing said element on one side of the circuit board, and after? A removable backing plate or a backing film is pasted, and this makes the installation hole for the element look like a board with counterbore processing to hold the element, and electrical connections and sealing with resin are performed. , and then the temporary lining 6 or the lining film is removed.

〔実施例〕〔Example〕

第１図は本発明の実施例における回路基板の実装構造の
断面図である。この実施例において回路基板１は半導体
素子３を配置する位置に素子を埋設させるに十分な穴加
工を施しである。そして半導体素子３を実装するために
素子を固定させ又保持させるため裏打ち仮もしくは、裏
打ちフィルムを回路基板１０半導体素子３との接続を行
なう回路パターン５の面と反対側の面に貼り付ける。裏
打ちフィルムとしては、たとえば後工程で熱を受ける場
合は接看剤付のポリイミドフィルム等の耐熱フィルム、
熱の彩りがない様な場合はポリエステルフィルム等が考
えられる。又、貼り付ける部分については素子部に限ら
ず回路基板と同一の形状で貼り付けることも考えられる
。特に素子が数箇所にある様な場合育効である。そして
裏打ちフィルムに素子を仮固定しワイヤーボンディング
等により半導体素子３と回路パターン５を接続させ封止
用樹脂６により封止を行ない後に裏打ち板もしくは、裏
打ちフィルム２を回路基板１から剥離する。この時回路
基板側に応力がかからない様な接看力の弱い接着剤又は
粘着剤であることが望ましい。半導体素子３を、固定す
る場合この接着剤又は粘着剤によって仮固定させること
もできる。FIG. 1 is a sectional view of a circuit board mounting structure in an embodiment of the present invention. In this embodiment, the circuit board 1 has sufficient holes drilled to embed the semiconductor element 3 at the position where the semiconductor element 3 is to be placed. Then, to mount the semiconductor element 3, a temporary lining or a lining film is pasted on the surface of the circuit board 10 opposite to the surface of the circuit pattern 5 to be connected to the semiconductor element 3 in order to fix and hold the element. As the backing film, for example, if it will be subjected to heat in the subsequent process, a heat-resistant film such as a polyimide film with adhesive, etc.
If there is no heat color, polyester film etc. may be considered. Further, the part to be pasted is not limited to the element part, but it is also conceivable to paste it in the same shape as the circuit board. This is particularly effective when the elements are located in several locations. Then, the element is temporarily fixed to the backing film, the semiconductor element 3 and the circuit pattern 5 are connected by wire bonding, etc., and sealed with a sealing resin 6. After that, the backing plate or the backing film 2 is peeled off from the circuit board 1. At this time, it is desirable to use an adhesive or adhesive with a weak contact force that does not apply stress to the circuit board side. When fixing the semiconductor element 3, it can also be temporarily fixed using this adhesive or adhesive.

第５図は集積回路用チップ素子の実装方法であり回路基
板１に間けられたチップ素子埋設用穴に対して貼られた
裏打ちフィルムに前記チップ素子を仮固定、又は保持し
半田により回路パターンと接続させる。そして裏打ちフ
ィルムを回路基板から剥離させることにより、より薄い
回路モジュールを提供することができる。FIG. 5 shows a method for mounting a chip element for an integrated circuit, in which the chip element is temporarily fixed or held on a backing film pasted to the hole for burying the chip element formed in the circuit board 1, and the circuit pattern is formed by soldering. Connect with. By peeling the backing film from the circuit board, a thinner circuit module can be provided.

第６図は回路基板に多層配線板を用いた例であり、裏打
ちフィルムを奢りがした状態の図である。FIG. 6 shows an example in which a multilayer wiring board is used as a circuit board, with the backing film removed.

第７図は１￥５図により得られた回路モジュールである
。Fig. 7 shows a circuit module obtained by Fig. 1\5.

〔発明の効果〕〔Effect of the invention〕

以上述べたように発明によれば回路基板の半導体素子及
び集積回路用チップ素子を固定し保持するための基材の
厚さを減らすことができ、又そのために前記素子を実装
した高さを最小限にし、なおかつ実装を行なう工程につ
いては従来の座ぐり基板又は回路基板上への実装と変わ
りなく行なうことができる。これらにより超薄型回路モ
ジュールを提供できるという効果を存する。As described above, according to the invention, it is possible to reduce the thickness of the base material for fixing and holding the semiconductor elements and integrated circuit chip elements of the circuit board, and for this purpose, the height of the mounted elements can be reduced to a minimum. Moreover, the mounting process can be carried out in the same way as mounting on a conventional counterbore board or circuit board. These have the advantage that an ultra-thin circuit module can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の回路基板の実装方法の一実施例を示す
主要断面図。 第２図、第３図は従来技術の実装方法を示す主要断面図
。 第４図、第６図、第７図は本発明の実装方法により得ら
れた回路モジュールの断面図。 第５図は本発明のチップ素子の場合の実装方法を示す主
要断面図である。 １・・・・・・回路基板 ２・・・・・・裏打ちフィルム ３・・・・・・半導体素子 ４・・・・・・導体 ５・・・・・・回路パターン ６・・・・・・封止樹脂 ７・・・・・・絶縁用レジスト ８・・・・・・集積回路用チップ素子 ９・・・・・・半田 １０・・・・・・回路基板（多層基板）以　　上 ｆ 第２図 第９図 第ｆ図 第１図FIG. 1 is a main sectional view showing an embodiment of the circuit board mounting method of the present invention. FIGS. 2 and 3 are main sectional views showing a conventional mounting method. 4, 6, and 7 are cross-sectional views of circuit modules obtained by the mounting method of the present invention. FIG. 5 is a main cross-sectional view showing a mounting method for the chip element of the present invention. 1... Circuit board 2... Backing film 3... Semiconductor element 4... Conductor 5... Circuit pattern 6... - Sealing resin 7... Insulating resist 8... Integrated circuit chip element 9... Solder 10... Circuit board (multilayer board) and above f Figure 2 Figure 9 Figure f Figure 1

Claims (1)

【特許請求の範囲】[Claims] 　半導体素子及び集積回路用チップ素子の電気的接続を
行なうための回路基板において前記素子の埋没設置する
穴に対して回路基板の一方の面に、前記素子の実装の後
に剥離可能な裏打ち板もしくは裏打ちフィルムを貼り付
け前記素子の実装を行ない、その後前記裏打ち板又は裏
打ちフィルムを剥離することを特徴とする回路基板の実
装方法。In a circuit board for electrically connecting semiconductor elements and chip elements for integrated circuits, a backing plate or lining that can be peeled off after mounting the elements is provided on one side of the circuit board for the holes in which the elements are installed. A method for mounting a circuit board, comprising: pasting a film to mount the element, and then peeling off the backing plate or backing film.
JP62118252A 1987-05-15 1987-05-15 Method for packaging circuit substrate Pending JPS63283136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62118252A JPS63283136A (en) 1987-05-15 1987-05-15 Method for packaging circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62118252A JPS63283136A (en) 1987-05-15 1987-05-15 Method for packaging circuit substrate

Publications (1)

Publication Number Publication Date
JPS63283136A true JPS63283136A (en) 1988-11-21

Family

ID=14732007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62118252A Pending JPS63283136A (en) 1987-05-15 1987-05-15 Method for packaging circuit substrate

Country Status (1)

Country Link
JP (1) JPS63283136A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
EP0623956A3 (en) * 1993-05-04 1995-03-22 Motorola Inc A semiconductor device having no die supporting surface and method for making the same.
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
US6033933A (en) * 1997-02-14 2000-03-07 Lg Semicon Co., Ltd Method for attaching a removable tape to encapsulate a semiconductor package
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
EP1914803A1 (en) * 2006-10-20 2008-04-23 Broadcom Corporation Low profile ball grid array (BGA) package witth exposed die and method of making same

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
EP0623956A3 (en) * 1993-05-04 1995-03-22 Motorola Inc A semiconductor device having no die supporting surface and method for making the same.
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US6294830B1 (en) * 1996-04-18 2001-09-25 Tessera, Inc. Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US6856235B2 (en) 1996-04-18 2005-02-15 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US7165316B2 (en) 1996-04-18 2007-01-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US6033933A (en) * 1997-02-14 2000-03-07 Lg Semicon Co., Ltd Method for attaching a removable tape to encapsulate a semiconductor package
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
US6888168B2 (en) 1997-02-18 2005-05-03 Tessera, Inc. Semiconductor package having light sensitive chips
US7095054B2 (en) 1997-02-18 2006-08-22 Tessera, Inc. Semiconductor package having light sensitive chips
EP1914803A1 (en) * 2006-10-20 2008-04-23 Broadcom Corporation Low profile ball grid array (BGA) package witth exposed die and method of making same
US8169067B2 (en) 2006-10-20 2012-05-01 Broadcom Corporation Low profile ball grid array (BGA) package with exposed die and method of making same

Similar Documents

Publication Publication Date Title
US6426564B1 (en) Recessed tape and method for forming a BGA assembly
JP2501019B2 (en) Flexible circuit board
US6045655A (en) Method of mounting a connection component on a semiconductor chip with adhesives
US4231154A (en) Electronic package assembly method
JP3238004B2 (en) Method for manufacturing semiconductor device
US20010049156A1 (en) Low-pin-count chip package and manufacturing method thereof
KR20010072583A (en) Laminated integrated circuit package
JPH04277636A (en) Preparation of semiconductor device
US5109601A (en) Method of marking a thin film package
KR100413027B1 (en) Tape carrier package and manufacturing method for the same
JPS63283136A (en) Method for packaging circuit substrate
JP2781019B2 (en) Semiconductor device and manufacturing method thereof
US6101098A (en) Structure and method for mounting an electric part
US4965700A (en) Thin film package for mixed bonding of chips
JP2001053413A (en) Substrate incorporating electronic parts, multilayered substrate incorporating electronic parts, and their manufacture
US4460224A (en) Foldable circuit assembly
JPH0342860A (en) Flexible printed wiring board
JPS63283035A (en) Circuit board
JP3331146B2 (en) Manufacturing method of BGA type semiconductor device
JPS6294970A (en) Film carrier lsi
JPH02222598A (en) Semiconductor device module
JP2822987B2 (en) Electronic circuit package assembly and method of manufacturing the same
JP2823189B2 (en) Semiconductor device
JPH05226839A (en) Manufacture of multilayered circuit board
JP3257931B2 (en) Semiconductor package, method of manufacturing the same, and semiconductor device